IT8324251A0 - Memoria impiegante linee di indirizzo di riga e colonna multiplate. - Google Patents

Memoria impiegante linee di indirizzo di riga e colonna multiplate.

Info

Publication number
IT8324251A0
IT8324251A0 IT8324251A IT2425183A IT8324251A0 IT 8324251 A0 IT8324251 A0 IT 8324251A0 IT 8324251 A IT8324251 A IT 8324251A IT 2425183 A IT2425183 A IT 2425183A IT 8324251 A0 IT8324251 A0 IT 8324251A0
Authority
IT
Italy
Prior art keywords
multiplate
row
memory
column address
address lines
Prior art date
Application number
IT8324251A
Other languages
English (en)
Other versions
IT8324251A1 (it
IT1173689B (it
Inventor
Austin Charles Dumbri
Frank John Procyk
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of IT8324251A0 publication Critical patent/IT8324251A0/it
Publication of IT8324251A1 publication Critical patent/IT8324251A1/it
Application granted granted Critical
Publication of IT1173689B publication Critical patent/IT1173689B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
IT24251/83A 1982-12-22 1983-12-19 Memoria impiegante linee di indirizzo di riga e colonna multiplate IT1173689B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/452,155 US4541078A (en) 1982-12-22 1982-12-22 Memory using multiplexed row and column address lines

Publications (3)

Publication Number Publication Date
IT8324251A0 true IT8324251A0 (it) 1983-12-19
IT8324251A1 IT8324251A1 (it) 1985-06-19
IT1173689B IT1173689B (it) 1987-06-24

Family

ID=23795276

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24251/83A IT1173689B (it) 1982-12-22 1983-12-19 Memoria impiegante linee di indirizzo di riga e colonna multiplate

Country Status (8)

Country Link
US (1) US4541078A (it)
EP (1) EP0129578A1 (it)
KR (1) KR840007196A (it)
CA (1) CA1204510A (it)
ES (1) ES8407615A1 (it)
GB (1) GB2132799A (it)
IT (1) IT1173689B (it)
WO (1) WO1984002608A1 (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5954096A (ja) * 1982-09-22 1984-03-28 Hitachi Ltd ダイナミツク型ｍｏｓｒａｍ
US4675808A (en) * 1983-08-08 1987-06-23 American Telephone And Telegraph Company At&T Bell Laboratories Multiplexed-address interface for addressing memories of various sizes
US5191555A (en) * 1990-07-31 1993-03-02 Texas Instruments, Incorporated Cmos single input buffer for multiplexed inputs
KR930008838A (ko) * 1991-10-31 1993-05-22 김광호 어드레스 입력 버퍼
US6072735A (en) * 1998-06-22 2000-06-06 Lucent Technologies, Inc. Built-in redundancy architecture for computer memories
KR100382555B1 (ko) * 2001-03-09 2003-05-09 주식회사 하이닉스반도체 반도체 메모리 소자의 데이터 입출력 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760384A (en) * 1970-10-27 1973-09-18 Cogar Corp Fet memory chip including fet devices therefor and fabrication method
US3806880A (en) * 1971-12-02 1974-04-23 North American Rockwell Multiplexing system for address decode logic
US4050061A (en) * 1976-05-03 1977-09-20 Texas Instruments Incorporated Partitioning of MOS random access memory array
JPS6023432B2 (ja) * 1977-12-09 1985-06-07 株式会社日立製作所 Ｍｏｓメモリ
US4200917A (en) * 1979-03-12 1980-04-29 Motorola, Inc. Quiet column decoder
DE2948159C2 (de) * 1979-11-29 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Integrierter Speicherbaustein mit wählbaren Betriebsfunktionen
JPS57118599U (it) * 1981-01-14 1982-07-23

Also Published As

Publication number Publication date
GB2132799A (en) 1984-07-11
KR840007196A (ko) 1984-12-05
IT8324251A1 (it) 1985-06-19
IT1173689B (it) 1987-06-24
CA1204510A (en) 1986-05-13
US4541078A (en) 1985-09-10
ES528170A0 (es) 1984-10-01
ES8407615A1 (es) 1984-10-01
EP0129578A1 (en) 1985-01-02
GB8332967D0 (en) 1984-01-18
WO1984002608A1 (en) 1984-07-05

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