IT8423868A0 - Circuito eliminatore delle condizioni di imballo. - Google Patents

Circuito eliminatore delle condizioni di imballo.

Info

Publication number
IT8423868A0
IT8423868A0 IT8423868A IT2386884A IT8423868A0 IT 8423868 A0 IT8423868 A0 IT 8423868A0 IT 8423868 A IT8423868 A IT 8423868A IT 2386884 A IT2386884 A IT 2386884A IT 8423868 A0 IT8423868 A0 IT 8423868A0
Authority
IT
Italy
Prior art keywords
eliminating circuit
packaging conditions
conditions eliminating
packaging
circuit
Prior art date
Application number
IT8423868A
Other languages
English (en)
Other versions
IT8423868A1 (it
IT1178686B (it
Inventor
George K Tarleton
Original Assignee
Gte Communication Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Communication Syst filed Critical Gte Communication Syst
Publication of IT8423868A0 publication Critical patent/IT8423868A0/it
Publication of IT8423868A1 publication Critical patent/IT8423868A1/it
Application granted granted Critical
Publication of IT1178686B publication Critical patent/IT1178686B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
IT23868/84A 1983-12-05 1984-12-03 Circuito eliminatore delle condizioni di imballo IT1178686B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/558,227 US4544850A (en) 1983-12-05 1983-12-05 Race condition mediator circuit

Publications (3)

Publication Number Publication Date
IT8423868A0 true IT8423868A0 (it) 1984-12-03
IT8423868A1 IT8423868A1 (it) 1986-06-03
IT1178686B IT1178686B (it) 1987-09-16

Family

ID=24228691

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23868/84A IT1178686B (it) 1983-12-05 1984-12-03 Circuito eliminatore delle condizioni di imballo

Country Status (4)

Country Link
US (1) US4544850A (it)
BE (1) BE901191A (it)
CA (1) CA1215135A (it)
IT (1) IT1178686B (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8401629A (nl) * 1984-05-22 1985-12-16 Philips Nv Elektrische schakeling met een faseregelkring.
US4786824A (en) * 1984-05-24 1988-11-22 Kabushiki Kaisha Toshiba Input signal level detecting circuit
US4980577A (en) * 1987-06-18 1990-12-25 Advanced Micro Devices, Inc. Dual triggered edge-sensitive asynchrounous flip-flop
US4999528A (en) * 1989-11-14 1991-03-12 Keech Eugene E Metastable-proof flip-flop
US5045801A (en) * 1990-05-29 1991-09-03 The United States Of America As Represented By The Secretary Of The Air Force Metastable tolerant asynchronous interface
US6631506B1 (en) * 2002-04-02 2003-10-07 Hewlett-Packard Development Company, L.P. Method and apparatus for identifying switching race conditions in a circuit design

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3912947A (en) * 1974-07-05 1975-10-14 Motorola Inc Mos data bus control circuitry
JPS6051749B2 (ja) * 1979-08-31 1985-11-15 富士通株式会社 エラ−訂正方式
SE422263B (sv) * 1980-03-11 1982-02-22 Ericsson Telefon Ab L M Forfarande och anordning for synkronisering av en biner datasignal
US4380736A (en) * 1981-05-04 1983-04-19 Motorola, Inc. Peripheral interface adapter circuit for counter synchronization

Also Published As

Publication number Publication date
BE901191A (fr) 1985-03-29
IT8423868A1 (it) 1986-06-03
CA1215135A (en) 1986-12-09
IT1178686B (it) 1987-09-16
US4544850A (en) 1985-10-01

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