IT971839B - Processo per la fabbricazione di dispositivi monolitici con tran sistori isolati - Google Patents
Processo per la fabbricazione di dispositivi monolitici con tran sistori isolatiInfo
- Publication number
- IT971839B IT971839B IT32876/72A IT3287672A IT971839B IT 971839 B IT971839 B IT 971839B IT 32876/72 A IT32876/72 A IT 32876/72A IT 3287672 A IT3287672 A IT 3287672A IT 971839 B IT971839 B IT 971839B
- Authority
- IT
- Italy
- Prior art keywords
- isolated
- manufacture
- monolithic devices
- tran sistors
- sistors
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/137—Collector regions of BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
- H10W15/01—Manufacture or treatment
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH105572A CH536028A (de) | 1972-01-25 | 1972-01-25 | Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT971839B true IT971839B (it) | 1974-05-10 |
Family
ID=4201392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT32876/72A IT971839B (it) | 1972-01-25 | 1972-12-14 | Processo per la fabbricazione di dispositivi monolitici con tran sistori isolati |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS4886490A (it) |
| CA (1) | CA992218A (it) |
| CH (1) | CH536028A (it) |
| DE (1) | DE2300412A1 (it) |
| FR (1) | FR2169069A1 (it) |
| IT (1) | IT971839B (it) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2532694B2 (ja) * | 1989-11-22 | 1996-09-11 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US5049521A (en) * | 1989-11-30 | 1991-09-17 | Silicon General, Inc. | Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate |
-
1972
- 1972-01-25 CH CH105572A patent/CH536028A/de not_active IP Right Cessation
- 1972-12-14 IT IT32876/72A patent/IT971839B/it active
- 1972-12-22 JP JP47128274A patent/JPS4886490A/ja active Pending
-
1973
- 1973-01-02 CA CA160,404A patent/CA992218A/en not_active Expired
- 1973-01-05 DE DE2300412A patent/DE2300412A1/de active Pending
- 1973-01-09 FR FR7301492A patent/FR2169069A1/fr not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| FR2169069A1 (it) | 1973-09-07 |
| CA992218A (en) | 1976-06-29 |
| JPS4886490A (it) | 1973-11-15 |
| DE2300412A1 (de) | 1973-08-02 |
| CH536028A (de) | 1973-04-15 |
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