IT989316B - Unita aritmetica e logica parti colarmente per sistemi di calcolo - Google Patents

Unita aritmetica e logica parti colarmente per sistemi di calcolo

Info

Publication number
IT989316B
IT989316B IT25620/73A IT2562073A IT989316B IT 989316 B IT989316 B IT 989316B IT 25620/73 A IT25620/73 A IT 25620/73A IT 2562073 A IT2562073 A IT 2562073A IT 989316 B IT989316 B IT 989316B
Authority
IT
Italy
Prior art keywords
colarly
arithmetic unit
logic parts
calculation systems
calculation
Prior art date
Application number
IT25620/73A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT989316B publication Critical patent/IT989316B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Error Detection And Correction (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
IT25620/73A 1972-07-31 1973-06-20 Unita aritmetica e logica parti colarmente per sistemi di calcolo IT989316B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US27633972A 1972-07-31 1972-07-31

Publications (1)

Publication Number Publication Date
IT989316B true IT989316B (it) 1975-05-20

Family

ID=23056251

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25620/73A IT989316B (it) 1972-07-31 1973-06-20 Unita aritmetica e logica parti colarmente per sistemi di calcolo

Country Status (6)

Country Link
US (1) US3752394A (it)
JP (1) JPS5228612B2 (it)
CA (1) CA1001307A (it)
DE (1) DE2335661A1 (it)
FR (1) FR2331262A5 (it)
IT (1) IT989316B (it)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3811039A (en) * 1973-02-05 1974-05-14 Honeywell Inf Systems Binary arithmetic, logical and shifter unit
DE2352686B2 (de) * 1973-10-20 1978-05-11 Vereinigte Flugtechnische Werke- Fokker Gmbh, 2800 Bremen Dezimaler Parallel-Addierer/Substrahierer
CH1130374A4 (it) * 1974-08-19 1977-03-31
US3958112A (en) * 1975-05-09 1976-05-18 Honeywell Information Systems, Inc. Current mode binary/bcd arithmetic array
US4001570A (en) * 1975-06-17 1977-01-04 International Business Machines Corporation Arithmetic unit for a digital data processor
US4125867A (en) * 1976-10-27 1978-11-14 Texas Instruments Incorporated Electronic calculator or microprocessor having a hexadecimal/binary coded decimal arithmetic unit
US4118786A (en) * 1977-01-10 1978-10-03 International Business Machines Corporation Integrated binary-BCD look-ahead adder
US4592005A (en) * 1982-07-06 1986-05-27 Sperry Corporation Masked arithmetic logic unit
US4644489A (en) * 1984-02-10 1987-02-17 Prime Computer, Inc. Multi-format binary coded decimal processor with selective output formatting
US5513362A (en) * 1992-04-23 1996-04-30 Matsushita Electric Industrial Co., Ltd. Method of and apparatus for normalization of a floating point binary number
RU2145112C1 (ru) * 1998-05-26 2000-01-27 Воронежский государственный университет Устройство для сложения и вычитания чисел по модулю
RU2156998C1 (ru) * 1999-02-02 2000-09-27 Воронежский государственный технический университет Устройство для сложения и вычитания чисел по модулю
RU2220441C1 (ru) * 2002-04-17 2003-12-27 Воронежский государственный технический университет Устройство для сложения n чисел по модулю p
TWI259356B (en) * 2004-03-26 2006-08-01 Infortrend Technology Inc Apparatus for checking data coherence, controller and storage system having the same and method therefore is disclosed

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3310786A (en) * 1964-06-30 1967-03-21 Ibm Data compression/expansion and compressed data processing
US3596074A (en) * 1969-06-12 1971-07-27 Ibm Serial by character multifunctional modular unit
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system

Also Published As

Publication number Publication date
DE2335661A1 (de) 1974-02-21
FR2331262A5 (fr) 1977-06-03
JPS5228612B2 (it) 1977-07-27
JPS4953741A (it) 1974-05-24
US3752394A (en) 1973-08-14
CA1001307A (en) 1976-12-07

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