ITMI20020931A0 - Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore - Google Patents

Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore

Info

Publication number
ITMI20020931A0
ITMI20020931A0 IT2002MI000931A ITMI20020931A ITMI20020931A0 IT MI20020931 A0 ITMI20020931 A0 IT MI20020931A0 IT 2002MI000931 A IT2002MI000931 A IT 2002MI000931A IT MI20020931 A ITMI20020931 A IT MI20020931A IT MI20020931 A0 ITMI20020931 A0 IT MI20020931A0
Authority
IT
Italy
Prior art keywords
manufactureing
semiconductor substrate
electronic circuits
integrated electronic
integrated
Prior art date
Application number
IT2002MI000931A
Other languages
English (en)
Inventor
Simone Alba
Roberto Colombo
Francesco Ciovacco
Chiara Savardi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2002MI000931A priority Critical patent/ITMI20020931A1/it
Publication of ITMI20020931A0 publication Critical patent/ITMI20020931A0/it
Priority to EP03009600.2A priority patent/EP1361603B1/en
Priority to US10/428,338 priority patent/US6998348B2/en
Publication of ITMI20020931A1 publication Critical patent/ITMI20020931A1/it
Priority to US11/294,763 priority patent/US20060073651A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H10P76/2043—Photolithographic processes using an anti-reflective coating
IT2002MI000931A 2002-05-02 2002-05-02 Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore ITMI20020931A1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT2002MI000931A ITMI20020931A1 (it) 2002-05-02 2002-05-02 Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore
EP03009600.2A EP1361603B1 (en) 2002-05-02 2003-04-29 Method for manufacturing electronic circuits integrated on a semiconductor substrate
US10/428,338 US6998348B2 (en) 2002-05-02 2003-05-01 Method for manufacturing electronic circuits integrated on a semiconductor substrate
US11/294,763 US20060073651A1 (en) 2002-05-02 2005-12-06 Method for manufacturing electronic circuits integrated on a semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2002MI000931A ITMI20020931A1 (it) 2002-05-02 2002-05-02 Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore

Publications (2)

Publication Number Publication Date
ITMI20020931A0 true ITMI20020931A0 (it) 2002-05-02
ITMI20020931A1 ITMI20020931A1 (it) 2003-11-03

Family

ID=11449819

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2002MI000931A ITMI20020931A1 (it) 2002-05-02 2002-05-02 Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore

Country Status (3)

Country Link
US (2) US6998348B2 (it)
EP (1) EP1361603B1 (it)
IT (1) ITMI20020931A1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMI20020931A1 (it) * 2002-05-02 2003-11-03 St Microelectronics Srl Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore
ITMI20022785A1 (it) 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
ITMI20022784A1 (it) 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
KR100700283B1 (ko) * 2005-12-28 2007-03-26 동부일렉트로닉스 주식회사 반도체소자의 소자분리용 트랜치 형성방법
US7838432B2 (en) * 2007-04-16 2010-11-23 Applied Materials, Inc. Etch process with controlled critical dimension shrink
JP2010041028A (ja) 2008-07-11 2010-02-18 Tokyo Electron Ltd 基板処理方法
JP5180121B2 (ja) * 2009-02-20 2013-04-10 東京エレクトロン株式会社 基板処理方法
JP2010283213A (ja) * 2009-06-05 2010-12-16 Tokyo Electron Ltd 基板処理方法
US9229326B2 (en) * 2014-03-14 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US20180323078A1 (en) * 2015-12-24 2018-11-08 Intel Corporation Pitch division using directed self-assembly

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DE3275447D1 (en) * 1982-07-03 1987-03-19 Ibm Deutschland Process for the formation of grooves having essentially vertical lateral silicium walls by reactive ion etching
DE3686721D1 (de) * 1986-10-08 1992-10-15 Ibm Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.
WO1993018715A1 (en) * 1992-03-20 1993-09-30 The General Hospital Corporation Laser illuminator
US5716494A (en) * 1992-06-22 1998-02-10 Matsushita Electric Industrial Co., Ltd. Dry etching method, chemical vapor deposition method, and apparatus for processing semiconductor substrate
US6040247A (en) * 1995-01-10 2000-03-21 Lg Semicon Co., Ltd. Method for etching contact
US5525542A (en) * 1995-02-24 1996-06-11 Motorola, Inc. Method for making a semiconductor device having anti-reflective coating
US5910453A (en) * 1996-01-16 1999-06-08 Advanced Micro Devices, Inc. Deep UV anti-reflection coating etch
US5750441A (en) * 1996-05-20 1998-05-12 Micron Technology, Inc. Mask having a tapered profile used during the formation of a semiconductor device
US5670401A (en) * 1996-08-22 1997-09-23 Vanguard International Semiconductor Corporation Method for fabricating a deep submicron mosfet device using an in-situ polymer spacer to decrease device channel length
EP0871213A3 (en) * 1997-03-27 1999-03-03 Siemens Aktiengesellschaft Method for producing vias having variable sidewall profile
US5994228A (en) * 1997-04-11 1999-11-30 Vanguard International Semiconductor Corporation Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes
JP3905232B2 (ja) * 1997-12-27 2007-04-18 東京エレクトロン株式会社 エッチング方法
KR100272510B1 (ko) * 1997-12-30 2000-12-01 김영환 반도체 소자의 콘택홀 형성방법
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ITMI20020931A1 (it) * 2002-05-02 2003-11-03 St Microelectronics Srl Metodo per fabbricare circuiti elettronici integrati su un substrato semiconduttore

Also Published As

Publication number Publication date
US6998348B2 (en) 2006-02-14
EP1361603A3 (en) 2004-04-14
ITMI20020931A1 (it) 2003-11-03
EP1361603A2 (en) 2003-11-12
US20060073651A1 (en) 2006-04-06
US20040029307A1 (en) 2004-02-12
EP1361603B1 (en) 2019-07-24

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