ITMI20031643A1 - Circuito ad anello ad aggancio di ritardo per correggere - Google Patents
Circuito ad anello ad aggancio di ritardo per correggereInfo
- Publication number
- ITMI20031643A1 ITMI20031643A1 IT001643A ITMI20031643A ITMI20031643A1 IT MI20031643 A1 ITMI20031643 A1 IT MI20031643A1 IT 001643 A IT001643 A IT 001643A IT MI20031643 A ITMI20031643 A IT MI20031643A IT MI20031643 A1 ITMI20031643 A1 IT MI20031643A1
- Authority
- IT
- Italy
- Prior art keywords
- correct
- ring circuit
- latch attachment
- latch
- attachment
- Prior art date
Links
- 238000010615 ring circuit Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Dram (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0060814A KR100486268B1 (ko) | 2002-10-05 | 2002-10-05 | 내부에서 자체적으로 듀티싸이클 보정을 수행하는지연동기루프 회로 및 이의 듀티싸이클 보정방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ITMI20031643A1 true ITMI20031643A1 (it) | 2004-04-06 |
Family
ID=32026121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT001643A ITMI20031643A1 (it) | 2002-10-05 | 2003-08-08 | Circuito ad anello ad aggancio di ritardo per correggere |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7184509B2 (it) |
| JP (1) | JP4447874B2 (it) |
| KR (1) | KR100486268B1 (it) |
| CN (1) | CN100530968C (it) |
| DE (1) | DE10336300B4 (it) |
| IT (1) | ITMI20031643A1 (it) |
| TW (1) | TWI281321B (it) |
Families Citing this family (99)
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| KR20190068033A (ko) * | 2017-12-08 | 2019-06-18 | 삼성전자주식회사 | 지연 고정 루프 회로 및 지연 고정 루프 회로의 구동 방법 |
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| CN113852370B (zh) * | 2020-06-28 | 2026-03-03 | 深圳市中兴微电子技术有限公司 | 一种相位抖动补偿方法、模块和数字锁相环 |
| CN113972910B (zh) * | 2020-07-24 | 2025-07-04 | 瑞昱半导体股份有限公司 | 频率控制装置与频率控制方法 |
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| US6570944B2 (en) * | 2001-06-25 | 2003-05-27 | Rambus Inc. | Apparatus for data recovery in a synchronous chip-to-chip system |
| JPS6481526A (en) * | 1987-09-24 | 1989-03-27 | Nec Corp | Dll circuit |
| AU1841895A (en) * | 1994-02-15 | 1995-08-29 | Rambus Inc. | Delay-locked loop |
| US5810900A (en) | 1995-01-18 | 1998-09-22 | Owens-Brockway Glass Container Inc. | Method and apparatus for delivering a cased glass stream |
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| US6125157A (en) | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
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| US6133861A (en) * | 1998-05-20 | 2000-10-17 | Marvell Technology Group | Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel |
| KR100520658B1 (ko) * | 1998-06-30 | 2005-11-30 | 주식회사 하이닉스반도체 | 디지털 듀티율 정정 회로 |
| KR100366618B1 (ko) * | 2000-03-31 | 2003-01-09 | 삼성전자 주식회사 | 클럭 신호의 듀티 사이클을 보정하는 지연 동기 루프 회로및 지연 동기 방법 |
| KR100360403B1 (ko) * | 2000-04-10 | 2002-11-13 | 삼성전자 주식회사 | 듀티 싸이클 보정회로 및 방법 |
| US7042971B1 (en) * | 2001-06-12 | 2006-05-09 | Lsi Logic Corporation | Delay-locked loop with built-in self-test of phase margin |
| US6731147B2 (en) * | 2001-10-29 | 2004-05-04 | Cypress Semiconductor Corp. | Method and architecture for self-clocking digital delay locked loop |
| US6671652B2 (en) * | 2001-12-26 | 2003-12-30 | Hewlett-Packard Devlopment Company, L.P. | Clock skew measurement circuit on a microprocessor die |
| US6911853B2 (en) * | 2002-03-22 | 2005-06-28 | Rambus Inc. | Locked loop with dual rail regulation |
-
2002
- 2002-10-05 KR KR10-2002-0060814A patent/KR100486268B1/ko not_active Expired - Fee Related
-
2003
- 2003-07-14 US US10/619,821 patent/US7184509B2/en not_active Expired - Fee Related
- 2003-07-25 TW TW092120445A patent/TWI281321B/zh not_active IP Right Cessation
- 2003-07-31 DE DE10336300A patent/DE10336300B4/de not_active Expired - Fee Related
- 2003-08-08 IT IT001643A patent/ITMI20031643A1/it unknown
- 2003-08-08 CN CNB031277217A patent/CN100530968C/zh not_active Expired - Fee Related
- 2003-09-24 JP JP2003331074A patent/JP4447874B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7184509B2 (en) | 2007-02-27 |
| JP2004129255A (ja) | 2004-04-22 |
| JP4447874B2 (ja) | 2010-04-07 |
| TWI281321B (en) | 2007-05-11 |
| DE10336300A1 (de) | 2004-04-15 |
| KR100486268B1 (ko) | 2005-05-03 |
| TW200414686A (en) | 2004-08-01 |
| KR20040031389A (ko) | 2004-04-13 |
| DE10336300B4 (de) | 2006-03-02 |
| US20040066873A1 (en) | 2004-04-08 |
| CN100530968C (zh) | 2009-08-19 |
| CN1487669A (zh) | 2004-04-07 |
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