ITMI20041988A1 - "metodo e sistema per la fornitura di rilevazione in un dispositivo di memoria a banchi multipli." - Google Patents
"metodo e sistema per la fornitura di rilevazione in un dispositivo di memoria a banchi multipli."Info
- Publication number
- ITMI20041988A1 ITMI20041988A1 IT001988A ITMI20041988A ITMI20041988A1 IT MI20041988 A1 ITMI20041988 A1 IT MI20041988A1 IT 001988 A IT001988 A IT 001988A IT MI20041988 A ITMI20041988 A IT MI20041988A IT MI20041988 A1 ITMI20041988 A1 IT MI20041988A1
- Authority
- IT
- Italy
- Prior art keywords
- delivery
- detection
- memory device
- multiple bench
- bench memory
- Prior art date
Links
- 238000001514 detection method Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT001988A ITMI20041988A1 (it) | 2004-10-20 | 2004-10-20 | "metodo e sistema per la fornitura di rilevazione in un dispositivo di memoria a banchi multipli." |
| US11/123,544 US7430150B2 (en) | 2004-10-20 | 2005-05-05 | Method and system for providing sensing circuitry in a multi-bank memory device |
| PCT/US2005/037546 WO2006044942A2 (en) | 2004-10-20 | 2005-10-18 | Method and system for providing sensing circuitry in a multi-bank memory device |
| TW94136654A TWI290716B (en) | 2004-10-20 | 2005-10-20 | Method and system for providing sensing circuitry in a multi-bank memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT001988A ITMI20041988A1 (it) | 2004-10-20 | 2004-10-20 | "metodo e sistema per la fornitura di rilevazione in un dispositivo di memoria a banchi multipli." |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ITMI20041988A1 true ITMI20041988A1 (it) | 2005-01-20 |
Family
ID=36180596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT001988A ITMI20041988A1 (it) | 2004-10-20 | 2004-10-20 | "metodo e sistema per la fornitura di rilevazione in un dispositivo di memoria a banchi multipli." |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7430150B2 (it) |
| IT (1) | ITMI20041988A1 (it) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7539062B2 (en) * | 2006-12-20 | 2009-05-26 | Micron Technology, Inc. | Interleaved memory program and verify method, device and system |
| US7414891B2 (en) | 2007-01-04 | 2008-08-19 | Atmel Corporation | Erase verify method for NAND-type flash memories |
| US7882405B2 (en) * | 2007-02-16 | 2011-02-01 | Atmel Corporation | Embedded architecture with serial interface for testing flash memories |
| US20080232169A1 (en) * | 2007-03-20 | 2008-09-25 | Atmel Corporation | Nand-like memory array employing high-density nor-like memory devices |
| US7746692B2 (en) * | 2008-01-31 | 2010-06-29 | Agere Systems Inc. | Multiple-level memory with analog read |
| WO2012102785A2 (en) * | 2011-01-27 | 2012-08-02 | Rambus Inc. | Memory cell with multiple sense mechanisms |
| JP2014149889A (ja) * | 2013-01-31 | 2014-08-21 | Toshiba Corp | 半導体記憶装置 |
| US11854609B2 (en) * | 2021-08-27 | 2023-12-26 | Qualcomm Incorporated | Memory with reduced capacitance at a sense amplifier |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2190260C2 (ru) * | 1994-06-02 | 2002-09-27 | Интел Корпорейшн | Считывающая схема для флэш-памяти с многоуровневыми ячейками |
| US6442644B1 (en) * | 1997-08-11 | 2002-08-27 | Advanced Memory International, Inc. | Memory system having synchronous-link DRAM (SLDRAM) devices and controller |
| EP0997912B1 (en) * | 1998-10-20 | 2006-01-11 | STMicroelectronics S.r.l. | Device for reading nonvolatile memory cells, in particular analog flash memory cells |
| US6275407B1 (en) * | 1999-06-29 | 2001-08-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device having sense and data lines for use to read and write operations |
| AU8000200A (en) * | 1999-10-08 | 2001-04-23 | Aplus Flash Technology, Inc. | Multiple level flash memory |
| US6697282B1 (en) * | 2000-09-29 | 2004-02-24 | Intel Corporation | Reference voltage generator employing large flash memory cells coupled to threshold tuning devices |
| JP2003223792A (ja) * | 2002-01-25 | 2003-08-08 | Hitachi Ltd | 不揮発性メモリ及びメモリカード |
| JP4225749B2 (ja) * | 2002-08-07 | 2009-02-18 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
-
2004
- 2004-10-20 IT IT001988A patent/ITMI20041988A1/it unknown
-
2005
- 2005-05-05 US US11/123,544 patent/US7430150B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US7430150B2 (en) | 2008-09-30 |
| US20060083097A1 (en) | 2006-04-20 |
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