ITRM20010530A1 - Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco. - Google Patents

Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco.

Info

Publication number
ITRM20010530A1
ITRM20010530A1 IT2001RM000530A ITRM20010530A ITRM20010530A1 IT RM20010530 A1 ITRM20010530 A1 IT RM20010530A1 IT 2001RM000530 A IT2001RM000530 A IT 2001RM000530A IT RM20010530 A ITRM20010530 A IT RM20010530A IT RM20010530 A1 ITRM20010530 A1 IT RM20010530A1
Authority
IT
Italy
Prior art keywords
sector
bench
flash memory
marking
cancellation
Prior art date
Application number
IT2001RM000530A
Other languages
English (en)
Inventor
Giovanni Naso
Giovanni Santin
Pasquale Pistilli
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to IT2001RM000530A priority Critical patent/ITRM20010530A1/it
Publication of ITRM20010530A0 publication Critical patent/ITRM20010530A0/it
Priority to US10/229,921 priority patent/US6717862B2/en
Publication of ITRM20010530A1 publication Critical patent/ITRM20010530A1/it
Priority to US10/706,133 priority patent/US6909641B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
IT2001RM000530A 2001-08-31 2001-08-31 Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco. ITRM20010530A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT2001RM000530A ITRM20010530A1 (it) 2001-08-31 2001-08-31 Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco.
US10/229,921 US6717862B2 (en) 2001-08-31 2002-08-28 Flash memory sector tagging for consecutive sector erase or bank erase
US10/706,133 US6909641B2 (en) 2001-08-31 2003-11-12 Flash memory sector tagging for consecutive sector erase or bank erase

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001RM000530A ITRM20010530A1 (it) 2001-08-31 2001-08-31 Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco.

Publications (2)

Publication Number Publication Date
ITRM20010530A0 ITRM20010530A0 (it) 2001-08-31
ITRM20010530A1 true ITRM20010530A1 (it) 2003-02-28

Family

ID=11455758

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001RM000530A ITRM20010530A1 (it) 2001-08-31 2001-08-31 Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco.

Country Status (2)

Country Link
US (2) US6717862B2 (it)
IT (1) ITRM20010530A1 (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITRM20010530A1 (it) * 2001-08-31 2003-02-28 Micron Technology Inc Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco.
ITRM20010556A1 (it) * 2001-09-12 2003-03-12 Micron Technology Inc Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.
KR100543929B1 (ko) * 2003-11-10 2006-01-23 주식회사 하이닉스반도체 반도체 메모리 소자의 뱅크 액티브/프리차지 커맨드 디코더
US7064985B2 (en) * 2004-05-27 2006-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Source line driver
KR100645047B1 (ko) * 2004-10-12 2006-11-10 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 고속 프로그램 방법
US7433790B2 (en) * 2005-06-06 2008-10-07 Standard Microsystems Corporation Automatic reference voltage trimming technique
US7751242B2 (en) * 2005-08-30 2010-07-06 Micron Technology, Inc. NAND memory device and programming methods
US7260019B1 (en) * 2005-10-31 2007-08-21 Spansion Llc Memory array
KR100669349B1 (ko) * 2005-12-02 2007-01-16 삼성전자주식회사 플래시 메모리 장치 및 그것의 읽기 방법
US7512015B1 (en) 2006-07-17 2009-03-31 Lattice Semiconductor Corporation Negative voltage blocking for embedded memories
US7636259B1 (en) 2006-07-17 2009-12-22 Lallice Semiconductor Corporation Flash memory array with independently erasable sectors
US7643352B2 (en) * 2008-06-03 2010-01-05 Elite Semiconductor Memory Technology Inc. Method for erasing flash memory
JP4746699B1 (ja) * 2010-01-29 2011-08-10 株式会社東芝 半導体記憶装置及びその制御方法
US9007860B2 (en) 2013-02-28 2015-04-14 Micron Technology, Inc. Sub-block disabling in 3D memory
US10877687B2 (en) 2018-06-29 2020-12-29 Micron Technology, Inc. Erasure of multiple blocks in memory devices
CN111061649B (zh) * 2019-10-28 2023-09-29 宁波三星智能电气有限公司 一种存储器的存储空间自适应分配方法
US12373255B2 (en) * 2022-12-30 2025-07-29 Advanced Micro Devices, Inc. Systems and methods for sharing memory across clusters of directly connected nodes

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0935255A2 (en) * 1989-04-13 1999-08-11 SanDisk Corporation Flash EEPROM system
DE69026653T2 (de) 1989-07-11 1997-01-09 Harmonic Lightwaves Inc Optische Sender, linearisiert durch parametrische Rückkopplung
US5270979A (en) * 1991-03-15 1993-12-14 Sundisk Corporation Method for optimum erasing of EEPROM
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US7071060B1 (en) * 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
US5657332A (en) * 1992-05-20 1997-08-12 Sandisk Corporation Soft errors handling in EEPROM devices
JP2647312B2 (ja) * 1992-09-11 1997-08-27 インターナショナル・ビジネス・マシーンズ・コーポレイション 一括消去型不揮発性半導体記憶装置
US5798968A (en) * 1996-09-24 1998-08-25 Sandisk Corporation Plane decode/virtual sector architecture
US5850305A (en) 1996-12-18 1998-12-15 Scientific-Atlanta, Inc. Adaptive predistortion control for optical external modulation
US6175891B1 (en) * 1997-04-23 2001-01-16 Micron Technology, Inc. System and method for assigning addresses to memory devices
US6021459A (en) * 1997-04-23 2000-02-01 Micron Technology, Inc. Memory system having flexible bus structure and method
US5974499A (en) * 1997-04-23 1999-10-26 Micron Technology, Inc. Memory system having read modify write function and method
US6016270A (en) * 1998-03-06 2000-01-18 Alliance Semiconductor Corporation Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations
US6055184A (en) * 1998-09-02 2000-04-25 Texas Instruments Incorporated Semiconductor memory device having programmable parallel erase operation
ITRM20010530A1 (it) * 2001-08-31 2003-02-28 Micron Technology Inc Marcatura di settore di memoria flash per consecutiva cancellazione in settore o banco.

Also Published As

Publication number Publication date
US6717862B2 (en) 2004-04-06
US20040240253A1 (en) 2004-12-02
US6909641B2 (en) 2005-06-21
ITRM20010530A0 (it) 2001-08-31
US20030063500A1 (en) 2003-04-03

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