ITRM20040257A1 - Metodo e sistema per comunicazioni dati su un "chip". - Google Patents

Metodo e sistema per comunicazioni dati su un "chip".

Info

Publication number
ITRM20040257A1
ITRM20040257A1 IT000257A ITRM20040257A ITRM20040257A1 IT RM20040257 A1 ITRM20040257 A1 IT RM20040257A1 IT 000257 A IT000257 A IT 000257A IT RM20040257 A ITRM20040257 A IT RM20040257A IT RM20040257 A1 ITRM20040257 A1 IT RM20040257A1
Authority
IT
Italy
Prior art keywords
chip
data communications
communications
data
Prior art date
Application number
IT000257A
Other languages
English (en)
Inventor
Frederick A Perner
Kenneth K Smith
Original Assignee
Hewlett Packard Development Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co filed Critical Hewlett Packard Development Co
Publication of ITRM20040257A1 publication Critical patent/ITRM20040257A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
IT000257A 2003-05-23 2004-05-21 Metodo e sistema per comunicazioni dati su un "chip". ITRM20040257A1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/444,477 US6956762B2 (en) 2003-05-23 2003-05-23 Method and system for data communication on a chip

Publications (1)

Publication Number Publication Date
ITRM20040257A1 true ITRM20040257A1 (it) 2004-08-21

Family

ID=33450669

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000257A ITRM20040257A1 (it) 2003-05-23 2004-05-21 Metodo e sistema per comunicazioni dati su un "chip".

Country Status (4)

Country Link
US (2) US6956762B2 (it)
JP (1) JP4137841B2 (it)
DE (1) DE102004004885B4 (it)
IT (1) ITRM20040257A1 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7038941B2 (en) * 2003-12-19 2006-05-02 Hewlett-Packard Development Company, L.P. Magnetic memory storage device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US6395991B1 (en) * 1996-07-29 2002-05-28 International Business Machines Corporation Column grid array substrate attachment with heat sink stress relief
US6256224B1 (en) * 2000-05-03 2001-07-03 Hewlett-Packard Co Write circuit for large MRAM arrays
US6053394A (en) * 1998-01-13 2000-04-25 International Business Machines Corporation Column grid array substrate attachment with heat sink stress relief
US6269027B1 (en) * 1998-04-14 2001-07-31 Honeywell, Inc. Non-volatile storage latch
US6400009B1 (en) * 1999-10-15 2002-06-04 Lucent Technologies Inc. Hermatic firewall for MEMS packaging in flip-chip bonded geometry
US6461881B1 (en) * 2000-06-08 2002-10-08 Micron Technology, Inc. Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
US6493259B1 (en) * 2000-08-14 2002-12-10 Micron Technology, Inc. Pulse write techniques for magneto-resistive memories
JP4726292B2 (ja) * 2000-11-14 2011-07-20 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
US6836429B2 (en) * 2002-12-07 2004-12-28 Hewlett-Packard Development Company, L.P. MRAM having two write conductors

Also Published As

Publication number Publication date
DE102004004885A1 (de) 2004-12-30
US7142448B2 (en) 2006-11-28
JP4137841B2 (ja) 2008-08-20
DE102004004885B4 (de) 2009-02-26
US20040233710A1 (en) 2004-11-25
JP2004348944A (ja) 2004-12-09
US20050281078A1 (en) 2005-12-22
US6956762B2 (en) 2005-10-18

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