ITRM20070167A1 - Non-volatile multilevel memory cell programming - Google Patents

Non-volatile multilevel memory cell programming

Info

Publication number
ITRM20070167A1
ITRM20070167A1 IT000167A ITRM20070167A ITRM20070167A1 IT RM20070167 A1 ITRM20070167 A1 IT RM20070167A1 IT 000167 A IT000167 A IT 000167A IT RM20070167 A ITRM20070167 A IT RM20070167A IT RM20070167 A1 ITRM20070167 A1 IT RM20070167A1
Authority
IT
Italy
Prior art keywords
memory cell
multilevel memory
cell programming
volatile multilevel
volatile
Prior art date
Application number
IT000167A
Other languages
English (en)
Inventor
Violante Moschiano
Massimo Rossini
Giovanni Santin
Tommaso Vali
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to IT000167A priority Critical patent/ITRM20070167A1/it
Priority to US12/038,445 priority patent/US7692971B2/en
Priority to KR1020097020150A priority patent/KR101117413B1/ko
Priority to CN2008800099166A priority patent/CN101652815B/zh
Priority to PCT/US2008/004114 priority patent/WO2008121351A1/en
Publication of ITRM20070167A1 publication Critical patent/ITRM20070167A1/it
Priority to US12/718,290 priority patent/US7944757B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5625—Self-converging multilevel programming

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
IT000167A 2007-03-27 2007-03-27 Non-volatile multilevel memory cell programming ITRM20070167A1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT000167A ITRM20070167A1 (it) 2007-03-27 2007-03-27 Non-volatile multilevel memory cell programming
US12/038,445 US7692971B2 (en) 2007-03-27 2008-02-27 Non-volatile multilevel memory cell programming
KR1020097020150A KR101117413B1 (ko) 2007-03-27 2008-03-28 레벨당 2개 이상의 검증 전압들로 프로그래밍하는 비휘발성 멀티레벨 메모리 셀
CN2008800099166A CN101652815B (zh) 2007-03-27 2008-03-28 每级具有多于两个检验电压的非易失性多级存储器单元编程
PCT/US2008/004114 WO2008121351A1 (en) 2007-03-27 2008-03-28 Non-volatile multilevel memory cell programming with more than two verify voltages per level
US12/718,290 US7944757B2 (en) 2007-03-27 2010-03-05 Non-volatile multilevel memory cell programming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000167A ITRM20070167A1 (it) 2007-03-27 2007-03-27 Non-volatile multilevel memory cell programming

Publications (1)

Publication Number Publication Date
ITRM20070167A1 true ITRM20070167A1 (it) 2008-09-29

Family

ID=39794028

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000167A ITRM20070167A1 (it) 2007-03-27 2007-03-27 Non-volatile multilevel memory cell programming

Country Status (5)

Country Link
US (2) US7692971B2 (it)
KR (1) KR101117413B1 (it)
CN (1) CN101652815B (it)
IT (1) ITRM20070167A1 (it)
WO (1) WO2008121351A1 (it)

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US8767487B2 (en) * 2010-03-02 2014-07-01 Micron Technology, Inc. Drain select gate voltage management
US8305820B2 (en) * 2010-04-29 2012-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Switched capacitor based negative bitline voltage generation scheme
US8472256B2 (en) 2010-05-12 2013-06-25 Micron Technology, Inc. Non-volatile memory programming
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US8385123B2 (en) * 2010-08-18 2013-02-26 Micron Technology, Inc. Programming to mitigate memory cell performance differences
KR101184830B1 (ko) * 2010-10-27 2012-09-20 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
US8385132B2 (en) 2010-12-22 2013-02-26 Sandisk Technologies Inc. Alternate bit line bias during programming to reduce channel to floating gate coupling in memory
US8917553B2 (en) 2011-03-25 2014-12-23 Micron Technology, Inc. Non-volatile memory programming
US8711619B2 (en) 2011-10-18 2014-04-29 Seagate Technology Llc Categorizing bit errors of solid-state, non-volatile memory
US8760932B2 (en) 2011-10-18 2014-06-24 Seagate Technology Llc Determination of memory read reference and programming voltages
US8737133B2 (en) 2011-10-18 2014-05-27 Seagate Technology Llc Shifting cell voltage based on grouping of solid-state, non-volatile memory cells
US8693257B2 (en) 2011-10-18 2014-04-08 Seagate Technology Llc Determining optimal read reference and programming voltages for non-volatile memory using mutual information
US9251907B2 (en) 2012-04-03 2016-02-02 Micron Technology, Inc. Memory devices and methods of operating memory devices including applying a potential to a source and a select gate between the source and a string of memory cells while performing a program operation on a memory cell in the string
US8842477B2 (en) * 2012-06-01 2014-09-23 Spansion Llc Method, apparatus, and manufacture for flash memory adaptive algorithm
KR101942863B1 (ko) 2012-06-19 2019-01-28 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 프로그램 방법
US9082510B2 (en) * 2012-09-14 2015-07-14 Freescale Semiconductor, Inc. Non-volatile memory (NVM) with adaptive write operations
US9135109B2 (en) 2013-03-11 2015-09-15 Seagate Technology Llc Determination of optimum threshold voltage to read data values in memory cells
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US9633719B2 (en) 2015-05-29 2017-04-25 Micron Technology, Inc. Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
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CN110910940B (zh) * 2018-09-18 2021-10-29 北京兆易创新科技股份有限公司 存储器的编程方法、装置、存储设备和存储介质
US10539973B1 (en) * 2018-12-17 2020-01-21 Micron Technology, Inc. Low-voltage bias generator based on high-voltage supply
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CN110140174B (zh) * 2019-03-26 2021-02-19 长江存储科技有限责任公司 用于通过施加多个位线偏置电压在非易失性存储器器件中编程的方法
US11335418B2 (en) * 2019-12-30 2022-05-17 Micron Technology, Inc. Memory device including dynamic programming voltage
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US11532367B2 (en) * 2020-12-08 2022-12-20 Micron Technology, Inc. Managing programming convergence associated with memory cells of a memory sub-system
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Also Published As

Publication number Publication date
US20100165739A1 (en) 2010-07-01
WO2008121351A1 (en) 2008-10-09
CN101652815B (zh) 2012-09-05
KR20090119919A (ko) 2009-11-20
CN101652815A (zh) 2010-02-17
US7944757B2 (en) 2011-05-17
US20080239806A1 (en) 2008-10-02
US7692971B2 (en) 2010-04-06
KR101117413B1 (ko) 2012-02-29

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