ITTO20010086A0 - Procedimento per sigillare e connettere parti di microsistemi elettromeccanici, fluidi, ottici e dispositivo cosi' ottenuto. - Google Patents

Procedimento per sigillare e connettere parti di microsistemi elettromeccanici, fluidi, ottici e dispositivo cosi' ottenuto.

Info

Publication number
ITTO20010086A0
ITTO20010086A0 IT2001TO000086A ITTO20010086A ITTO20010086A0 IT TO20010086 A0 ITTO20010086 A0 IT TO20010086A0 IT 2001TO000086 A IT2001TO000086 A IT 2001TO000086A IT TO20010086 A ITTO20010086 A IT TO20010086A IT TO20010086 A0 ITTO20010086 A0 IT TO20010086A0
Authority
IT
Italy
Prior art keywords
electromechanical
fluids
sealing
procedure
connecting parts
Prior art date
Application number
IT2001TO000086A
Other languages
English (en)
Inventor
Ubaldo Mastromatteo
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2001TO000086A priority Critical patent/ITTO20010086A1/it
Publication of ITTO20010086A0 publication Critical patent/ITTO20010086A0/it
Priority to US10/060,068 priority patent/US7531897B2/en
Publication of ITTO20010086A1 publication Critical patent/ITTO20010086A1/it
Priority to US12/417,461 priority patent/US8050011B2/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/093—Conductive package seal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/285—Alignment aids, e.g. alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/161—Aligning
    • H10W80/168—Aligning using guiding structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Fluid-Pressure Circuits (AREA)
IT2001TO000086A 2001-01-30 2001-01-30 Procedimento per sigillare e connettere parti di microsistemi elettromeccanici, fluidi, ottici e dispositivo cosi' ottenuto. ITTO20010086A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT2001TO000086A ITTO20010086A1 (it) 2001-01-30 2001-01-30 Procedimento per sigillare e connettere parti di microsistemi elettromeccanici, fluidi, ottici e dispositivo cosi' ottenuto.
US10/060,068 US7531897B2 (en) 2001-01-30 2002-01-29 Process for sealing and connecting parts of electromechanical, fluid and optical microsystems and device obtained thereby
US12/417,461 US8050011B2 (en) 2001-01-30 2009-04-02 Process for sealing and connecting parts of electromechanical, fluid and optical microsystems and device obtained thereby

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001TO000086A ITTO20010086A1 (it) 2001-01-30 2001-01-30 Procedimento per sigillare e connettere parti di microsistemi elettromeccanici, fluidi, ottici e dispositivo cosi' ottenuto.

Publications (2)

Publication Number Publication Date
ITTO20010086A0 true ITTO20010086A0 (it) 2001-01-30
ITTO20010086A1 ITTO20010086A1 (it) 2002-07-30

Family

ID=11458481

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001TO000086A ITTO20010086A1 (it) 2001-01-30 2001-01-30 Procedimento per sigillare e connettere parti di microsistemi elettromeccanici, fluidi, ottici e dispositivo cosi' ottenuto.

Country Status (2)

Country Link
US (2) US7531897B2 (it)
IT (1) ITTO20010086A1 (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070042491A (ko) * 2003-12-19 2007-04-23 인터내셔널 비지네스 머신즈 코포레이션 미소 전자기계 시스템의 부품들을 자동 정렬하기 위한 방법및 시스템
DE102005027276B3 (de) * 2005-06-08 2007-01-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer Stapelanordnung
WO2007012991A1 (en) * 2005-07-25 2007-02-01 Koninklijke Philips Electronics, N.V. Interconnection and packaging method for biomedical devices with electronic and fluid functions
KR20120091691A (ko) * 2011-02-09 2012-08-20 삼성전자주식회사 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법
WO2012171663A1 (en) * 2011-06-15 2012-12-20 Eth Zurich Low-temperature wafer-level packaging and direct electrical interconnection
US9570421B2 (en) 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
DE102014210852B4 (de) * 2014-06-06 2022-10-06 Robert Bosch Gmbh Bauteil mit zwei Halbleiter-Bauelementen, die über eine strukturierte Bond-Verbindungsschicht miteinander verbunden sind, und Verfahren zum Herstellen eines solchen Bauteils
ITUA20164673A1 (it) 2016-06-27 2017-12-27 St Microelectronics Srl Dispositivo mems formato da almeno due strati strutturali incollati reciprocamente e relativo processo di fabbricazione
CN108100986B (zh) * 2016-11-24 2020-01-31 上海新微技术研发中心有限公司 一种共晶键合方法和半导体器件
US10381330B2 (en) * 2017-03-28 2019-08-13 Silicon Storage Technology, Inc. Sacrificial alignment ring and self-soldering vias for wafer bonding
US10998480B2 (en) * 2018-09-19 2021-05-04 Facebook Technologies, Llc Light-emitting structure alignment preservation in display fabrication
FI131218B1 (en) 2023-10-30 2024-12-10 Kyocera Tech Oy Device and method for centering bonding force

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4784970A (en) * 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor
US5343064A (en) * 1988-03-18 1994-08-30 Spangler Leland J Fully integrated single-crystal silicon-on-insulator process, sensors and circuits
US5236118A (en) * 1992-05-12 1993-08-17 The Regents Of The University Of California Aligned wafer bonding
JP3151956B2 (ja) * 1992-09-04 2001-04-03 株式会社村田製作所 加速度センサ
US6570221B1 (en) * 1993-07-27 2003-05-27 Hyundai Electronics America Bonding of silicon wafers
FR2718571B1 (fr) * 1994-04-08 1996-05-15 Thomson Csf Composant hybride semiconducteur.
US5633535A (en) * 1995-01-27 1997-05-27 Chao; Clinton C. Spacing control in electronic device assemblies
US6137164A (en) * 1998-03-16 2000-10-24 Texas Instruments Incorporated Thin stacked integrated circuit device
US6291875B1 (en) * 1998-06-24 2001-09-18 Analog Devices Imi, Inc. Microfabricated structures with electrical isolation and interconnections
WO2000002014A1 (en) * 1998-07-07 2000-01-13 The Goodyear Tire And Rubber Company Dual output capacitance interface circuit
US6238946B1 (en) * 1999-08-17 2001-05-29 International Business Machines Corporation Process for fabricating single crystal resonant devices that are compatible with integrated circuit processing
US6759332B2 (en) * 2001-01-31 2004-07-06 International Business Machines Corporation Method for producing dual damascene interconnections and structure produced thereby
JP4890689B2 (ja) * 2001-07-24 2012-03-07 オリンパス株式会社 三次元構造体の製造方法及び揺動体の製造方法
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same

Also Published As

Publication number Publication date
ITTO20010086A1 (it) 2002-07-30
US8050011B2 (en) 2011-11-01
US20090186447A1 (en) 2009-07-23
US20020119597A1 (en) 2002-08-29
US7531897B2 (en) 2009-05-12

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