ITTO20070109A1 - Circuito e metodo di lettura per un dispositivo di memoria non volatile basati sulla generazione adattativa di una grandezza elettrica di riferimento - Google Patents

Circuito e metodo di lettura per un dispositivo di memoria non volatile basati sulla generazione adattativa di una grandezza elettrica di riferimento

Info

Publication number
ITTO20070109A1
ITTO20070109A1 IT000109A ITTO20070109A ITTO20070109A1 IT TO20070109 A1 ITTO20070109 A1 IT TO20070109A1 IT 000109 A IT000109 A IT 000109A IT TO20070109 A ITTO20070109 A IT TO20070109A IT TO20070109 A1 ITTO20070109 A1 IT TO20070109A1
Authority
IT
Italy
Prior art keywords
adaptative
generation
circuit
memory device
volatile memory
Prior art date
Application number
IT000109A
Other languages
English (en)
Inventor
Pierluca Guarino
Edoardo Nocita
Giovanni Pagano
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000109A priority Critical patent/ITTO20070109A1/it
Priority to US12/031,645 priority patent/US7773445B2/en
Publication of ITTO20070109A1 publication Critical patent/ITTO20070109A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers
IT000109A 2007-02-14 2007-02-14 Circuito e metodo di lettura per un dispositivo di memoria non volatile basati sulla generazione adattativa di una grandezza elettrica di riferimento ITTO20070109A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000109A ITTO20070109A1 (it) 2007-02-14 2007-02-14 Circuito e metodo di lettura per un dispositivo di memoria non volatile basati sulla generazione adattativa di una grandezza elettrica di riferimento
US12/031,645 US7773445B2 (en) 2007-02-14 2008-02-14 Reading method and circuit for a non-volatile memory device based on the adaptive generation of a reference electrical quantity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000109A ITTO20070109A1 (it) 2007-02-14 2007-02-14 Circuito e metodo di lettura per un dispositivo di memoria non volatile basati sulla generazione adattativa di una grandezza elettrica di riferimento

Publications (1)

Publication Number Publication Date
ITTO20070109A1 true ITTO20070109A1 (it) 2008-08-15

Family

ID=39715714

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000109A ITTO20070109A1 (it) 2007-02-14 2007-02-14 Circuito e metodo di lettura per un dispositivo di memoria non volatile basati sulla generazione adattativa di una grandezza elettrica di riferimento

Country Status (2)

Country Link
US (1) US7773445B2 (it)
IT (1) ITTO20070109A1 (it)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9159452B2 (en) * 2008-11-14 2015-10-13 Micron Technology, Inc. Automatic word line leakage measurement circuitry
KR101083302B1 (ko) * 2009-05-13 2011-11-15 주식회사 하이닉스반도체 반도체 메모리 장치
US8406059B2 (en) * 2009-12-24 2013-03-26 Samsung Electronics Co., Ltd. Nonvolatile semiconductor memory devices, data updating methods thereof, and nonvolatile semiconductor memory systems
US8472262B2 (en) 2010-06-10 2013-06-25 Hewlett-Packard Development Company, L.P. Sense amplifier for reading a crossbar memory array
CN103366790A (zh) * 2012-03-30 2013-10-23 硅存储技术公司 用于读出放大器的可调整参考发生器
US8760180B1 (en) * 2013-07-29 2014-06-24 Analog Test Engines Systems and methods mitigating temperature dependence of circuitry in electronic devices
CN105336377B (zh) * 2014-06-27 2019-03-12 展讯通信（上海）有限公司 存储器的测试装置和测试方法
CN105206303B (zh) * 2014-06-27 2018-11-16 展讯通信（上海）有限公司 存储器的测试装置和测试方法
US12353503B2 (en) * 2019-05-02 2025-07-08 Silicon Storage Technology, Inc. Output array neuron conversion and calibration for analog neural memory in deep learning artificial neural network
CN110797067B (zh) * 2019-10-21 2021-10-22 上海闪易半导体有限公司 存储阵列模块及其控制方法、装置、模组
DE102021105181A1 (de) * 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Vorrichtung und verfahren zum lesen von daten in einem speicher
KR102861762B1 (ko) * 2020-05-22 2025-09-17 삼성전자주식회사 인-메모리 프로세싱을 수행하는 장치 및 이를 포함하는 컴퓨팅 장치
CN113409855B (zh) * 2021-05-11 2025-03-11 珠海博雅科技股份有限公司 非易失性存储单元的参考电流确定方法、装置及存储介质
US11935603B2 (en) * 2021-11-04 2024-03-19 Infineon Technologies LLC Erase power loss indicator (EPLI) implementation in flash memory device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69514783T2 (de) * 1995-03-23 2000-06-08 Stmicroelectronics S.R.L., Agrate Brianza Leseschaltung für serielle dichotomische Abfühlung von mehrschichtigen nichtflüchtigen Speicherzellen
FR2760888B1 (fr) * 1997-03-11 1999-05-07 Sgs Thomson Microelectronics Circuit de lecture pour memoire adapte a la mesure des courants de fuite
IT1308857B1 (it) * 1999-10-29 2002-01-11 St Microelectronics Srl Metodo e circuito di lettura per una memoria non volatile.
US6697283B2 (en) 2001-01-03 2004-02-24 Micron Technology, Inc. Temperature and voltage compensated reference current generator
EP1640995B1 (en) 2004-09-28 2009-06-17 STMicroelectronics S.r.l. A reading circuit and method for a nonvolatile memory device

Also Published As

Publication number Publication date
US20080205158A1 (en) 2008-08-28
US7773445B2 (en) 2010-08-10

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