ITTO930955A1 - Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologia cmos - Google Patents

Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologia cmos

Info

Publication number
ITTO930955A1
ITTO930955A1 IT93TO000955A ITTO930955A ITTO930955A1 IT TO930955 A1 ITTO930955 A1 IT TO930955A1 IT 93TO000955 A IT93TO000955 A IT 93TO000955A IT TO930955 A ITTO930955 A IT TO930955A IT TO930955 A1 ITTO930955 A1 IT TO930955A1
Authority
IT
Italy
Prior art keywords
high speed
cmos technology
signal transceiver
numerical signal
speed numerical
Prior art date
Application number
IT93TO000955A
Other languages
English (en)
Inventor
Valter Bella
Andrea Finotello
Danilo Galgani
Marco Gandini
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to ITTO930955A priority Critical patent/IT1272078B/it
Publication of ITTO930955A0 publication Critical patent/ITTO930955A0/it
Priority to US08/330,914 priority patent/US5621755A/en
Priority to CA002138106A priority patent/CA2138106C/en
Priority to EP94119838A priority patent/EP0658995A1/en
Priority to DE0658995T priority patent/DE658995T1/de
Priority to JP33423094A priority patent/JP2665728B2/ja
Publication of ITTO930955A1 publication Critical patent/ITTO930955A1/it
Application granted granted Critical
Publication of IT1272078B publication Critical patent/IT1272078B/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H04L27/2272—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals using phase locked loops

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Ricetrasmettitore per segnali numerici ad alta velocità in tecnologia CMOS, in cui il ricevitore possiede un circuito di estrazione del segnale di orologio, che è in grado di autoallinearsi ai dati in arrivo senza pericolo di falsi agganci. Utilizzando la tecnica del PLL, il circuito genera un segnale di orologio agganciato al segnale in arrivo utilizzando un oscillatore locale, controllato in tensione da due anelli di reazione, uno principale per le correzioni di frequenza e di fase e uno secondario per le correzioni di fase. Sono inoltre previste soluzioni circuitali originali per i discriminatori di fase e per i filtri passa-basso.Fig. 4.
ITTO930955A 1993-12-16 1993-12-16 Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologiacmos IT1272078B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
ITTO930955A IT1272078B (it) 1993-12-16 1993-12-16 Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologiacmos
US08/330,914 US5621755A (en) 1993-12-16 1994-10-28 CMOS technology high speed digital signal transceiver
CA002138106A CA2138106C (en) 1993-12-16 1994-12-14 Cmos technology high speed digital signal transceiver
EP94119838A EP0658995A1 (en) 1993-12-16 1994-12-15 CMOS technology high speed digital signal transceiver
DE0658995T DE658995T1 (de) 1993-12-16 1994-12-15 Digitaler Hochgeschwindigkeitssenderempfänger in CMOS-Technologie.
JP33423094A JP2665728B2 (ja) 1993-12-16 1994-12-16 Ｃｍｏｓ技術高速デジタル信号トランシーバ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITTO930955A IT1272078B (it) 1993-12-16 1993-12-16 Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologiacmos

Publications (3)

Publication Number Publication Date
ITTO930955A0 ITTO930955A0 (it) 1993-12-16
ITTO930955A1 true ITTO930955A1 (it) 1995-06-16
IT1272078B IT1272078B (it) 1997-06-11

Family

ID=11411937

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO930955A IT1272078B (it) 1993-12-16 1993-12-16 Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologiacmos

Country Status (6)

Country Link
US (1) US5621755A (it)
EP (1) EP0658995A1 (it)
JP (1) JP2665728B2 (it)
CA (1) CA2138106C (it)
DE (1) DE658995T1 (it)
IT (1) IT1272078B (it)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801867A (en) * 1996-03-20 1998-09-01 Ericsson Raynet DC-coupled receiver for shared optical system
US5953386A (en) * 1996-06-20 1999-09-14 Lsi Logic Corporation High speed clock recovery circuit using complimentary dividers
US5946355A (en) * 1997-03-21 1999-08-31 Tektronix, Inc. Serial-digital receiver
JP3147038B2 (ja) * 1997-05-12 2001-03-19 日本電気株式会社 ビットレート選択型タイミング抽出器、ビットレート選択型識別再生器およびビットレート選択型光再生中継器
US6704382B1 (en) * 1997-07-11 2004-03-09 Tellabs Operations, Inc. Self-sweeping autolock PLL
US5950115A (en) * 1997-08-29 1999-09-07 Adaptec, Inc. GHz transceiver phase lock loop having autofrequency lock correction
JP3094971B2 (ja) 1997-10-08 2000-10-03 日本電気株式会社 位相比較回路並びにこれを用いた位相同期ループ回路及びシリアル―パラレル変換回路
JP2001508272A (ja) * 1997-11-06 2001-06-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 送受信器及び送受信器を有する電気通信システム
US6177835B1 (en) 1998-07-31 2001-01-23 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method and apparatus for high data rate demodulation
WO2000019608A2 (de) * 1998-09-30 2000-04-06 Koninklijke Philips Electronics N.V. Schaltungsanordnung zum verarbeiten von datensignalen
KR100296385B1 (ko) * 1999-01-18 2001-07-12 윤종용 전송 속도 인식방법 및 그 장치
US6313712B1 (en) 2000-06-13 2001-11-06 International Business Machines Corporation Low power crystal oscillator having improved long term and short term stability
US6993107B2 (en) * 2001-01-16 2006-01-31 International Business Machines Corporation Analog unidirectional serial link architecture
US6931075B2 (en) * 2001-04-05 2005-08-16 Microchip Technology Incorporated Event detection with a digital processor
AU2002345380A1 (en) * 2002-06-24 2004-01-06 Samsung Electronics Co., Ltd. Memory module having a path for transmitting high-speed data and a path for transmitting low-speed data and memory system having the memory module
KR100513192B1 (ko) * 2002-09-30 2005-09-08 유티스타콤코리아 유한회사 기지국 트랜시버의 송신 로컬 장치
WO2005071828A1 (en) 2004-01-22 2005-08-04 The Regents Of The University Of Michigan Demodulatr, chip and method for digitally demodulating an fsk signal
US7319731B2 (en) * 2004-02-05 2008-01-15 Broadcom Corporation High precision continuous time gmC BPF tuning
US7432770B2 (en) * 2005-08-10 2008-10-07 Seiko Epson Corporation Signal transmission device
KR100913400B1 (ko) * 2007-07-24 2009-08-21 고려대학교 산학협력단 직렬 송수신 장치 및 그 통신 방법
US8498344B2 (en) * 2008-06-20 2013-07-30 Rambus Inc. Frequency responsive bus coding
US8873693B2 (en) * 2011-09-21 2014-10-28 Fujitsu Limited Phase averaging-based clock and data recovery

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4298986A (en) * 1979-12-26 1981-11-03 General Electric Company Receiver for phase-shift modulated carrier signals
US5015970A (en) * 1990-02-15 1991-05-14 Advanced Micro Devices, Inc. Clock recovery phase lock loop having digitally range limited operating window
JPH05252046A (ja) * 1991-12-25 1993-09-28 Nec Corp ８−１４変調符号復調器
US5487093A (en) * 1994-05-26 1996-01-23 Texas Instruments Incorporated Autoranging digital analog phase locked loop

Also Published As

Publication number Publication date
CA2138106A1 (en) 1995-06-17
DE658995T1 (de) 1996-01-04
EP0658995A1 (en) 1995-06-21
ITTO930955A0 (it) 1993-12-16
US5621755A (en) 1997-04-15
CA2138106C (en) 1998-09-22
JP2665728B2 (ja) 1997-10-22
JPH07202874A (ja) 1995-08-04
IT1272078B (it) 1997-06-11

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971124