ITTO950130A0 - Unita' di ritardo controllata in tensione per dispositivi con anello di aggancio di ritardo. - Google Patents

Unita' di ritardo controllata in tensione per dispositivi con anello di aggancio di ritardo.

Info

Publication number
ITTO950130A0
ITTO950130A0 ITTO950130A ITTO950130A ITTO950130A0 IT TO950130 A0 ITTO950130 A0 IT TO950130A0 IT TO950130 A ITTO950130 A IT TO950130A IT TO950130 A ITTO950130 A IT TO950130A IT TO950130 A0 ITTO950130 A0 IT TO950130A0
Authority
IT
Italy
Prior art keywords
delay
devices
voltage controlled
hooking ring
delay unit
Prior art date
Application number
ITTO950130A
Other languages
English (en)
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to IT95TO000130A priority Critical patent/IT1279115B1/it
Publication of ITTO950130A0 publication Critical patent/ITTO950130A0/it
Priority to EP96102656A priority patent/EP0729231A3/en
Priority to CA002170122A priority patent/CA2170122A1/en
Priority to JP8060258A priority patent/JPH08288792A/ja
Publication of ITTO950130A1 publication Critical patent/ITTO950130A1/it
Application granted granted Critical
Publication of IT1279115B1 publication Critical patent/IT1279115B1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
IT95TO000130A 1995-02-23 1995-02-23 Unita' di ritardo controllata in tensione per dispositivi con anello di aggancio di ritardo. IT1279115B1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT95TO000130A IT1279115B1 (it) 1995-02-23 1995-02-23 Unita' di ritardo controllata in tensione per dispositivi con anello di aggancio di ritardo.
EP96102656A EP0729231A3 (en) 1995-02-23 1996-02-22 Voltage-controlled delay unit for delay-locked loop devices
CA002170122A CA2170122A1 (en) 1995-02-23 1996-02-22 Voltage-controlled delay unit for delay-locked loop devices
JP8060258A JPH08288792A (ja) 1995-02-23 1996-02-23 遅延ロックドループデバイス用電圧制御遅延装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT95TO000130A IT1279115B1 (it) 1995-02-23 1995-02-23 Unita' di ritardo controllata in tensione per dispositivi con anello di aggancio di ritardo.

Publications (3)

Publication Number Publication Date
ITTO950130A0 true ITTO950130A0 (it) 1995-02-23
ITTO950130A1 ITTO950130A1 (it) 1996-08-23
IT1279115B1 IT1279115B1 (it) 1997-12-04

Family

ID=11413250

Family Applications (1)

Application Number Title Priority Date Filing Date
IT95TO000130A IT1279115B1 (it) 1995-02-23 1995-02-23 Unita' di ritardo controllata in tensione per dispositivi con anello di aggancio di ritardo.

Country Status (4)

Country Link
EP (1) EP0729231A3 (it)
JP (1) JPH08288792A (it)
CA (1) CA2170122A1 (it)
IT (1) IT1279115B1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60024404T2 (de) 2000-02-02 2006-08-03 Telefonaktiebolaget Lm Ericsson (Publ) Verfahren und Vorrichtung zur Vorverzerrung eines digitalen Signales
DE10233218A1 (de) * 2002-07-22 2004-02-19 Infineon Technologies Ag Schaltkreis-Anordnung
JP4753800B2 (ja) * 2006-06-05 2011-08-24 日本電信電話株式会社 Ｃｄｒ回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL89120A (en) * 1988-02-17 1992-08-18 Mips Computer Systems Inc Circuit synchronization system
US4868522A (en) * 1988-12-13 1989-09-19 Gazelle Microcircuits, Inc. Clock signal distribution device
US5192916A (en) * 1991-09-20 1993-03-09 Mos Electronics Corporation Charge-pump phase locked loop circuit
DE4326062C1 (de) * 1993-08-03 1994-08-18 Siemens Ag Phasenregelanordnung

Also Published As

Publication number Publication date
ITTO950130A1 (it) 1996-08-23
JPH08288792A (ja) 1996-11-01
EP0729231A3 (en) 1998-03-18
IT1279115B1 (it) 1997-12-04
CA2170122A1 (en) 1996-08-24
EP0729231A2 (en) 1996-08-28

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19990125