ITTO991148A0 - Dispositivo elettronico con collegamenti a doppio filo, metodo di fabb ricazione di tale dispositivo elettronico e metodo di verifica dell'in - Google Patents

Dispositivo elettronico con collegamenti a doppio filo, metodo di fabb ricazione di tale dispositivo elettronico e metodo di verifica dell'in

Info

Publication number
ITTO991148A0
ITTO991148A0 IT99TO001148A ITTO991148A ITTO991148A0 IT TO991148 A0 ITTO991148 A0 IT TO991148A0 IT 99TO001148 A IT99TO001148 A IT 99TO001148A IT TO991148 A ITTO991148 A IT TO991148A IT TO991148 A0 ITTO991148 A0 IT TO991148A0
Authority
IT
Italy
Prior art keywords
electronic device
testing
manufacturing
information
wire connections
Prior art date
Application number
IT99TO001148A
Other languages
English (en)
Inventor
Filippo Marino
Salvatore Capici
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1999TO001148A priority Critical patent/IT1311277B1/it
Publication of ITTO991148A0 publication Critical patent/ITTO991148A0/it
Priority to US09/747,172 priority patent/US6525916B2/en
Publication of ITTO991148A1 publication Critical patent/ITTO991148A1/it
Application granted granted Critical
Publication of IT1311277B1 publication Critical patent/IT1311277B1/it
Priority to US10/337,153 priority patent/US7263759B2/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/465—Bumps or wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
IT1999TO001148A 1999-12-23 1999-12-23 Dispositivo elettronico con collegamenti a doppio filo, metodo difabbricazione di tale dispositivo elettronico e metodo di verifica IT1311277B1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT1999TO001148A IT1311277B1 (it) 1999-12-23 1999-12-23 Dispositivo elettronico con collegamenti a doppio filo, metodo difabbricazione di tale dispositivo elettronico e metodo di verifica
US09/747,172 US6525916B2 (en) 1999-12-23 2000-12-21 Electronic device with double-wire bonding, manufacturing method thereof, and method for checking intactness of bonding wires of this electronic device
US10/337,153 US7263759B2 (en) 1999-12-23 2003-01-02 Methods of manufacturing and testing bonding wires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999TO001148A IT1311277B1 (it) 1999-12-23 1999-12-23 Dispositivo elettronico con collegamenti a doppio filo, metodo difabbricazione di tale dispositivo elettronico e metodo di verifica

Publications (3)

Publication Number Publication Date
ITTO991148A0 true ITTO991148A0 (it) 1999-12-23
ITTO991148A1 ITTO991148A1 (it) 2001-06-23
IT1311277B1 IT1311277B1 (it) 2002-03-12

Family

ID=11418331

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999TO001148A IT1311277B1 (it) 1999-12-23 1999-12-23 Dispositivo elettronico con collegamenti a doppio filo, metodo difabbricazione di tale dispositivo elettronico e metodo di verifica

Country Status (2)

Country Link
US (2) US6525916B2 (it)
IT (1) IT1311277B1 (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3639226B2 (ja) * 2001-07-05 2005-04-20 松下電器産業株式会社 半導体集積回路装置、実装基板および実装体
DE10316357B4 (de) * 2002-10-25 2005-02-10 Semikron Elektronik Gmbh Verfahren zur Überwachung von Leistungshalbleiterbauelementen
TWI245125B (en) * 2004-07-26 2005-12-11 Au Optronics Corp An electrical measurement apparatus and method thereof in the bonding process
JP2008078628A (ja) * 2006-08-25 2008-04-03 Canon Inc 電子モジュールおよびその製造方法
JP4962762B2 (ja) * 2006-08-30 2012-06-27 ブラザー工業株式会社 画像形成装置及びその断線検査方法
DE102006049324A1 (de) * 2006-10-19 2008-04-30 Austriamicrosystems Ag Halbleiterkörper und Verfahren zum Testen eines Halbleiterkörpers
CN109765479B (zh) * 2019-01-28 2021-10-01 合肥京东方视讯科技有限公司 一种电路板缺件检测装置和方法
DE102021202583A1 (de) 2021-03-17 2022-09-22 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Überprüfung von Mehrfachbondverbindungen
US12381553B2 (en) * 2022-12-13 2025-08-05 Texas Instruments Incorporated Integrated circuit with bondwire fault detection circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303400A (en) * 1961-07-25 1967-02-07 Fairchild Camera Instr Co Semiconductor device complex
US3264562A (en) * 1961-09-28 1966-08-02 Warwick Electronics Inc Plural bridge system for simultaneously testing a plurality of interconnected circuit elements
US3250992A (en) * 1962-03-30 1966-05-10 Rca Corp System which includes means for automatically checking connections during the wiring of electrical equipment
US4591659A (en) * 1983-12-22 1986-05-27 Trw Inc. Multilayer printed circuit board structure
FR2560437B1 (fr) * 1984-02-28 1987-05-29 Citroen Sa Procede de report a plat d'elements de puissance sur un reseau conducteur par brasage de leurs connexions
US5684332A (en) * 1994-05-27 1997-11-04 Advanced Semiconductor Engineering, Inc. Method of packaging a semiconductor device with minimum bonding pad pitch and packaged device therefrom
US5745990A (en) * 1995-06-06 1998-05-05 Vlsi Technology, Inc. Titanium boride and titanium silicide contact barrier formation for integrated circuits
US5751015A (en) * 1995-11-17 1998-05-12 Micron Technology, Inc. Semiconductor reliability test chip
DE69833087T2 (de) * 1997-10-08 2006-07-20 Delphi Technologies, Inc., Troy Verfahren zur Herstellung von Dickfilmschaltungen
JPH11160356A (ja) * 1997-11-25 1999-06-18 Matsushita Electric Ind Co Ltd ウェハ一括型測定検査用プローブカードおよびセラミック多層配線基板ならびにそれらの製造方法

Also Published As

Publication number Publication date
ITTO991148A1 (it) 2001-06-23
US6525916B2 (en) 2003-02-25
US20010019169A1 (en) 2001-09-06
IT1311277B1 (it) 2002-03-12
US20030099074A1 (en) 2003-05-29
US7263759B2 (en) 2007-09-04

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