JP2000077263A - Thin film capacitors and substrates - Google Patents

Abstract

[PROBLEMS] To provide a thin film capacitor having a low inductance structure which is easy to mount and easy to laminate. A capacitive element is formed by forming a first electrode layer on a lower surface of a dielectric layer and a second electrode layer on an upper surface of the dielectric layer.
Are arranged in parallel at predetermined intervals, and terminal electrode layers 4 and 5 for connecting the first electrode layers 2 and the second electrode layers 3 are connected between the plurality of capacitive elements A, B, C and D. And external terminals 7 are further provided on the terminal electrode layers 4 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film capacitor, for example, a large-capacity, low-inductance thin-film capacitor provided in an electric circuit operating at high speed and used for bypassing high-frequency noise or preventing fluctuations in power supply voltage. The present invention relates to a thin film capacitor and a substrate.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been an increasing demand for electronic components installed in the electronic devices to be smaller, thinner, and compatible with high frequencies.

In particular, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is from 100 MHz to several hundred MHz, and the clock frequency of the bus between chips is also from 30 MHz, even at the personal computer level. The speed is remarkably increased to 100 MHz.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components, such as capacitors, to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.

In order to reduce the size and the capacity of a capacitor, it is most effective to make the dielectric sandwiched between the pair of electrodes thinner and thinner. The thinning also conforms to the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Among them, what is particularly important in the function of removing high-frequency noise, which is the role of the capacitor, is to instantaneously reduce the power supply voltage that occurs when logic circuits are switched at the same time. This function is reduced by supplying. A capacitor having such a function is a so-called decoupling capacitor.

[0007] The performance required of the decoupling capacitor lies in how quickly the current can be supplied according to the current fluctuation of the load section faster than the clock frequency. Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

However, an actual capacitor element has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitance component decreases as the frequency increases, but the inductance component increases as the frequency increases. Therefore, as the operating frequency increases, the inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error occurs in the logic circuit.

Particularly, in recent LSIs, the power supply voltage has been reduced in order to suppress an increase in power consumption due to an increase in the total number of elements.
The allowable fluctuation range of the power supply voltage is also small. Therefore, it is very important to reduce the inductance of the decoupling capacitor element itself in order to minimize the voltage fluctuation width during high-speed operation.

There are three ways to reduce inductance. The first is to minimize the length of the current path, the second is to reduce the magnetic field formed by one current path by the magnetic field formed by another adjacent current path, and the third is to reduce the number of current paths to n. This is a method of dividing the effective inductance to 1 / n.

The first method is to increase the capacitance per unit area to reduce the size, and can be achieved by reducing the thickness of the capacitor element. In order to obtain a capacitor having a large capacity and good high-frequency characteristics, Japanese Patent Application Laid-Open No. 60-9471
Japanese Patent Application Laid-open No. 6 discloses a thinner dielectric material having a thickness of 1 μm or less.

[0012]

However, when considering a decoupling capacitor that can be mounted at a desired place, the size that can be handled is 0.5 mm × 0.5 mm.
mm or more is required, and there is a limit to reducing the inductance by only the first thin film and the method of miniaturization.

A method using a combination of the first to third methods is also conceivable.
A thin film capacitor having sufficient characteristics in terms of characteristics such as large capacity and high frequency response could not be obtained.

An object of the present invention is to provide a thin film capacitor having a low inductance structure that is easy to mount and easy to stack.

[0015]

According to the thin film capacitor of the present invention, a plurality of capacitive elements each having a first electrode layer formed on a lower surface of a dielectric layer and a second electrode layer formed on an upper surface are arranged at predetermined intervals. In addition, terminal electrode layers for connecting the first electrode layers and the second electrode layers are provided between the plurality of capacitive elements, and external terminals are provided on the terminal electrode layers.

The multilayer thin film capacitor of the present invention comprises a plurality of dielectric layers and a plurality of electrode layers alternately laminated, and the electrode layers alternately contact the first electrode layer or the second electrode layer from below. And a plurality of terminal elements for connecting the first electrode layers and the second electrode layers on the same plane are provided between the plurality of capacitance elements. In addition, an external terminal is provided on the uppermost terminal electrode layer.

Further, the substrate of the present invention is provided with the above-mentioned thin film capacitor provided on the surface and / or inside of the substrate.

[0018]

In the thin film capacitor of the present invention, a plurality of capacitive elements are juxtaposed at a predetermined interval, and the first electrode layer and the second electrode layer of each capacitive element are connected by the terminal electrode layer provided between the capacitive elements. Since the external terminals are formed on the respective terminal electrode layers by being connected to each other, each capacitive element is divided into a plurality of parts, the current path can be divided, and the inductance can be reduced.

A terminal electrode layer for connecting the first electrode layers and a terminal electrode layer for connecting the second electrode layers are formed between the respective capacitor elements, and these terminal electrode layers are each provided with an external terminal. Is provided, the distance between the terminal electrode layers is shortened, the effective current path is shortened, and the inductance can be further reduced.

Further, each electrode layer can be connected at a terminal electrode formed between the capacitance elements, and can be manufactured by a similar manufacturing method only by changing the electrode shape of the conventional capacitor as shown in FIG. Therefore, lamination becomes easy. Further, since the external terminal used for the contact with the outside can be formed on the terminal electrode layer where the dielectric layer does not exist directly below, it is possible to prevent damage to the capacitive element due to thermal stress at the time of forming the external terminal, Further, there is no need to consider the adverse effects, and the mounting becomes easy.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIGS. 1 and 2, a single-plate type thin film capacitor of the present invention has a first electrode layer 2 as a positive electrode on the lower surface of a dielectric layer 1 and a negative electrode on the upper surface. Second
Capacitive elements A, B, C, and D formed by forming the electrode layer 3 are juxtaposed at predetermined intervals.

Terminal electrode layers 4 and 5 are formed between the capacitive elements A, B, C and D, respectively.
The first electrode layers 2 and the second electrode layers 3 are connected via terminal electrode layers 4 and 5, respectively. The capacitance elements A, B, C, D and the terminal electrode layers 4, 5 are formed on the upper surface of the substrate 6.

As shown in FIG. 2, the upper surfaces of three terminal electrode layers 4 connecting the first electrode layers 2 and the upper surfaces of three terminal electrode layers 5 connecting the second electrode layers 3 are formed. Have external terminals 7 that are exposed to the outside.

FIG. 3 shows the planar shapes of the electrode layers 2 and 3 and the dielectric layer 1 connected by the terminal electrode layers 4 and 5 described above. The first electrode layer 2 and the terminal electrode layer 4, and the second electrode layer 3 and the terminal electrode layer 5 are formed on the same plane as shown in FIGS. 3A and 3C, and have a comb shape as a whole. I have.

The terminal electrode layers 4 and 5 are composed of capacitive elements A, B,
It can be formed not only between C and D, but also outside the capacitive elements A, B, C, and D as shown in FIG.

Further, as shown in FIG. 3B, the dielectric layer 1 is formed in a rectangular shape having a size to cover the first electrode layer 2 or the second electrode layer 3. The dielectric layers 1 may be separated from each other at a predetermined interval as shown in FIG. 3B, or each of the terminal electrode layers may be formed as shown in FIG. As long as it does not cover the entire surface of 4,5,
The dielectric layer 1 may be formed so as to be connected to the connection portion 9 made of the same material. By forming such a connection portion 9, the insulation between the terminal electrode layers 4 and 5 having different polarities can be improved.

In the above example, four capacitive elements A, B,
Although the case where C and D are provided has been described, the number of capacitors may be three or more. As the number of capacitor elements increases, the number of terminal electrode layers increases, and the number of external terminals formed thereon can be increased. Therefore, the number of divisions of a current path increases, and inductance can be reduced.

The external terminal 7 of the thin film capacitor of the present invention
As shown in FIG. 2, the capacitors can be formed on the terminal electrode layers 4 and 5, respectively, whereby the capacitance can be taken out. Need not be formed, but may be formed in a required number as needed. However, in order to obtain the effect of dividing the current path, as shown in FIG. 4, it is desirable to form at least two terminal electrode layers 4 and 5, respectively. Also, as shown in FIG. 5, one terminal electrode layer 4,
5 may be formed with two or more external terminals 7. In this case, fixing when connecting to the substrate by the external terminals 7 can be reliably performed.

The thicknesses of the dielectric layer 1 and the electrode layers 2 and 3 are as follows.
The size is 0.1 to 1 μm, and the size is 0.5 to 3 mm on one side. The thickness and size of each layer can be appropriately changed depending on the material and the application.

The substrate 6 used in the present invention is preferably made of alumina, sapphire, MgO single crystal, SrTiO ₃ single crystal, SiO ₂ coated silicon, or the like. In particular, alumina and sapphire are desirable in that they have low reactivity with a thin film, are inexpensive, have high strength, and are crystalline in a dielectric film or an electrode film.

The electrode layers 2, 3 and the terminal electrode layers 4, 5 of the present invention are made of gold (Au), platinum (Pt), palladium (Pd).
d), copper (Cu), silver (Ag), nickel (Ni) thin films and the like. Among these, gold (Au) and platinum (Pt), which have low reactivity with the dielectric and are hardly oxidized, A low copper (Cu) thin film is optimal.

Further, the dielectric layer 1 may have a high dielectric constant in a high frequency region.
μm or less is desirable. For example, the dielectric layer 1 is a dielectric thin film made of a perovskite-type composite oxide crystal containing Pb, Mg, and Nb as metal elements, and has a measurement frequency of 30.
A dielectric thin film having a relative dielectric constant at 0 MHz (room temperature) of 1000 or more is desirable. As the dielectric layer 1, for example,
Perovskite-type composite oxide crystal containing Ba and Ti, P
ZT, PLZT, SrTiO ₃ , Ta ₂ O ₅ or the like may be used, and is not particularly limited. Such a dielectric layer 1 is manufactured by a known method such as a PVD method, a CVD method, and a sol-gel method.

The external terminal 7 may be in the form of a bump, a foil, a plate, a wire, a paste, or the like, and is not particularly limited. A plurality of the external terminals 7 may be combined. The material is solder, Pb, Sn, Ag, Au, Cu, Pt,
There are Al, Ni, conductive resin and the like, and there is no particular limitation, and a plurality of them may be combined.

In the thin film capacitor configured as described above, since the electrode layers 2 and 3 of the capacitive elements A, B, C and D are connected by the terminal electrode layers 4 and 5, the current path is divided into four. And lower inductance can be achieved.

Further, the terminal electrode layers 4 and 5 formed between the capacitive elements A, B, C and D can be made close to each other, and the distance L between the external terminals 7 formed on the terminal electrode layers 4 and 5 can be reduced.
Can be shortened, the current path is shortened, and the inductance can be reduced.

That is, in the conventional thin film capacitor as shown in FIG. 7, the first electrode layer 21 and the dielectric layer 2
2, the second electrode layer 23 is sequentially laminated, and a capacitance extracting portion 24 is formed at an end of the first electrode layer 21 and the second electrode layer 23. It is conceivable to connect them in parallel by connecting them. In this case, although the current path can be divided into four, the distance between the capacity extracting portions 24 becomes long, and the effect of reducing inductance is small.

Further, since the external terminals 7 used for contact with the outside are formed on the terminal electrode layers 4 and 5, respectively, the positive and negative external terminals 7 are exposed upward. The external terminals 7 can be mounted by bonding the external terminals 7 to the electrodes of the formed substrate, and mounting on a substrate or the like becomes easy.

The laminated type thin film capacitor of the present invention will be described with reference to FIG. According to FIG. 6, the laminated thin film capacitor is obtained by further laminating a dielectric layer and an electrode layer on the single plate type thin film capacitor shown in FIG.

That is, capacitance elements formed by alternately laminating the electrode layers 2 and 3 and the dielectric layer 1 are juxtaposed at predetermined intervals, and terminal electrode layers 4 and 5 are formed between the capacitance elements, respectively. Two first electrode layers 2 of the device and two second electrode layers 3
These are connected via terminal electrode layers 4 and 5, respectively. The capacitor and the terminal electrode layers 4 and 5 are formed on the upper surface of the substrate 6.

The multilayer thin film capacitor having the structure shown in FIG. 6 also has the effect of dividing the current path by the plurality of external terminals 7, just like the single plate type thin film capacitor shown in FIGS. In addition, the inductance can be reduced by the effect of shortening the current path due to the close formation of the terminal electrode layers 4 and 5, and the external terminals 7 can be formed on the uppermost terminal electrode layers 4 and 5, so that mounting is easy. Becomes Furthermore, since the electrode layers 2 and 3 and the dielectric layer 1 are alternately laminated, a high capacity is obtained. In addition, the terminal electrode layers 4 and 5 and the electrode layers 2 and 3 can be simultaneously formed, so that the lamination is easy. Becomes

Further, a terminal electrode layer 4 for connecting the lower first electrode layers 2 and a terminal electrode layer 4 for connecting the upper first electrode layers 2 are laminated. 3 and the terminal electrode layer 5 connecting the upper second electrode layers 3 to each other are laminated, and the dielectric layer 1 is provided immediately below the terminal electrode layers 4 and 5. Does not exist,
Damage to the dielectric layer 1 due to thermal stress when forming external terminals can be prevented.

In general, the thin film capacitor of the present invention is formed on the surface of a substrate as described above, but can be used by being built in the substrate. When the laminated type is built in the substrate, the terminal electrode layers are connected to each other by, for example, through-hole conductors formed in the substrate,
Further, the external terminals can also be formed by through-hole conductors, whereby the capacitance is taken out.

Further, although an example has been described in which the shape of the electrode layers 2 and 3 is rectangular, any shape such as a square or a circle may be used.

[0044]

EXAMPLE 1 An electrode layer, a terminal electrode layer and a dielectric layer were all formed by a high-frequency magnetron sputtering method. Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation.

A substrate holder and three target holders are provided in the process chamber, and sputtering from three types of target materials is possible. At the time of sputtering, the substrate holder was moved to the target position of the kind of the material to be formed, and the distance between the substrate and the target was fixed at 60 mm.

A high frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high frequency power supply, and a high-density plasma is generated near the target by a magnetron magnetic field formed by a permanent magnet installed on the back of the target. Then, the target surface was sputtered.

The application of the high-frequency voltage can be independently applied to the three targets. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant.

On the target side of the substrate placed on the substrate holder, three types of metal masks having a thickness of 0.10 mm are provided, and necessary masks can be set on the substrate deposition surface according to the deposition pattern. Structured.

First, a first electrode layer as shown in FIG. 3A is connected to a terminal electrode layer by sputtering a Pt target with a first mask pattern on an alumina sintered body substrate having a thickness of 0.25 mm. the comb electrode integrally formed, subsequently using a _{Pb (Mg 1/3 Nb 2/3} ) O 3 sintered body target, set the second mask pattern, the substrate temperature 53
Under a condition of 5 ° C. and a high frequency power of 200 W, a dielectric layer as shown in FIG. 3B was formed.

Next, a third mask pattern is set, and P
As shown in FIG. 3C, a comb-shaped electrode in which the second electrode layers were connected to each other by a terminal electrode layer was formed integrally by sputtering of the t target. The total area of each of the first electrode layer and the second electrode layer was 0.8 mm ² .

A solder bump was formed on the terminal electrode layer of the manufactured single-plate type thin film capacitor and mounted on an evaluation board.
The used solder bumps had a diameter of 0.1 mm and were formed three on each terminal electrode layer to produce a thin film capacitor as shown in FIGS. The distance L between the solder bumps is 0.
5 mm.

The evaluation was carried out by using an impedance analyzer (HP4291A, manufactured by Hewlett-Packard Company) for the impedance characteristics from 1 MHz to 1.8 GHz. After the above measurement, when the cross section of the thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.4 μm.

As a comparative example, except that the structure of a conventional general capacitor as shown in FIG. 7 was used, for example, conditions such as the area of the electrode layer were manufactured in the same manner as above, and the capacitance component and the inductance component were changed. Was measured, the capacitance component was 1
A value of 7.6 nF and an inductance component of 380 pH was obtained.

Example 2 A laminated thin-film capacitor having 10 dielectric layers was fabricated in exactly the same manner as in Example 1, and evaluated by the same method as in Example 1. The capacitance component was 176 nF and the inductance component was 80.
A pH value was obtained. After the above measurement, when the cross section of the multilayer thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.4 μm.

Example 3 A substrate material, an electrode material, an electrode forming method, a shape, and dimensions were exactly the same as in Example 1, and only a dielectric layer was formed by a sol-gel method. The procedure for producing a film by the sol-gel method was as follows.

Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2 and refluxed in 2-methoxyethanol (1).
(At 24 ° C. for 24 hours), and an MgNb composite alkoxide solution (Mg = 4.95 mmol, Nb = 10.05 mm)
ol, 2-methoxyethanol 150 mmol) was synthesized. Next, 15 mmol of lead acetate (anhydride) and 150 mm
ol of 2-methoxyethanol was mixed, and a Pb precursor solution was synthesized by a distillation operation at 120 ° C.

The MgNb precursor solution and the Pb precursor solution are mixed at a molar ratio of Pb: (Mg + Nb) = 1: 1,
Stir well at room temperature and add Pb (Mg _1/3 Nb _2/3 ) O ₃ (P
(MN) precursor solution was synthesized.

The solution was diluted about 3-fold with 2-methoxyethanol to obtain a coating solution. Next, on the electrode layer,
The coating solution was applied by a spin coater, dried, and then heat-treated at 300 ° C. for 1 minute to prepare a gel film. After repeating the application of the coating solution and the heat treatment, 8
Firing at 30 ° C. for 1 minute (in air) is performed, and Pb (Mg
_{A 1/3} Nb _2/3 ) O ₃ thin film was obtained.

A resist is coated on the obtained dielectric thin film, exposed and developed by a photolithography process, and the dielectric film is patterned into the same pattern shape as in Example 1 by wet etching using the resist as a mask. Then, the same thin-layer capacitor as in Example 1 was manufactured.

The manufactured thin film capacitor was replaced with the same as in Example 1.
It was mounted on an evaluation board, and the impedance characteristics at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP4291A, manufactured by Hewlett-Packard Company). As a result, the capacitance component obtained a value of 42.5 nF and the inductance component obtained a value of 80 pH. After the above measurement, when the cross section of the thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.5 μm.

[0061]

As described above in detail, in the thin film capacitor of the present invention, each capacitance element is divided into a plurality of parts, the current path can be divided, the inductance can be reduced, and the capacitance between each capacitance element can be reduced. In addition, a terminal electrode layer connecting the first electrode layers and a terminal electrode connecting the second electrode layers are formed, and by providing an external terminal to each of these terminal electrodes, the distance between the terminal electrodes is reduced. As a result, the effective current path becomes shorter and the inductance can be reduced. Furthermore, since the structure of the present invention can be easily laminated, and the external terminals used for contact with the outside are formed on the terminal electrode layer, it is necessary to consider damage to the capacitive element due to thermal stress generated when forming the external terminals. And it is easy to mount.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing a single-plate type thin film capacitor of the present invention.

FIG. 2 is a plan view of FIG.

FIG. 3 is a plan view showing a comb-shaped electrode in which electrode layers of the thin film capacitor of the present invention are connected by a terminal electrode layer, and a dielectric layer.

FIG. 4 is a plan view of a thin film capacitor having a terminal electrode layer on which no external terminal is formed.

FIG. 5 is a plan view of a thin film capacitor in which two external terminals are formed on a terminal electrode layer.

FIG. 6 is an exploded perspective view showing a multilayer thin film capacitor of the present invention.

FIG. 7 is an exploded perspective view showing a conventional thin film capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Dielectric layer 2 ... 1st electrode layer 3 ... 2nd electrode layer 4, 5 ... Terminal electrode layer 6 ... Substrate A, B, C, D ... Capacitance element 7 ... External terminals

Claims (3)

[Claims] A plurality of capacitive elements each having a first electrode layer formed on a lower surface of the dielectric layer and a second electrode layer formed on the upper surface thereof at predetermined intervals; A thin-film capacitor comprising: a terminal electrode layer for connecting the first electrode layers and the second electrode layer; and an external terminal for the terminal electrode layer. 2. A capacitor comprising a plurality of dielectric layers and a plurality of electrode layers alternately laminated, wherein said electrode layers are alternately arranged as a first electrode layer or a second electrode layer from below at predetermined intervals. And a plurality of terminal electrodes for connecting the first electrode layers and the second electrode layers on the same plane, respectively, between the plurality of capacitive elements, and further comprising the uppermost terminal electrode A thin-film capacitor comprising an external terminal provided on a layer. 3. A substrate comprising the thin film capacitor according to claim 1 provided on the surface and / or inside of a substrate.