JP2000201068A - Clock synchronization circuit and storage medium storing program - Google Patents

Abstract

(57) [Summary] [Problem] To select one of a plurality of reference clocks and perform PL
When synchronizing with the L circuit, the phase jump at the time of clock switching is minimized. SOLUTION: When a reference clock REF1 is selected by a selector 1, a selector 8 receives an input A and a selector 9 receives an input B.
Select The flip-flop 6 divides REF1 by １ ／, and the flip-flop 7
An operation of punching out the L output with the reference clock REF2 is performed. When the signal is switched from REF1 to REF2 by the selection signal CONT, the selectors 8 and 9 switch the inputs A and B by the decoder 10. At this time, the output of the selector 1 makes a phase jump, but since the phase of the flip-flop 7 is the divided phase closest to the phase of the flip-flop 6, the phase jump is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization circuit for selecting and synchronizing one of a plurality of reference clocks used in a communication device or the like and a storage medium storing a program.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional reference signal selection type clock synchronization circuit. In FIG. 5, the EX-OR type phase comparator 2, low-pass filter 3, voltage-controlled oscillator 4, and 1/2 frequency divider 5 constitute a PLL circuit. One of the input reference clocks REF1 and REF2 is selected by the selector 1 and input as a clock of the flip-flop 12. The flip-flop 12 receives the inverted output as an input and operates as a 1/2 frequency divider. An output of the flip-flop 12 becomes an input of the EX-OR type phase comparator 2 and becomes a reference signal of the PLL circuit.

[0003]

FIG. 6 shows the operation of the circuit shown in FIG. 5 when the reference clock is switched. As shown in FIG. 6, the clock input of REF1 (FIG. 6) and REF2
When the switching by the selector 1 occurs between adjacent edges of both clocks when the phases of the clock inputs (same) are close, as shown in FIG. , Two adjacent pulses are input.

At this time, since the phase of the 1/2 frequency divider 5 jumps by almost 180 degrees, there is a problem that it takes a long time to pull in the PLL and the output has a large fluctuation in frequency until pulling.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is an object of the present invention to minimize a phase jump at the time of clock switching in a clock synchronous circuit that selects and synchronizes one of a plurality of reference clocks. With the goal.

[0006]

In order to achieve the above object, in a clock synchronization circuit according to the present invention, a plurality of frequency dividing means for dividing a plurality of reference clocks respectively,
A selecting means for selecting one of the output clocks of each frequency dividing means in accordance with the selection signal, and an output phase of the frequency dividing means not selected is kept at a phase closest to an output phase of the selected frequency dividing means. And control means for performing control.

Further, in the clock synchronization circuit according to the present invention, a plurality of flip-flops each of which divides a plurality of reference clocks, and a first selection for selecting one of output clocks of each flip-flop according to a selection signal. Means, a synchronizing means for generating a clock synchronized with the selected clock, and each inverted output clock of each flip-flop as an input A, and a clock generated in synchronism as a common input B. A plurality of second selecting means for selecting and outputting to a corresponding flip-flop; and a second selecting means corresponding to a flip-flop whose output clock is not selected by the first selecting means selects an input B and outputs a flip-flop. And control means for performing control in accordance with the selection signal so as to output the selected signal to the control unit.

In the clock storage medium according to the present invention, a frequency dividing process for dividing a plurality of reference clocks, and a selecting process for selecting one of the frequency divided outputs according to a selection signal are selected. And a control process for controlling the non-divided output phase so as to maintain the phase closest to the selected divided output phase.

In the storage medium according to the present invention,
Frequency division processing for dividing a plurality of reference clocks using a plurality of flip-flops, selection processing for selecting one of output clocks of each flip-flop according to a selection signal, and clock synchronized with the selected clock And a control process for controlling a flip-flop whose output clock is not selected by the selection process in accordance with a selection signal so that a clock generated in synchronization with the flip-flop is supplied. Program is stored.

[0010] In the clock synchronization circuit and the storage medium, the flip-flop not selected selects
The input B may be punched out with the input reference clock, and a synchronized clock may be generated using a PLL circuit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, in a clock synchronization circuit that selects and synchronizes one of a plurality of reference clocks used in a communication device or the like, a phase of each divider that divides an unselected reference clock is selected. And a circuit that keeps the phase closest to the phase of the frequency divider of the reference clock and minimizes the phase jump at the time of switching.

FIG. 1 shows a clock synchronization circuit according to an embodiment of the present invention. In FIG. 1, the reference clock REF
1 and REF2 are input as clocks of flip-flops 6 and 7, respectively. The inverted outputs of the flip-flops 6 and 7 are both input to the selector 1, and at the same time, the inverted outputs of the flip-flops 6 and 7 are
9 is input A.

The output of the selector 1 becomes one input of the EX-OR type phase comparator 2, and the output of the EX-OR type phase comparator 2 passes through the low-pass filter 3 and controls the voltage-controlled oscillator 4. Input as a signal. The output of the voltage-controlled oscillator 4 is output to the outside as the output of the clock synchronization circuit, and
The signal is input to the 1/2 frequency divider 5. The output of the 1/2 frequency divider 5 is the other input of the EX-OR type phase comparator 2.

The EX-OR type phase comparator 2, low pass filter 3, voltage control type oscillator 4, and 1/2 frequency divider 5 constitute a PLL circuit. The output of the 1/2 frequency divider 5 becomes the input B of the selectors 8 and 9 after the polarity is inverted by the inverting circuit 11 at the same time.

On the other hand, the selection signal CONT is input to the selector 1 and controls which of the two inputs is selected. The selection signal CONT is input to the decoder 10 at the same time. The decoder 10 is controlled by the selection signal CONT and outputs a selection signal to the selectors 8 and 9. At this time, the decoder 10 controls the selectors 8 and 9 such that the selector on the side where the reference clock is selected by the selector 1 selects the input A and the other selectors select the input B.

Next, the operation of the above configuration will be described. FIG. 2 shows an example of an output waveform of each unit when switching from REF1 as a reference clock to REF2. , Are the inputs of the reference clocks REF1 and REF2, are the outputs of the flip-flop 6, are the outputs of the flip-flop 7, are the outputs of the selector 1, are the outputs of the 1/2 frequency divider 5, and are EX-OR type phase comparators. The output 2 indicates the output of the inverting circuit 11 and the input of the switching signal CONT.

In the initial state, REF1 is used as a reference clock.
Is selected, the selector 8 selects the input A and the selector 9 selects the input B. As a result, flip-flop 6
Operates as a frequency divider that divides the input REF1 by １ ／. This 1/2 frequency dividing operation is performed by the EX-OR type phase comparator 2
Is supplied with a reference signal having a duty ratio of 50%.

On the other hand, the flip-flop 7 includes the inverting circuit 1
The operation of punching out the output of No. 1 with the clock of REF2 is performed. Since the EX-OR type phase comparator 2 receives the waveform of the following, the EX-OR type phase comparator 2, the low-pass filter 3, the voltage control type oscillator 4, and the 1/2 frequency divider 5 The configured PLL loop is phase locked to the waveform of
At the input of the EX-OR type phase comparator 2, the phase converges to 90 ° as shown in FIG.

Here, when the switching of the REF2 to the reference clock occurs, the selector 8 sets the input to A
To B, and the selector 9 switches the input from B to A. At the same time, the selection input to the EX-OR type phase comparator 2 is switched to kara. As a result, the PLL loop starts phase synchronization with the waveform, and a phase jump occurs. The magnitude of the phase jump generated at this time is the phase difference between the original waveform and the original waveform.

FIG. 3 shows the relationship between the input phase of REF1 and REF2 and the phase difference between the outputs of flip-flops 6 and 7.
Shown in FIG. 3 shows the reference clock of REF 1 and the output of flip-flop 6. Indicates a reference clock of REF2, and indicates an output of the flip-flop 7.

Now, consider the frequency division phase of the flip-flop 7 such that the phase jump is minimized when the reference clock is switched. When the phase of the flip-flop 7 takes the divided phase closest to the phase of the flip-flop 6, the phase jump is minimized.

That is, if the cycle of the reference clock is T,
R in the range of rising edge of flip-flop 6 ± T / 2
The rising edge of EF2 has a rising divided phase, and the falling edge of flip-flop 6 ± T /
For the rising edge of REF2 in the range of 2,
If the dividing phase of the flip-flop 7 is determined so as to have the falling dividing phase, the phase jump can be minimized.

This is the area division in FIG. That is, when the reference clock of REF2 rises in the area A, the flip-flop 7 takes the frequency-divided phase of the rise, and when the reference clock of REF2 rises in the area B, the flip-flop 7 falls. , The phase jump of the PLL is minimized.

Here, as described above, in the EX-OR type phase comparator 2, the phase difference between the reference signal and the self-excited signal is 9
Since it converges to 0 °, the output of the 1/2 frequency divider 5 at the time of convergence is as shown in FIG. When this is inverted by the inverting circuit 11, the waveform of FIG. 3 is obtained. When this is compared with the above-described area division, it can be seen that the area A corresponds to L and the area B corresponds to H.

That is, by punching out the waveform of FIG. 3 at the rising edge of REF2, the flip-flop 7
Can be adjusted to the phase with the minimum phase jump. For this reason, the frequency-selecting flip-flop of the unselected reference clock is connected to the inverting circuit 11.
In this case, the phase difference of the output of the frequency divider can be suppressed to only the phase difference between the reference clocks by switching the input to the inverted output of the flip-flop at the same time as the selection is made. When the modulation polarity of the voltage controlled oscillator 4 is opposite, the inverting circuit 11 is unnecessary.

Next, a second embodiment of the present invention will be described with reference to FIG. 4, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The difference between the present embodiment and the first embodiment is that the first embodiment is a synchronous circuit that selects one from two reference clocks, whereas the present embodiment has N . REFN are configured as a synchronous circuit for selecting one from the reference clocks REF1, REF2,.

For this purpose, a flip-flop 13 and a selector 14 are added in FIG. Also in the present embodiment, as in the first embodiment, a frequency-dividing flip-flop of an unselected reference clock is made to stand by in a state where the output of the inverting circuit 11 is punched out by the reference clock, and the reference clock is output. By switching the input to the inverted output of the flip-flop at the same time when the clock is selected, the phase jump can be suppressed to only the phase difference between the reference clocks.

Although the present invention can be realized by a hardware configuration, when realized by a computer system including a CPU and a memory, the memory constitutes a storage medium according to the present invention. A program for executing the operation of each of the above-described embodiments is stored in the storage medium. Further, as the storage medium, a semiconductor storage device, an optical disk, a magneto-optical disk, a magnetic medium, or the like can be used.

[0029]

As described above, according to the present invention,
In a clock synchronization circuit that uses a plurality of reference clocks by switching, there is an effect that a phase jump generated at the time of switching can be suppressed to only a phase difference between the reference clocks.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a clock synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the clock synchronization circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining a phase difference at the time of clock switching.

FIG. 4 is a configuration diagram illustrating a clock synchronization circuit according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram showing a conventional clock synchronization circuit.

FIG. 6 is a timing chart showing an operation of a conventional clock synchronization circuit.

[Explanation of symbols]

 1, 8, 9, 14 selector 2 EX-OR type phase comparator 3 low-pass filter 4 voltage controlled oscillator 5 1/2 frequency divider 6, 7, 12, 13 flip-flop

Claims (8)

[Claims] 1. A plurality of frequency dividers for dividing a plurality of reference clocks, a selector for selecting one of output clocks of each divider according to a selection signal, and a divider not selected And control means for controlling the output phase of the frequency dividing means so as to maintain the phase closest to the output phase of the selected frequency dividing means. 2. A plurality of flip-flops each of which divides a plurality of reference clocks, first selection means for selecting one of output clocks of each flip-flop according to a selection signal, A synchronizing means for generating a synchronized clock; and an inverted output clock of each of the flip-flops as an input A and a clock generated in synchronization as a common input B. A plurality of second selecting means for outputting to the flip-flop, the second selecting means corresponding to a flip-flop whose output clock is not selected by the first selecting means, selecting the input B, And a control means for controlling according to the selection signal so as to output the clock signal to the clock synchronous circuit. 3. The clock synchronization circuit according to claim 2, wherein the unselected flip-flop operates so as to punch out the input B with an input reference clock. 4. The clock synchronization circuit according to claim 2, wherein said synchronization means is constituted by a PLL circuit. 5. A dividing process for dividing a plurality of reference clocks, a selecting process for selecting one of the divided outputs according to a selecting signal, and a dividing output phase that is not selected are selected. A storage medium storing a program for executing a control process of performing control so as to maintain the phase closest to the divided output phase. 6. A dividing process for dividing a plurality of reference clocks using a plurality of flip-flops, a selecting process for selecting one of output clocks of each flip-flop according to a selection signal, and Synchronous processing for generating a clock synchronized with the selected clock; and responding to the selection signal such that the synchronously generated clock is supplied to a flip-flop whose output clock is not selected by the selection processing. A storage medium that stores a program for executing a control process for performing control. 7. The storage medium storing a program according to claim 6, wherein the control processing is performed by the unselected flip-flop so that the input B is punched out by an input reference clock. . 8. The storage medium storing a program according to claim 6, wherein said synchronization processing is processing by a PLL loop.