JP2000201497A - Step motor drive control circuit - Google Patents

Abstract

(57) [Summary] An object of the present invention is to provide a drive control circuit for a low-noise step motor that repeats on and off of a phase signal according to the speed of the step motor. Also, a phase signal is generated so as not to simultaneously drive a pair of phases of the step motor. A motor includes a step motor, driving means for exciting the phase of the step motor according to the phase signal to drive the step motor, and generating a phase signal each time a drive signal is applied. Means and control means for controlling the on and off of the phase signal generated by the phase signal generating means when the drive signal is not applied to the phase signal generating means for a predetermined time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control circuit for a stepping motor suitable as an image reading motor for a facsimile or the like.

[0002]

2. Description of the Related Art Conventionally, a stepping motor is generally used in a paper transport system of a facsimile. As this driving method, two methods of a constant current driving and a constant voltage driving are used. When driving at a relatively low speed, constant-voltage driving is often performed using a four-phase unipolar stepping motor capable of simplifying the driving circuit.

[0003]

However, the general 4
With the use of phase unipolar, under worst-case conditions, current flows through all four-phase coils, which can cause equipment damage due to overheating of the motor. As a measure against software runaway, it is conceivable to add a protection circuit such as interrupting the current with a thermal fuse in order to prevent damage.However, adding a protection circuit increases the cost. Sometimes it was necessary to replace parts to regenerate.

[0004] In addition, there is also a problem that, when driving at a low speed, driving with the same driving force as at the time of high speed driving, the force is too large and the conveying noise becomes loud.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a drive control circuit for a low-noise step motor which repeatedly turns on and off a phase signal in accordance with the speed of the step motor. Things.

Another object of the present invention is to generate a phase signal so as not to simultaneously drive a pair of phases of a step motor.

[0007]

In order to achieve the above object, the present invention provides a step motor, driving means for driving the step motor by exciting a phase of the step motor according to a phase signal, A phase signal generating means for generating the phase signal each time a signal is applied, and turning on and off a phase signal generated from the phase signal generating means when the driving signal is not applied to the phase signal generating means for a predetermined time. And a control means for controlling so as to repeat the step.

Further, the present invention provides a step motor having at least two pairs of phases, driving means for exciting the phase of the step motor in accordance with a phase signal to drive the step motor, and Phase signal generating means for generating the phase signal each time the phase signal is added, and phase signal generating means for generating the phase signal so as not to simultaneously drive a paired phase of the step motor each time a drive signal is added. And control means for repeating on and off of a phase signal generated from the phase signal generation means when the drive signal is not applied to the phase signal generation means for a predetermined time. A circuit is adopted.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

First, a facsimile will be described as an example to which the motor drive control circuit according to the embodiment of the present invention can be applied.
FIG. 1 is a circuit block diagram of a facsimile to which a motor drive control circuit according to an embodiment of the present invention can be applied. Since the configuration of the facsimile shown in FIG. 1 is a general one, only the function of each part will be outlined.

In FIG. 1, 1 is a CPU for controlling the operation of the entire facsimile apparatus of the present invention, 2 is a bus used for exchanging data, exchanging instructions, and the like, and 3 is a CPU for exchanging instructions. A ROM for storing a control program, 4 is an SRAM for storing source information, user registration information, etc., 5 is a modem for modulating image signals and audio signals, 6 is a telephone A network control unit for controlling the connection between the line and the device;
Is a public telephone line, 8 is a wired telephone, 9 is a wireless base unit for communicating with a wireless telephone, and 10 is a wireless base unit.
Reference numeral denotes a cross point switch for switching a path of audio data, reference numeral 12 denotes a reading sensor (line sensor) for reading an image, reference numeral 11 denotes an image processing gate array, and reference numeral 13 denotes a print head for recording an image.

Reference numeral 14 denotes a DRAM for temporarily storing an image to be supplied to the print head. Reference numeral 16 denotes a document detection sensor for detecting a document width and the presence or absence of a document.
Reference numeral 7 denotes a paper detection sensor for detecting the paper size and presence / absence of paper. Reference numeral 20 denotes a reading motor for transporting the document. Reference numeral 22 denotes a motor driver (transistor array) for driving the reading motor. Reference numeral 19 denotes The operation panel is composed of a keyboard and an LCD for displaying the status of the image forming apparatus.

Reference numeral 18 denotes a system gate array (multifunctional gate array), which includes a print head 13 and a DRA.
M14, various sensors 16 and 17, a motor driver 22 of a reading motor 20, and an operation panel 19 are connected.

The system gate array 18 further converts the image data arranged in the main scanning direction into image data arranged in the sub-scanning direction in accordance with the arrangement of the nozzles of the head and the synchronizing signal generation section and the read motor drive protection circuit. And prints key input data and various data input from the keyboard and output signals of various sensors
A process of converting the code signal into a code signal that can be determined by the PU and a timing process of the reading motor are performed.

Reference numeral 25 denotes an LF motor for conveying the recording paper in the sub-scanning direction; 23, a motor driver for driving the motor 25; 26, a CR motor for driving a carriage on which a print head is mounted. And 2
Reference numeral 4 denotes a motor driver for driving the CR motor 26.

Next, a motor drive circuit according to the present invention will be described. FIG. 2 is an example of a drive control circuit for a motor driver of a reading motor in a system gate array. The reading motor is a motor that feeds the original in the sub-scanning direction to read the original in a facsimile. 201 is a first register for designating an excitation phase, and 202 is a first register 2
01 is a second register for holding a value of 01, and 203 is a SW
(Switching) a third register for designating a time to start the control, 204 a shift register for measuring the time from the change of the excitation phase, and 205 a fourth register for designating the on / off duty of the switch control. Yes, 2
06 is a comparator that compares the value written in the first register with the previous value (the value of the second register 202), and generates an RST * signal if the values are different. A comparator that compares the value of the register 203 with the value of the shift register 204 and generates a SWEN signal that permits switch control when a specified time or more has elapsed. 208 is a 50 μS cycle based on the value of the fourth register 205. Is a pulse generating circuit for generating a PULSE signal for controlling the on / off duty of the A / D converter, 210 is a NAND circuit for generating a SW signal from the SWEN and PULSE signals, 209 is an A phase and an A * (negation of A) phase, and B is a Exclusive control for inhibiting simultaneous driving of the phase and the B * (negation of B) phase, and the NAND circuit 210
This is a port control unit that turns on and off the driving of the excitation phase by the SW signal from the controller.

The reading motor 20 is a four-phase unipolar stepping motor, and is driven by a motor driver 22 composed of a transistor array based on a control signal from the system gate array 18.

The four drive signals correspond to the four drive coils A, B, A * and B * phases of the reading motor, respectively. As shown in FIG. 3, the directions of the forces generated on the rotation axis of the motor by driving the four drive coils are A and A *, and B and B *.
Are the opposite directions, respectively, A, A * and B, B * exert forces in orthogonal directions, and the rotation of the motor involves the steps of the combination of driving the four coils as shown in Table 1 of the attached sheet. It is done by changing.

In actual motor driving, the A and A * phases or the B and B * phases are not driven at the same time, and both phases of these two combinations are driven at the same time by the exclusive control of the port control unit 209. It is forbidden to do so. Specifically, the driving of the A phase and the B phase is prioritized, and the A * phase when the A phase is driven and the B * phase when the B phase is driven become invalid.

More specifically, the port control unit 209
Are NOT circuits 209a and 209b, and an AND circuit 209
c to 209h, for example, a NOT circuit 209a
Is controlled through two AND circuits 209c and 209f, so that the input of the NOT circuit 209a is H level.
At the time of (high), the output of the NOT circuit 209a becomes L (low) and only L (low) is input to the A * phase, so that simultaneous driving is prohibited.

FIG. 4 is a time chart showing the operation of the motor drive circuit during a certain period. Specifically, FIG. 4 shows steps 8 (excitation phase is A) to step 1 (excitation phase is A) in Table 1.
7 is a time chart for explaining an example when shifting to B).

In the first register 201, a motor drive signal is directly written from the CPU 1 as a 4-bit data bus signal, and the written drive signal (data) is stored in the first register 201.
From the first register 201 to the second register 202 at a predetermined period. A phase signal corresponding to the data written in the second register 202 is transmitted to the port control unit 209.
And the phase signal generated by the port controller 209 is applied to the driver 22 to excite the coil of the step motor 20. Accordingly, the data written in the second register 202 is rewritten one after another, whereby the phase signals generated by the port control unit 209 are sequentially switched, and the coils of the step motor 20 are sequentially switched through the driver 22 by excitation, so that the motor It will be driven.

Here, drive signals (data) are successively applied to the first register 201, and the time from when the first drive signal is applied to when the next drive signal is applied is equal to the first drive signal. In the case where the time is shorter than a certain period of time for shifting data from the first register 201 to the second register 202, that is, when the data is rotated faster than a certain speed, the first register 201 is used. Does not match the data of the second register 202, the comparator 206 does not output the RST signal.

Conversely, the time from when the first drive signal is applied to when the next drive signal is applied is equal to a predetermined period for shifting data from the first register 201 to the second register 202. When the time is slower than the time, that is, when the motor is rotated more slowly than a certain speed or when the motor is stopped, the data in the first register 201 and the data in the second register 202 match. , And the comparator 206 outputs an RST signal. That is, when the value of the first register 201 to which the drive signal is input is rewritten by the write signal at the timing (a), the value of the second register 202 held by the value of the first register 201 and the value of the first , The RST signal is output from the comparator 206. When the RST signal is output from the comparator 206, the shift register 204 is initialized.

The third register 203 is a register for designating the number of XSH signals, which are periodic read signals, before starting on / off control. This third
Is set to XSH = 1. Therefore,
When XSH is input to the initialized shift register 204, the value of the shift register 204 and the third register 20
The SWEN signal is output from the SWEN generation unit 207 at the timing (b) when the values of 3 match.

The fourth register 205 is initialized each time the XSH signal is input, and specifies an ON / OFF cycle. The pulse generator 208 is provided in the fourth register 2
05 from the fourth register 205
Generates a pulse signal with an on / off cycle specified by. Accordingly, at the timing (c) when the fourth register 205 is initialized, the SW signal from the NAND circuit 210 is output according to the pulse signal from the pulse generation unit 208,
The fourth register 205 changes the duty of the pulse signal at timing (d) initialized by the XSH signal,
The SW signal from NAND circuit 210 also changes accordingly.

As described above, the ON / OFF state of the NAND circuit 210
Since the SW signal that repeatedly turns off is output, the phase signal generated by the port control unit 209 repeatedly turns on and off.

The PULSE signal has a period of 50 μS.
The on / off duty for one cycle changes according to the designation of the fourth register 205. The 50 μS cycle is set so that the resonance sound generated from the drive system is outside the audible band when performing the SW control.

When driving with the same driving force as in high-speed driving at low-speed driving, the driving force is too large and the carrier sound becomes loud. Therefore, the switching duty and the period until the start of switching are controlled to control the driving force. Adjustments are made to reduce drive noise.

[0030]

As described above, according to the present invention,
A motor drive circuit that reliably prevents current from flowing in all four phases is obtained.

Further, when driving with the same driving force as in high-speed driving during low-speed driving, the driving force is too large and the carrier noise increases, so the switching duty and the period until the start of switching are controlled to adjust the driving force. And a motor drive circuit capable of reducing the drive noise is obtained.

[Table 1]

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a facsimile apparatus as an example to which a motor drive control circuit according to the present invention can be applied;

FIG. 2 is a circuit diagram showing a main part of an image reading step motor drive control circuit of the facsimile apparatus shown in FIG. 1;

FIG. 3 is a view for explaining an excitation phase and a direction of generated force of the step motor shown in FIG. 1;

FIG. 4 is a time chart of the step motor drive control circuit shown in FIG. 2;

[Explanation of symbols]

 1 CPU 2 bus 3 ROM 18 system gate array 19 operation panel 20 read motor 22 read motor drive driver 201 first register 202 second register 203 shift register 204 third register 205 fourth register 206 comparator 207 SWEN signal generator 208 pulse generation circuit 209 port control unit 210 NAND circuit

Claims (7)

[Claims] 1. A step motor, driving means for exciting the phase of the step motor in accordance with a phase signal to drive the step motor, and phase signal generating means for generating the phase signal each time a drive signal is applied. And control means for controlling so as to repeat on and off of a phase signal generated from the phase signal generation means when the drive signal is not applied to the phase signal generation means for a predetermined time. Step motor drive control circuit. 2. The step motor drive control circuit according to claim 1, further comprising: a time counting means for counting a predetermined time after the drive signal is input to the phase signal generating means, wherein the predetermined time counted by the time counting means is provided. A step motor drive control circuit, further comprising an operation means for operating the control means when a next drive signal is not applied to the phase signal generation means within a time. 3. The step motor drive control circuit according to claim 1, wherein said drive signal is a 4-bit data bus signal, and said time-measuring means is configured to write a 4-bit data bus signal to said first signal.
And a second register that shifts the data written in the first register at a certain predetermined period, wherein the operating means operates the first register within a time corresponding to the certain predetermined period. A step motor drive control circuit, comprising: comparing means for comparing whether the value of the register is different from the value of the second register. 4. The step motor drive control circuit according to claim 1, wherein said control means has an adjustment means for adjusting an on / off time of a phase signal generated from said phase signal generation means. Step motor drive control circuit. 5. The step motor drive control circuit according to claim 1, wherein said step motor is a four-phase unipolar motor. 6. A step motor drive control circuit according to claim 1, wherein said drive means determines an excitation phase and an excitation time of said step motor in accordance with a phase signal. 7. A step motor having at least two pairs of phases, driving means for driving the step motor by exciting the phase of the step motor in response to a phase signal, and each time the driving means is added. Phase signal generating means for generating the phase signal; phase signal generating means for generating the phase signal so as not to simultaneously drive a paired phase of the step motor each time a drive signal is added; And a control means for repeatedly turning on and off a phase signal generated from the phase signal generating means when the phase signal is not applied to the phase signal generating means for a predetermined time.