JP2000214826A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

(57) [Problem] To provide a time-division driving color display liquid crystal device capable of suppressing the occurrence of crosstalk between colors, achieving good display quality, and extending the lighting time of a monochromatic light source. provide. SOLUTION: Before an image signal writing period tw in a time-divided image display period (sub-frame period) of a liquid crystal panel 2, all data lines are selected from data line reset circuits 140 and 150 in a state where all scanning lines are selected. , A liquid crystal reset signal is applied to generate an electric field for returning the liquid crystal alignment in all the pixels to the initial alignment state side. Thus, the influence of the write data in the previous image display period can be reduced, and the occurrence of crosstalk between colors can be suppressed. Further, by shortening the fall time of the liquid crystal, the lighting time of the light emitting light source can be set longer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for driving the same, and more particularly, to a liquid crystal display device for performing color display by color mixing by time division and a method for driving the same.

[0002]

2. Description of the Related Art In recent years, attention has been paid to a liquid crystal display device which performs color display by time difference color mixing within a single dot, that is, color mixing by time division. In such a color liquid crystal display device, since one pixel is one picture element, three times the resolution can be obtained as compared with a color liquid crystal display device that performs side-by-side color mixture using a color filter, and furthermore, no color filter is used. Therefore, there is an advantage that light use efficiency is high.

As a liquid crystal display device that performs color display by using color mixture by time division, R (red), G (green), and B (blue) are provided behind a liquid crystal panel that performs black and white display.
And three color light sources that emit light of the primary colors are arranged. In the liquid crystal panel, writing of red image data, writing of green image data,
It is controlled and driven so that writing of blue image data is performed in a time-division manner. Correspondingly, in the color light source, at a predetermined timing with respect to a period during which writing of red image data is performed, a period during which writing of green image data is performed, and a period during which writing of blue image data is performed. , And is driven and controlled to emit red light, green light, and blue light in a time-division manner.

FIG. 7 shows the drive timing of the above-mentioned liquid crystal panel and each color light source. As shown in the figure, one frame period is time-divided into three, and is allocated to a red image period TR, a green image period TG, and a blue image period TB, respectively. In each of the periods TR, TG, and TB, a predetermined writing period TRW, TGW, TB in which an image signal corresponding to each color image is output to the liquid crystal display panel side.
W is set, and as shown in the figure, generally, image data is written line-sequentially from the scanning line at the top of the screen to the scanning line at the bottom of the screen. In each of the display periods TR, TG, and TB, a predetermined time TL from the lapse of a predetermined time TC to the end of the display period after elapse of the writing period and a rise period of the liquid crystal in the lowermost scanning line on the screen is anticipated. Each color light source is driven to emit light.

[0005]

However, the liquid crystal display device which performs color display by the above-described time-division driving has the following problems due to the voltage response time, particularly, the fall time of the liquid crystal. ing.

FIG. 8 is a diagram showing a voltage response time characteristic in a normally white mode liquid crystal panel. In this liquid crystal panel, the rise time (time until the transmittance becomes 100% to 10%) Tr until the liquid crystal rises in the direction of the electric field, and the rise time until the liquid crystal returns to the initial alignment state with no electric field or a smaller electric field. It is known that the falling time Tf (time from when the transmittance becomes 0% to 90%) is much longer than the falling time Tf. For this reason, in the above-described liquid crystal display device, when the writing of the next color image period is performed after the emission of the color light source in the previous color image period ends, the state of writing in the previous color image period is performed. Since the time required for the liquid crystal to fall from the liquid crystal alignment state is slow, crosstalk between colors occurs. In particular, the response of the liquid crystal tends to be insufficient at the lower pixel of the screen. Such a problem also applies to a normally black mode liquid crystal panel. here,
If the time for waiting for the fall of the liquid crystal is arranged after the image period of the previous color, there is a problem that the lighting time of the color light source after the next writing is performed becomes short.

Therefore, the present invention provides a liquid crystal display device and a method of driving the liquid crystal display device, which suppress the occurrence of crosstalk between colors so that the display quality is good and the lighting time of the monochromatic light source can be extended. It is intended to provide.

[0008]

SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a liquid crystal display device for performing color display, comprising a time-division three-primary-color light-emitting light source and a liquid crystal panel for performing time-division driven black and white display, Prior to an image signal writing period in a time-divided image display period of the liquid crystal panel, a liquid crystal reset signal output for collectively applying a liquid crystal reset signal for generating an electric field for returning liquid crystal alignment to the initial alignment state side to all pixels. It is characterized by comprising means.

According to such a configuration of the present invention, by applying the liquid crystal reset signal to all the pixels, the state written in the display period of the previous color image, that is, the alignment state of the liquid crystal is shifted to the initial alignment state side. You can go back. Therefore, the fall time longer than the rise time of the liquid crystal can be shortened, so that the influence of data written in the previous color pixel display period can be suppressed.

Further, according to the present invention, the potential of the liquid crystal reset signal is set to be the same as the center potential of the amplitude of the image signal, or the potential opposite to the image signal of the immediately preceding image display period with reference to the center potential of the amplitude of the image signal. It is preferable to use a polar potential.
According to such a configuration, it is possible to reliably apply an electric field that returns the alignment state of the liquid crystal to the initial alignment state side.

Further, according to the present invention, the liquid crystal reset signal output means outputs the liquid crystal reset signal in synchronization with the reset selection drive signal of the reset selection signal drive means for selecting all the scanning lines of the liquid crystal panel. Is preferred.
According to such a configuration, all the scanning lines of the liquid crystal panel are selected by the reset selection driving signal output from the reset selection signal driving means, and the liquid crystal reset signal is input to all the pixels to cause the liquid crystal to fall. It becomes possible.

In the present invention, it is preferable that the output time of the liquid crystal reset signal is set shorter than the fall time Tf of the liquid crystal. With such a configuration,
The fall time of the liquid crystal can be made shorter than the natural fall time Tf, and the influence of write data in the display period of the previous color image can be reduced to suppress the occurrence of crosstalk between colors.

Further, in the present invention, the liquid crystal reset signal output means may include a liquid crystal reset signal potential line and the liquid crystal reset signal potential line in synchronization with a reset selection drive signal of the reset selection signal drive means. And a switch circuit connected to the line. With such a configuration, it is possible to apply the liquid crystal reset signal voltage to all the pixels in synchronization with the reset selection signal for selecting all the scanning lines.

The present invention comprises a time-division three-primary-color light-emitting light source and a time-division driven liquid crystal panel for displaying black and white.
A method for driving a liquid crystal display device for performing color display,
Prior to an image signal writing period in a time-divided image display period of the liquid crystal panel, a liquid crystal reset signal for generating an electric field for returning the liquid crystal alignment to the initial alignment state side is collectively applied to all pixels. .

According to such a configuration of the present invention, by applying the liquid crystal reset signal to all the pixels, the data written in the display period of the previous color image, that is, the alignment state of the liquid crystal is shifted to the initial alignment state side. You can go back. For this reason,
The fall time longer than the rise time of the liquid crystal can be shortened, which has the effect of suppressing the influence of data written in the previous color pixel display period and suppressing the occurrence of crosstalk between colors.

Further, in the present invention, it is preferable that the liquid crystal reset signal is set to have the same potential as the center potential of the amplitude of the image signal or a polarity opposite to the image signal in the immediately preceding image display period with reference to the center potential. . According to such a configuration, an electric field that returns the alignment state of the liquid crystal to the initial alignment state side can be reliably applied, and the fall time of the liquid crystal can be shortened. In addition, the writing can be completed quickly, the lighting time of the light emitting light source can be lengthened, and the display image quality can be improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of a liquid crystal display device and a method of driving the same according to the present invention will be described below with reference to the drawings.

(Embodiment) FIGS. 1 to 5 show an embodiment of the present invention. This embodiment is a liquid crystal display device that performs time-division driving and performs color display.

As shown in FIG. 1, a liquid crystal display device 1 of the present embodiment has a transmission type active matrix type liquid crystal panel 2 having a liquid crystal reset function for all pixels and performing black and white display, and has three primary colors. R (red), G (green), B (blue)
And a backlight system 3 having three monochromatic light sources, that is, a red light source 3R, a green light source 3G, and a blue light source 3B, each of which independently emits light.

The liquid crystal display device 1 performs color display by time division driving. In order to suppress the occurrence of flicker (flicker) due to color switching, the three primary colors are reduced to about 1/6.
It is necessary to switch within 0 seconds or less. Therefore, the liquid crystal panel 2 performs R, G, B at 180 Hz, which is three times 60 Hz.
Is set to be written.

The red light source 3R, the green light source 3G, and the blue light source 3B provided in the backlight system 3 are driven to emit light in a time-division manner in correspondence with image writing of each color on the liquid crystal panel 2. Is set. As shown in FIG. 1, the backlight system 3 includes a red light source 3R, a green light source 3G, and a blue light source 3B, which are arranged along a longitudinal direction of one side surface of the light guide plate 31 having a predetermined thickness. The edge light type units are arranged adjacent to each other so as to be parallel to each other. In addition, in the backlight system 3, a reflection plate (not shown) is arranged on the back side of the light guide plate 31, and a prism sheet and a diffusion plate (not shown) are sequentially arranged on the front side of the light guide plate 31. In addition,
Since the light guide plate 31, the reflection plate, the prism sheet, and the diffusion plate are arranged corresponding to the pixel matrix portion (display area) of the liquid crystal panel 2, they are designed to have a size that covers the entire surface of the pixel matrix portion. ing.

Next, the configuration of the main part including the drive system of the liquid crystal display device 1 of the present embodiment will be described with reference to FIG. As shown in the figure, the liquid crystal display device 1 of the embodiment includes a liquid crystal panel 2, a red light source 3R, a green light source 3G, and a blue light source 3.
B, the above-described backlight system 3, the timing controller 11, and the field memories 12R, 12G, and 12B for storing image data corresponding to each of the three primary colors.
A scanning driver 13 for selecting scanning lines of the liquid crystal panel 2 in a line-sequential manner, a data driver 14 for writing image data, and light emitting sources 3R, 3G, and 3B, respectively, which emit light corresponding to the light emitting sources. And driving circuits 15R, 15G, and 15B to be driven. In the present embodiment, since the light-emitting light sources 3R, 3G, and 3B of each color are formed of fluorescent tubes, the driving circuits 15R, 15G, and 15B are formed of inverter circuits.

In the liquid crystal display device 1 having such a configuration, the timing controller 11 controls all timings of the liquid crystal display device 1 which is driven in a time-division manner.
First, an image signal is sampled by a sampling circuit (not shown) and stored in the field memories 12R, 12G, and 12B corresponding to R, G, and B, respectively. Next, the timing of the image signals stored in the field memories 12R, 12G, and 12B is controlled by the timing controller 11 so as to be sent to the data driver 14 for each color. Here, as shown in the timing chart of FIG. 4, one frame period is divided into three periods (hereinafter, referred to as three periods).
This is called a subframe period. 3) Since image signals for three colors are sent to TR, TG, and TB one by one, the speed is about three times as fast as sampling. In the scanning driver 13, scanning lines are sequentially selected line by line, and an image signal is written from the data driver 14 to the pixel in synchronization with the selection pulse. The period tw shown in FIG. 4 is a state in which the LCD drive signal is output, that is, a state in which each color image signal is written, and writing is performed in this image signal writing period tw. The image signal writing period tw is set to the same time in each of the sub-frame periods TR, TG, and TB.

On the other hand, the backlight system 3 driven by time division is also controlled by the timing controller 11. That is, for example, when the pixel signal for red is written in the sub-frame period TR for displaying the red image, FIG.
As shown in (2), after a lapse of a predetermined time (including the liquid crystal response time) 2 from the writing period tw, the light emission drive signal is transmitted from the timing controller 11 to the drive circuit 15R corresponding to R.
To be output. T3 shown in FIG. 4 indicates the pulse width of the red light source 3R. As shown in the figure, the light emission drive signals corresponding to the green and blue image signals are also transmitted from the timing controller 11 to the drive circuits (15G, 15B) corresponding to each color during the sub-frame period (TG, TB) of each color. Output green light source 3 respectively
The G, blue light source 3B emits light of pulse width t3.
As described above, in one sub-frame period, a writing period tw for writing an image signal, a predetermined time (including a liquid crystal response time in a pixel arranged on a scanning line scanned last in the sub-frame period) t2, And a light emission period t3 having a pulse width of each color light.

As shown in FIG. 3, in the liquid crystal display device 1 of the present embodiment, scanning lines Y1, Y2,.
The scanning line driving circuit (the scanning driver 13 in FIG.
Corresponding to ) 110 and odd-numbered data lines X1, X
, Xm−1, an odd data line driving circuit (included in the data driver 14 in FIG. 2) 120 and an even data line driving circuit driving the even data lines X2, X4,. (Included in the data driver 14 of FIG. 2.) 130 and odd-numbered data lines X1, X3,.
An odd-numbered data line reset circuit 140 for outputting a liquid crystal reset signal to Xm-1, and even-numbered data lines X2, X4,
, An even data line reset circuit 150 for outputting a liquid crystal reset signal to Xm. Note that the liquid crystal panel 2 is of the active matrix type as described above, and the symbol Q shown in FIG. 3 indicates a thin film transistor (TFT) as a switching element of each pixel portion, the symbol Cs indicates a storage capacitor, and the symbol CLC indicates a liquid crystal capacitor. ing.

The scanning line driving circuit 110 supplies the scanning lines Y1, Y2,..., Yn at a predetermined timing based on a power supplied from an external control circuit (not shown), a reference clock from the timing controller 11, and an inverted clock thereof. An N-bit shift register 111 for applying the scanning signals G1, G2,... In the scanning line driving circuit 110, the shift register 111 and each of the scanning lines Y1 to Yn are connected via a gate 112 and an inverter 113. An enable terminal 114 is connected to the input side of each gate 112. A reset selection signal is output to the enable terminal 114 at a timing described later.

The odd-numbered data line driving circuit 120 includes an m / 2-bit shift register 121, a u × m / 2-bit latch A122 and a latch B123, and an m / 2-bit D / D
An A converter 124 and a sampling circuit 125 are provided. In the odd-numbered data line drive circuit 120, the above-described scan line drive circuit 110 scans the scan signals G1, G2, G2 based on the power supplied from an external control circuit (not shown), the reference clock from the timing controller 11, and the inverted clock thereof. .., In accordance with the timing of applying Gn, for each of the plurality of image signal lines 126,
The sampling circuit drive signal output from the shift register 121 is supplied to the sampling circuit 125 via each of the sampling circuit drive lines 127 at a predetermined timing for each of the odd-numbered data lines X1, X3,. It is supposed to. The image signals D1T and D2 from the image signal line 126 sampled in this way.
T,... DuT are latch A122, latch B123, D
Odd-numbered data line X via A / A converter 124
1, X3,..., Xm-1.

The configuration of the even-numbered data line driving circuit 130 is similar to that of the odd-numbered data line driving circuit 120, and is similar to that of the m / 2-bit shift register 131 and the u × m / 2-bit latch A1.
32, a latch B 133, an m / 2-bit D / A converter 134, and a sampling circuit 135. In the even-numbered data line drive circuit 130, the above-described scan line drive circuit 110 scans the scan signal G based on a power supplied from an external control circuit (not shown), a reference clock from the timing controller 11, and an inverted clock thereof.
1, G2,..., Gn
For each of the plurality of image signal lines 136, the shift register 1 is provided for each even-numbered data line X2, X4,.
The sampling circuit drive signal output from 31 is supplied to the sampling circuit 125 via each of the sampling circuit drive lines 137 at a predetermined timing. The image signals D1B, D2B,... DuB from the image signal lines 136 thus sampled.
Are connected to the even-numbered data lines X2, X4,... Via a latch A132, a latch B133, and a D / A converter 134.
Xm. Thus, in the present embodiment, the odd data line driving circuit 120 and the even data line driving circuit 130 are provided, and the polarity can be inverted for each odd line and each even line. It has a configuration that can be performed. In this case, in synchronization with the reset selection signal input to the enable terminal 114 incorporated in the scanning line driving circuit 110,
The liquid crystal reset signal voltages output from the odd data line reset circuit 140 and the even reset circuit 150 can also be optimized for each polarity.

The odd data line reset circuit 140 is connected to the odd data lines X1, X3,..., Xm-1 and to the liquid crystal reset signal voltage Vodd.
, And the liquid crystal reset signal line 142 for outputting the odd data lines X1, X3,..., Xm-1 in synchronization with the reset selection signal output to the enable terminal 114 of the scanning line drive circuit 110. And a reset switch drive signal line 143 for outputting a liquid crystal reset signal RSB by making the reset signal line 142 conductive.

Similarly, the even data line reset circuit 150
Are connected to the even data lines X2, X4,... Xm, and the liquid crystal reset signal voltage V connected to the even data lines via the switch circuit 151.
The liquid crystal reset signal line 152 for outputting an even signal and the switch circuit 151 are driven in synchronization with the reset selection signal output to the enable terminal 114 of the scanning line driving circuit 110 to reset the even data lines X2, X4,. And a reset switch drive signal line 153 that outputs a liquid crystal reset signal RST by making the signal line 152 conductive.

In the liquid crystal display device 1 having such a configuration, the timing controller 11 samples the sampled image signals D1T, D2T,.
Bn and D2B are controlled so as to be written into the pixel portions along the scanning lines Y1, Y2,... Then, after writing the image data in the image period of each color, the light emitting light source 3R of the corresponding color,
One of 3G and 3B is turned on. After the end of the previous color image period, a liquid crystal reset signal for returning the liquid crystal to the initial alignment side is output to all the pixels at the beginning of the next color image period. To output this liquid crystal reset signal collectively for all pixels, a reset selection signal INH is output to the enable terminal 114 of the scanning line drive circuit 110 at a predetermined timing to select all the scanning lines, and the reset switch is synchronized with this timing. The drive signal lines 143 and 153 are output and the switch circuits 141 and 151 are output.
To reset the liquid crystal reset signals RSB and RS to all data lines.
Output T. By the output of the liquid crystal reset signal, the liquid crystal in all the pixel portions can be lowered to the initial alignment side.
In addition, in order to invert the polarity of the liquid crystal driving voltage every predetermined period, in the present embodiment, the potential of the liquid crystal reset signal is
The potential is set to a reference potential (for example, 0 V) for polarity inversion or a potential on the opposite polarity side to a potential at which liquid crystal rises.

Next, the operation of the liquid crystal display device 1 of the present embodiment will be described with reference to the timing chart of FIG. As shown in the figure, one frame period is divided into three periods (hereinafter, referred to as three periods).
This is called a subframe period. 3) Image signals for three colors are sent to TR, TG, and TB one by one. Scan line drive circuit 110
In the sub-frame period, all the lines are sequentially selected line by line in the sub-frame period, and the image signal is sequentially transmitted from the odd data line driving circuit 120 and the even data line driving circuit 130 in synchronization with the selection pulse. Is written to the pixel corresponding to the pixel, and writing is performed on the entire screen. The writing period tw required for writing the image signal is set to the same time in each of the sub-frame periods TR, TG, and TB.

In this embodiment, each sub-frame period T
During a predetermined period t1 at the beginning of R, TG, and TB, the reset selection signal Sr is output to all the scanning lines to set all the scanning lines to the selected state. Liquid crystal reset signals RSB and RST are output to all data lines (odd data lines and even data lines) in synchronization with the reset selection signal Sr, and the liquid crystal alignment is reset for all the screens (all pixels) at once. . Thereafter, as shown in FIG. 3, a color image is written by scanning all the scanning lines line by line during the pixel writing period tw of each color. Then, after a writing period tw, a period t2 in which the rise time of the liquid crystal is taken into account has elapsed, and the light emitting light source of the color corresponding to the writing image is turned on.

The backlight system 3 including the light emitting sources 3R, 3G and 3B is also a timing controller 11
Is controlled by That is, for example, when the pixel signal for red is written in the sub-frame period TR for displaying the red image, as shown in FIG. 4, after the lapse of the period t2 from the writing period tw, the respective light emitting light sources are switched between the colors. Light is emitted during the same period t3.

Here, the odd data line reset circuit 140
The liquid crystal reset signals RSB and RST output from the even data line reset circuit 150 will be described.

In the present embodiment, attention is paid to the phenomenon that the falling time Tf is much longer than the rising time Tr of the liquid crystal when the liquid crystal panel 2 is in the normally white mode (the same applies to the normally black mode). At the beginning of the sub-frame period (or at the end of the sub-frame period), an electric field is applied to all the pixels in a direction in which the alignment of the liquid crystal is forcibly returned to the initial alignment state. That is, the fall time Tf is forcibly set by applying, for example, OV or a voltage having a polarity (relative to the reference voltage) opposite to the write drive voltage to the pixel electrode in which the image data is written in the previous subframe period. This is shortened to: Here, it is not necessary to completely return the liquid crystal to the initial alignment state.

As described above, the long fall time Tf can be shortened by inputting the liquid crystal reset signal to all the pixels at the beginning of each subframe period. As shown in FIG. 4, on the scanning line Y1 at the top of the screen, writing is performed at the beginning of each of the red, green, and blue image writing periods tw. At this time, in the pixel portion arranged along the scanning line Y1, the liquid crystal is Since it has not completely returned to the initial alignment state, the image signal D1
The rise of the liquid crystal at the time of writing T, D2T,... DuT, D1B, D2B, etc. is easily performed. That is, since the rise time Tr of the liquid crystal is much shorter than the fall time Tf as shown in FIG. 8, the rise time is further increased when the state of the liquid crystal is between the rise state and the fall state. Can be shortened.
Conversely, depending on the image signal, there may be a signal that further lowers the liquid crystal. However, the writing time in the scanning line Y1 is equal to the entire writing period tw in the sub-frame period.
, It falls sufficiently before lighting is performed.

On the scanning line Yn at the bottom of the screen, the scanning signal Gn is output at the end of the writing period tw. At this time, the liquid crystal sufficiently falls due to the liquid crystal reset signal output at the beginning of the sub-frame period. Since the liquid crystal display is in the initial state (initial alignment state), it is only necessary to secure a relatively short rising period Tr of the liquid crystal as a time until the light emitting light source is turned on.

Here, the response of the liquid crystal will be described with reference to FIG. 5 taking a sub-frame period for a red image as an example.

First, when a reset selection signal is output to the enable terminal as shown in FIG.
During this period, the liquid crystal reset signal is input. At this time, for example, an OV liquid crystal reset signal is input to the pixel electrode, and the liquid crystal in the state written in the previous blue image sub-frame is forcibly driven to the falling state during the period t1, and the transmittance is reduced. Changes from, for example, 0% to, for example, 50%. Thereafter, when a write signal is input to the pixel electrode, the pixel electrode potential becomes VP, and the liquid crystal is activated by a driving electric field. Since the rise time tr at this time is a rise from a position where the liquid crystal is in the intermediate alignment state, FIG.
The rise of the liquid crystal is completed in a time shorter than the rise time Tr shown in FIG. Thereafter, this state is substantially maintained until the lighting of the red light source 3R is completed by the action of the storage capacitor Cs.

As shown in the lower part of FIG. 5, in the scanning line Yn at the lowermost part of the screen, during the period t1 selected by the reset selection signal, the liquid crystal reset signal is input to the pixel electrode, and Driving for lowering the liquid crystal is performed in the same manner as the scanning line Y1. After that, since there is time until the writing of image data, the liquid crystal gradually falls from the intermediate alignment state and the transmittance becomes 100%. The time tf required for the fall at this time is shorter than Tf shown in FIG. When the write selection signal is input to the scanning line Yn, an image signal is input from the data line in synchronization with the input, and the rising of the liquid crystal starts. The time required for this rise is shown in FIG.
Is the same as the rising time Tr shown in FIG. For this reason, if a relatively short rising time Tr is secured after the writing of the scanning line Yn, the red light emitting light source 3R can be turned on.

As described above, in the present embodiment, since the falling of the slow liquid crystal can be shortened by falling with the liquid crystal reset signal voltage, it is sufficient to secure only the rising time after writing. It should be noted that such resetting of the alignment state of the liquid crystal can effectively eliminate at least the influence of data written in the previous sub-frame period without performing it for a sufficient time. There is. Further, according to the present embodiment, since the reset period for causing the liquid crystal to fall toward the lower side of the screen can be lengthened, the effect of improving the response of the liquid crystal at the lower side of the screen can be improved. Play.

Although the embodiments have been described above, the present invention is not limited to the embodiments, and various changes accompanying the gist of the configuration are possible. For example, in the above embodiment, the liquid crystal reset signal is arranged at the beginning of the sub-frame, but may be arranged at the end of the sub-frame. Further, in the above-described embodiment, the data line driving circuit is provided for each of the odd data line and the even data line. However, when the line inversion or the dot inversion is not planned, the present invention is not limited to this. In the above-described embodiment, the case where the liquid crystal display panel 2 is in the normally white mode has been described. However, it is needless to say that the present invention can be applied to the case where the liquid crystal display panel 2 is in the normally black mode. FIG.
As shown in (2), paying attention to the fact that it takes some time until the liquid crystal actually starts moving after changing the voltage, the liquid crystal does not respond at least for the time of the initial rising Tr0. For example, a configuration in which the lighting time is extended or a configuration in which the next writing is performed may be used. For this reason, a long lighting time can be secured after all, and there is an effect of improving display image quality.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram showing a main part of the configuration of the embodiment.

FIG. 3 is a circuit diagram of the liquid crystal display device of the embodiment.

FIG. 4 is a timing chart showing a method for driving the liquid crystal display device of the embodiment.

FIG. 5 is a diagram showing a relationship between drive timing, pixel electrode potential, and transmittance of the liquid crystal display device of the embodiment.

FIG. 6 is a diagram showing an optical response of a liquid crystal.

FIG. 7 is a timing chart showing a driving method of a conventional time-division driving color liquid crystal display device.

FIG. 8 is a diagram showing an optical response of a liquid crystal.

[Explanation of symbols]

 Reference Signs List 1 liquid crystal display device 2 liquid crystal panel 3 backlight system 3R red light source 3G green light source 3B blue light source 11 timing controller 12R, 12G, 12B field memory 13 scan driver 14 data driver 15R, 15G, 15B drive circuit 110 scan line drive Circuit 114 Enable terminal 120 Odd data line drive circuit 130 Even data line drive circuit 140 Odd data line reset circuit 141 Switch circuit 142 Liquid crystal reset signal line 143 Reset switch drive signal line 150 Even data line reset circuit 151 Switch circuit 152 Liquid crystal reset signal line 153 Reset switch drive signal line

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Claims (8)

[Claims] 1. A liquid crystal display device for performing color display, comprising: a time-division three-primary-color light-emitting light source; and a liquid-crystal panel that performs black-and-white display driven in a time-division manner. A liquid crystal reset signal output means for collectively applying, to all pixels, a liquid crystal reset signal for generating an electric field for returning the liquid crystal alignment to the initial alignment state prior to an image signal writing period in the period. apparatus. 2. The liquid crystal reset signal has the same potential as a center potential of the amplitude of the image signal.
The liquid crystal display device according to claim 1. 3. The liquid crystal according to claim 1, wherein the liquid crystal reset signal is a potential having a polarity opposite to that of the image signal in the immediately preceding image display period with reference to a center potential of the amplitude of the image signal. Display device. 4. The liquid crystal reset signal output means outputs the liquid crystal reset signal in synchronization with a reset selection drive signal of a reset selection signal drive means for selecting all the scanning lines of the liquid crystal panel. The liquid crystal display device according to any one of claims 1 to 3. 5. The liquid crystal display device according to claim 1, wherein an output time of the liquid crystal reset signal is set shorter than a fall time Tf of the liquid crystal. 6. The liquid crystal reset signal output means connects the liquid crystal reset signal potential line to a data line of the liquid crystal panel in synchronization with a liquid crystal reset signal potential line and a reset selection drive signal of the reset selection signal drive means. The liquid crystal display device according to claim 4, further comprising: a switch circuit configured to perform the operation. 7. A method for driving a liquid crystal display device for performing color display, comprising: a time-division three-primary-color light-emitting light source; Prior to an image signal writing period in an image display period, a liquid crystal reset signal for generating an electric field for returning liquid crystal alignment to the initial alignment state side is collectively applied to all pixels, and a driving method of the liquid crystal display device is characterized in that . 8. The liquid crystal reset signal is set to the same potential as the center potential of the amplitude of the image signal or to a potential of the opposite polarity to the image signal in the immediately preceding image display period with reference to the center potential. The method for driving a liquid crystal display device according to claim 7.