JP2000221949A - Display device - Google Patents

Abstract

(57) [Summary] In a display device for displaying a video signal such as a personal computer, when a scan converter that performs signal processing such as enlargement / reduction interpolation performs signal processing in two phases, an odd number of OSD signals are output.・ It is necessary to add separately for each even number. A one-phase output of an OSD IC is developed into two phases of odd-numbered pixels and even-numbered pixels, and a decrease in dot clock speed due to the two-phase development is accelerated by a memory and input to a two-phase input of a scan converter. The disadvantage that characters and graphics of the OSD are enlarged twice in the horizontal direction is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device such as a liquid crystal projector, and to an on-screen display function.

[0002]

2. Description of the Related Art In recent years, with the development of graphical interfaces such as Windows, personal computers (hereinafter referred to as PCs) have become widespread.

[0003] Generally, VGA is used as an output video signal of a PC.
(Video Graphics Array), SVGA (Super Video Gr)
aphics Array), XGA (Extended Video Graphics Ar
ray), SXGA (Super Extended Video Graphics Arr)
ay), there are signals with different numbers of screen display pixels, and these signal specifications are VESA (Video Electronics Standards
Assosiation).

A matrix display device such as a liquid crystal projector for displaying an output video signal of a PC has 1024 horizontal dots and 768 vertical lines when its screen display pixel is compatible with, for example, XGA. Such an XGA matrix display device has, for example, 800 dots horizontally and 600 dots vertically.
If you want to display the SVGA signal of the line on the entire screen,
It is necessary to expand and interpolate the VGA signal to the XGA signal,
The signal processing LSI that performs this enlargement interpolation is called a scan converter. When the SXGA signal of 1280 dots in the horizontal direction and 1024 lines in the vertical direction is to be reduced and displayed in the screen, the above-mentioned scan converter performs the reduction interpolation.

[0005] However, if the signal becomes XGA or more, the first
The frequency for pixels (hereinafter referred to as dot clock) is 60M
Hz or more, and when such a high-speed signal is subjected to signal processing by a scan converter, the circuit operation speed inside the LSI may not be able to catch up with the signal as it is.

Therefore, as shown in FIG.
At the same time as sampling by the converter, it is divided into two phases of odd-numbered pixels and even-numbered pixels, and the output clock of the AD converter, that is, the dot clock to the scan converter, is halved. Further, signal processing is performed inside the scan converter while dividing the signal into two phases. By performing the two-phase processing in this way, the corresponding signal of the scan converter can be doubled as compared with the one-phase signal.

On the other hand, in a display device such as a liquid crystal projector, an on-screen display (hereinafter referred to as OSD) for overwriting characters and graphics on a display screen so that various adjustments such as contrast and brightness adjustments can be performed by a user. Function). O
SD function is an OS that generally generates characters and graphics
Using the D IC, the output of the OSD IC is added to the video signal. Generally, a scan converter has an OSD addition function for switching between a video signal and an OSD signal.

[0008]

When the scan converter is performing two-phase processing, the scan converter has two phases.
There is a phase OSD signal input, and it is necessary to add the OSD signal separately for each odd / even number.

On the other hand, an OSD IC is usually NTSC (Nati
Many have been developed for low-speed signals such as televisions for the onal Television System Committee, and their output is only one phase. Here, OSD is input to the two-phase input of the scan converter.
When the one-phase outputs of the ICs are connected at the same time, the same OSD signal is added to a pair of odd-numbered / even-numbered signals as shown in FIG.
It will be doubled.

[0010]

Therefore, the one-phase output of the OSD IC is developed into two phases of odd and even signals, and the reduction of the dot clock speed due to the two-phase development is speeded up with a memory to provide a two-phase input to the scan converter. By entering
The problem that the character or graphic of D is enlarged twice in the horizontal direction can be eliminated.

[0011]

FIG. 1 shows a first embodiment of the present invention.

The feature of this embodiment is that the one-phase output of the OSD IC is developed into two phases of odd-numbered pixels and even-numbered pixels. To enter the OSD
It is possible to solve the problem that the character or graphic is enlarged twice in the horizontal direction.

FIG. 1 is a block diagram showing a first embodiment of the present invention. An OSDIC 1, a serial / parallel converter 2, a memory 3, a memory control circuit 4, an AD converter 5, a scan converter 6, a DA converter And a display unit 8. The memory control circuit 4 includes a write control circuit 41 and a read control circuit 42, and the scan converter 6 includes an enlargement / reduction processing unit 61 and an OSD addition unit 62.

The operation of this embodiment will be briefly described with reference to FIG.

An analog video signal input from a signal source such as a PC is converted into a digital signal by an AD converter 5 and further divided into two phases of an odd pixel and an even pixel as shown in FIG. On the other hand, the OSDIC 1 outputs a one-phase OSD signal. This one-phase OSD signal is divided by the serial / parallel converter 2 into two phases of odd-numbered pixels and even-numbered pixels. At this time, since the dot clock speed is reduced, a memory 3 such as an input / output asynchronous memory such as a FIFO is used, and the write control circuit 41 of the memory control circuit 4 controls the OSDIC 1 to 2.
When writing and reading the phase output, the read control circuit 42 reads the phase output at, for example, twice the clock speed of the writing.

Thus, the OSD signal can be converted into a two-phase signal corresponding to the scan converter 6.

The scan converter 6 performs enlargement / reduction interpolation processing on the two-phase video signal input from the AD converter 5 so as to correspond to the number of pixels of the display unit 8, and further converts the signal obtained by adding the two-phase OSD signal into a DA signal. Output to the converter 7. The D / A converter 7 converts the two-phase digital video signal into a one-phase analog signal, which is received by the display unit 8 and projected on a screen in a liquid crystal projector, for example.

Next, the two-phase conversion of the OSD signal will be described in more detail with reference to FIGS. FIG. 2 shows an example of the internal configuration of the serial / parallel converter 2, and FIG. 3 is an operation timing chart thereof. 2, the serial / parallel converter 2 includes latches 21 to 24, a timing controller 25, and switcher circuits 26 and 27. The operation of the serial / parallel converter 2 will be described with reference to the timing chart of FIG. 3. First, the timing controller 25 generates a signal 2 to a signal 5 and a signal 10 in response to a signal 0 which is a main clock. Here, signal 0 is the operating clock of OSDIC1. OSDIC
For example, if an OSD (MB90096) manufactured by Fujitsu is used for 1, the maximum operating frequency is 80 MHz, so the signal 0 is a clock of, for example, 80 MHz. Signals 2 to 5 are trigger signals obtained by dividing signal 0 by 4 and shifting each signal by 1 clock, and signal 10 is a signal obtained by dividing signal 0 by 4 to have a duty ratio of 50%. These signals can be generated by, for example, a counter circuit and a shift register circuit.

The latches 21 to 24 receive the trigger signal of the signal 2 to the signal 5, and take in the signal 1 which is the output of the OSDIC 1. The result is signal 6 to signal 9. That is, latch 2
1 and the latch 22 fetch even two pixels, and the latch 2
3 and the latch 24 fetch two odd pixels. Thereafter, the outputs of the latch 21 and the latch 22 are switched by the switcher circuit 26,
By switching the outputs of the latches 23 and 24 at the timing of the signal 10 by the switcher circuit 27, an even pixel signal can be output as the signal 11 and an odd pixel signal can be output as the signal 12. Thus, a one-phase signal can be converted into a two-phase signal.

However, as shown in FIG. 3, the signals 11 and 12 which are two-phase outputs are に 対 し て of the clock speed of the signal 0 which is the main clock, that is, 40 MHz. Therefore, it is necessary to increase the clock speed in the memory control circuit 4. FIG. 4 is a timing chart of the clock speed increase by the memory control circuit 4. The write control circuit 41 supplies a clock having a half frequency of the signal 0 in FIG. 3 to the memory 3 in accordance with the OSD two-phase output, and the read control circuit 42 supplies a read clock having the same frequency as the signal 0 to the memory 3 in accordance with the OSD two-phase output. To supply. Thus, a signal output from the memory 3 can be read at a clock frequency corresponding to the scan converter 6, for example, 80 MHz.

As a result, as shown in the OSD addition timing chart of FIG. 5, by inputting the OSD two-phase signal to the scan converter 6,
Can be added in accordance with the phase signal.
D addition can be performed.

Here, in this embodiment, the FIFO is stored in the memory 3.
In the above description, a dual port memory (input and output data ports are separated) is described as an example, but a single port such as an SDRAM (input and output data ports are shared)
It may be a memory. FIG. 6 shows a configuration example of a memory and a memory control circuit when a single-port memory is used. FIG. 6 includes a single port memory 32 and a memory control circuit 4. The memory control circuit 4 includes a bidirectional buffer 45, an input data buffer 46, an output data buffer 47, a buffer control circuit 48, and a write / read control circuit 49. The input data buffer 46 and the output data buffer 47
A line memory such as O may be used. FIG. 7 is a timing chart showing the operation of FIG.

Referring to FIGS. 6 and 7, the write / read operation of the single port memory 32 will be described. The signal sent from the serial / parallel converter 2 is stored for a certain period in the input data buffer 46 in the memory control circuit 4, and is written to the single port memory 32 by changing the clock frequency (see the signal in FIG. 7). Next, the image data stored in the single-port memory 32 is read out for a certain period of time, stored in the output data buffer 47, and output while changing the clock frequency (see the signal in FIG. 7).

This operation is repeated, for example, three times within one horizontal period. Here, when reading a signal from the output data buffer 47, the frequency conversion can be performed by increasing the clock frequency from the signal. The input data buffer 4
6. The output data buffer 47 is controlled by the buffer control circuit 48, and the write / read control of the single port memory 32 is performed by the write / read control circuit 49. The input / output switching of the data port of the single port memory 32 is performed by the bidirectional buffer 45. Here, the operation example of FIG. 7 shows an example in which the write / read operation is repeated three times within one horizontal period.
The number of repetitions and the period are arbitrary.

FIG. 4 shows an example in which the output of the serial / parallel converter 2 is twice frequency-converted by the memory 3, but the frequency conversion rate may be any value within the operating frequency range of the memory 3.

As described above, the serial / parallel converter 2
By using the above, the one-phase signal of the OSDIC 1 can be converted into a two-phase signal, and the problem that characters and graphics of the OSD are doubled in the horizontal direction can be eliminated.

FIG. 8 shows a second embodiment of the present invention.

A feature of this embodiment is that the same effect can be obtained even if the order of the serial / parallel converter 2 and the memory 3 in the first embodiment is reversed.

FIG. 8 is a block diagram showing a second embodiment of the present invention, in which parts corresponding to those in FIG. 1 which is a configuration example of the first embodiment are denoted by the same reference numerals. The difference is that the order of the serial / parallel converter 2 and the memory 3 is reversed. Otherwise, the configuration is the same as that of the first embodiment, and the description is omitted. FIG. 9 is a timing chart showing the operation of the second embodiment.

The operation of this embodiment will be described with reference to FIGS.

The OSDIC 1 outputs a one-phase OSD signal. For example, OSD1 manufactured by Fujitsu (MB900
96), the maximum operating frequency is 80
MHz, the frequency of the OSD signal is, for example, 80M
Hz. The clock frequency of this one-phase signal is multiplied by 1.5 by the memory 3, for example, as shown in FIG.
To Thereafter, the serial / parallel converter 2 performs two-phase expansion of the even-numbered and odd-numbered pixels, and outputs the result to the scan converter 6. At that time, the operating frequency becomes 1/2, that is, 60 MHz. The operations of the memory 3 and the serial / parallel converter 2 alone are the same as in the first embodiment, and will not be described.

Although FIG. 9 shows an example in which the OSD signal is frequency-converted to 1.5 times by the memory 3, the frequency conversion rate may be any value within the operating frequency range of the memory 3.

As described above, the serial / parallel converter 2
Even if the order of the memory 3 is reversed, the same effect as in the first embodiment can be obtained.

FIG. 10 shows a third embodiment of the present invention.

The feature of this embodiment is that the two-phase expansion of the even-numbered and odd-numbered pixels can be performed without using a serial / parallel converter by utilizing the lower / upper write enable function of the memory.

FIG. 10 is a block diagram showing a third embodiment of the present invention, in which parts corresponding to those in FIG. 1 which is a configuration example of the first embodiment are denoted by the same reference numerals. The difference is that the serial / parallel converter 2 is deleted and the memory 3 is
The memory 31 having a built-in upper write enable function has been changed, and the write control circuit 41 has been changed to a write control circuit 43 having a built-in lower / upper write enable generation function. FIG. 11 is a timing chart showing the operation of the third embodiment.

The operation of this embodiment will be described with reference to FIGS.

The OSDIC 1 outputs a one-phase OSD signal. When the memory 31 captures the two pixels of the one-phase signal, the memory 31 fetches the lower and upper two times into one address. That is, as shown in FIG. 11, the lower / upper write enable is controlled so that the input data D0 is taken in the lower part of the address A0 and the input data D1 is taken in the upper part of the address A0. By repeating this, as shown in the write transition diagram of FIG. 11, even data is written in the lower part of each address and odd data is written in the upper part. Next, when reading from the memory 31,
By reading the lower and upper bits of each address at the same time, it is possible to develop even and odd two phases.

The memory 31 having the lower / upper write enable function is, for example, an SDRAM manufactured by Hitachi.
(HM52216165) may be used.

Here, the control is performed such that even-numbered data is written in the lower part of each address and odd-numbered data is written in the upper part. However, the same effect can be obtained by writing odd-numbered data in the lower part and even-numbered data in the upper part.

As described above, by utilizing the lower / upper write enable function of the memory 31, it is possible to perform the two-phase expansion of the even and odd pixels without using the serial / parallel converter 2.

FIG. 12 shows a fourth embodiment of the present invention.

The feature of this embodiment is that the LUT (Look Up Tabl
e: reference memory) to improve the OSD display color.

Normally, the output signal of the OSDIC 1 is 4 bits of RGB + halftone, and its display capability is 16 colors. However, since 16 colors cannot express a delicate graphic image, 16 out of 256 colors can be expressed by expanding the OSD signal to, for example, 8 bits using an LUT.

FIG. 12 is a block diagram showing a fourth embodiment of the present invention, in which parts corresponding to those in FIG. 1 which is a configuration example of the first embodiment are denoted by the same reference numerals. The different part is L
The UT 10 has just been added. Otherwise, the configuration is the same as that of the first embodiment, and the description is omitted. FIG. 13 shows L
FIG. 4 is an address map diagram showing an operation of the UT 10.

The operation of this embodiment will be described with reference to FIGS.

The two-phase OSD signal output from the memory 3 is output to the LUT 10 in the same operation as in the first embodiment.
For example, each one-phase signal is 4-bit data of RGB + halftone. The LUT 10 recognizes the transmitted 4-bit data as an address, and outputs the data stored at that address to the scan converter 6. When outputting data,
For example, it is expanded to 8 bits, the upper 4 bits are input data, and the lower 4 bits output 4-bit data stored in the LUT 10. As a result, the OSD signal becomes 16 out of 256 colors.
Can be extended to color representation.

In this embodiment, an example of conversion from 4 bits to 8 bits by the LUT 10 has been described, but the conversion rate may be any value.

As described above, by using the LUT, the OSD
Can be improved in display color.

FIG. 14 shows a fifth embodiment of the present invention.

The feature of this embodiment is that the OSD display is performed on the entire display screen having a resolution higher than the OSDIC by using the write enable function of the memory.

Normal OSDIC 1, for example, OSD manufactured by Fujitsu
In the case of (MB90096), the maximum resolution is only 768 × 512, which is comparable to that of the NTSC signal. For example, OSD display cannot be performed on the entire XGA screen (1024 × 768). Therefore, the OSD signal can be displayed on the entire screen by loading the OSD signal into the memory in several frames.

FIG. 14 is a block diagram showing a fifth embodiment of the present invention, in which parts corresponding to those in FIG. 1 which is a configuration example of the first embodiment are denoted by the same reference numerals. The different point is that a write control circuit 44 having a write enable function is used. Otherwise, the configuration is the same as that of the first embodiment, and the description is omitted. FIG. 15 shows the write control circuit 4.
FIG. 4 is a conceptual diagram showing operations of a memory 4 and a memory 3.

The operation of this embodiment will be described with reference to FIGS.

In this embodiment, the OSD signal is written into the memory 3 in several frames. First, as in frame 1 in FIG. 15, the write enable is controlled to write the OSD signal only on the upper left map of the memory 3. In the frame 2, the write enable is controlled as shown in the figure, and the O is written only on the lower left map so as not to overwrite the area written in the frame 1.
Write the SD signal. This is repeated, and the write enable is controlled so that the OSD signal is written in the entire memory map in frame 4, for example. At the time of reading, control is performed so that the entire memory map is always read. If the capacity of the memory 3 and the number of display pixels of the display unit 8 are matched, OSD display can be performed on the entire screen.

In this embodiment, the control for writing the OSD signal to the entire memory in four frames has been described. However, the number of frames for writing and the writing position are arbitrary.

As described above, by utilizing the write enable function of the memory, the OSD display can be performed on the entire display screen having a resolution higher than the OSDIC.

Finally, in the first to fifth embodiments, a liquid crystal projector is described as an example, but any display device having a built-in digital processing such as a liquid crystal direct-view monitor and a PDP may be used.

[0059]

As described above, according to the present invention, O
The one-phase output of the SD IC is developed into two phases of odd-numbered pixels and even-numbered pixels, and the reduction of the dot clock speed due to the two-phase development is accelerated by the memory and input to the two-phase input of the scan converter, so that OSD characters and The problem that the graphic is enlarged twice in the horizontal direction can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a display device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the display device of the first embodiment.

FIG. 3 is a timing chart illustrating the operation of the first embodiment.

FIG. 4 is a timing chart illustrating the operation of the first embodiment.

FIG. 5 is a timing chart illustrating the operation of the first embodiment.

FIG. 6 is a block diagram illustrating the operation of the single-port memory according to the first embodiment.

FIG. 7 is a timing chart for explaining the operation of the first embodiment.

FIG. 8 is a block diagram illustrating a display device according to a second embodiment of the present invention.

FIG. 9 is a timing chart illustrating the operation of the second embodiment.

FIG. 10 is a block diagram illustrating a display device according to a third embodiment of the present invention.

FIG. 11 is a timing chart illustrating the operation of the third embodiment.

FIG. 12 is a diagram illustrating a fourth embodiment of the present invention.

FIG. 13 is a view for explaining the operation of the fourth embodiment.

FIG. 14 is a view for explaining a fifth embodiment of the present invention.

FIG. 15 is a view for explaining the operation of the fifth embodiment.

FIG. 16 illustrates a conventional example.

FIG. 17 illustrates a conventional example.

[Explanation of symbols]

1. OSDIC, 2. Serial / parallel converter, 3.
Memory, 4 ... memory control circuit, 41 ... write control circuit,
42 read control circuit, 5 AD converter, 6 scan converter, 61 enlargement / reduction processing unit, 62 OSD addition unit, 7 DA converter, 8 display unit, 21 to 24 latch, 25 Timing controller, 26 to 27 switcher, 43 write control circuit, 44 write control circuit, 10 LUT, 32 single port memory, 45
... bidirectional buffer, 46 ... input data buffer, 47 ...
Output data buffer, 48 ... buffer control circuit, 49 ...
Write / read control circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5C006 AA01 AA22 AB01 AF03 AF04 AF25 AF41 AF47 AF71 AF81 AF82 AF85 BB11 BF02 BF03 BF04 BF22 BF27 BF28 BF31 EC11 FA11 FA16 5C080 AA05 AA10 BB05 CC03 DD08 DD09 EE30 JJ04 JJ05 5C082 AA02 BA02 BA12 BA34 BA35 BB51 BC19 CA12 CA56 DA54 DA55 DA71 DA87

Claims (5)

[Claims] In a display apparatus which receives image information of an information processing apparatus, on-screen image information of n (two or more) pixels is converted into a so-called n-phase image signal which is simultaneously transmitted in synchronization with a predetermined clock. A signal processing unit for superimposing a display signal; a display unit for receiving and displaying an output digital signal of the signal processing unit; an on-screen display generator for generating an on-screen display signal; A display device comprising: a serial / parallel converter that develops a signal; and a memory that writes an n-phase signal output of the serial / parallel converter and then reads the output at a signal frequency different from the writing. 2. A display device which receives image information of an information processing apparatus, and on-screen converts the image information of n (2 or more) pixels into a so-called n-phase image signal which is simultaneously transmitted in synchronization with a predetermined clock. A signal processing unit for superimposing a display signal, a display unit for receiving and displaying an output digital signal of the signal processing unit, an on-screen display generator for generating an on-screen display signal, and writing the on-screen display signal A display device comprising: a memory that reads out at a signal frequency different from that of post-writing; and a serial-parallel converter that expands an output signal of the memory into an n-phase signal. 3. In a display device which receives image information of an information processing apparatus, on-screen image information of n (2 or more) pixels is converted into a so-called n-phase image signal which is simultaneously transmitted in synchronization with a predetermined clock. A signal processing unit for superimposing a display signal, a display unit for receiving and displaying an output digital signal of the signal processing unit, an on-screen display generator for generating an on-screen display signal, and writing the on-screen display signal A memory for reading at a signal frequency different from that of the post-writing, wherein when the memory writes the on-screen display signal, the memory controls the n pixels to be written to one address respectively, and the memory When reading from the memory, one address is read at the same time, so that the memory output signal Display device characterized by deploying the No.. 4. In a display device which receives image information of an information processing apparatus, on-screen image information of n (2 or more) pixels is converted into a so-called n-phase image signal which is simultaneously transmitted in synchronization with a predetermined clock. A signal processing unit for superimposing a display signal; a display unit for receiving and displaying an output digital signal of the signal processing unit; an on-screen display generator for generating an on-screen display signal; A serial-to-parallel converter for developing a signal, a memory for writing the n-phase signal output of the serial-to-parallel converter and then reading out the signal at a different signal frequency from the write, and a bit width of the signal output of the memory for a desired bit width And a data converter for converting the data into a data. 5. In a display device which receives image information of an information processing apparatus, on-screen image information of n (2 or more) pixels is converted into a so-called n-phase image signal which is simultaneously transmitted in synchronization with a predetermined clock. A signal processing unit for superimposing a display signal; a display unit for receiving and displaying an output digital signal of the signal processing unit; an on-screen display generator for generating an on-screen display signal; A display device comprising: a serial / parallel converter that develops a signal; and a memory that writes an n-phase signal output of the serial / parallel converter and then reads the signal at a different signal frequency from the writing. When the memory writes the expanded on-screen display signal, different on-screen Write a display signal to the memory, and the display device is controlled so as to vary the area to be written to memory for each frame, when reading from the memory, characterized in that repeatedly reads the desired area.