JP2000252599A - Printed-circuit board - Google Patents
Printed-circuit boardInfo
- Publication number
- JP2000252599A JP2000252599A JP11047646A JP4764699A JP2000252599A JP 2000252599 A JP2000252599 A JP 2000252599A JP 11047646 A JP11047646 A JP 11047646A JP 4764699 A JP4764699 A JP 4764699A JP 2000252599 A JP2000252599 A JP 2000252599A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- conductive
- sealing member
- circuit board
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000007789 sealing Methods 0.000 claims abstract description 37
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000945 filler Substances 0.000 claims 1
- 230000002265 prevention Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 238000004806 packaging method and process Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000006071 cream Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スルーホールを備
えたプリント基板の構造に関し、特にチップ部品のリフ
ロー時における、チップオンスルーホール部のレジスト
膨れ防止構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a printed circuit board having a through hole, and more particularly to a structure for preventing a resist from swelling in a chip-on-through hole portion at the time of reflow of a chip component.
【０００２】[0002]
【従来の技術】従来のスルーホールを備えたプリント基
板としては図７乃至図９に示すものがある。図７はプリ
ント基板の導電回路パターン及びスルーホールと導電膜
部分を示す平面図、図８はプリント基板の要部断面図、
図９はスルーホール部分の封止部材がリフロー時の熱に
より膨れた状態を示す要部断面図である。2. Description of the Related Art FIGS. 7 to 9 show a conventional printed circuit board having through holes. FIG. 7 is a plan view showing a conductive circuit pattern and a through hole and a conductive film portion of the printed circuit board. FIG.
FIG. 9 is a cross-sectional view of an essential part showing a state in which the sealing member in the through hole portion is swollen by heat during reflow.
【０００３】絶縁基板１０１は、フェノール樹脂などか
ら形成され、その表面及び裏面には銅などの導電層をエ
ッチング加工することにより、絶縁基板１０１上に搭載
されるチップ部品１１３などの電子部品を、接続して導
通させる導電回路パターン１０２、１０３が適宜形成さ
れたものとなっている。[0003] The insulating substrate 101 is formed of a phenolic resin or the like, and an electronic component such as a chip component 113 mounted on the insulating substrate 101 is formed by etching a conductive layer such as copper on the front and rear surfaces thereof. Conductive circuit patterns 102 and 103 for connection and conduction are appropriately formed.
【０００４】スルーホール１０４は、前記絶縁基板１０
１の表面及び裏面にエッチング加工などで銅などの導電
層をラウンド状に形成した後、このラウンドの中心部に
表裏両面に達する貫通孔を形成し、この貫通孔内壁に銅
又はニッケルなどの導体壁１０５をめっき加工などで形
成することにより、前記絶縁基板１０１の表面と裏面に
形成された導電回路パターン１０２、１０３間同士を接
続している。また、絶縁基板１０１上の実装密度を向上
させるために、前記スルーホール１０４上にチップ部品
１１３を配設して取り付けが可能な、チップオンスルー
ホール構造とするために、前記スルーホール１０４の貫
通孔内には、例えばエポキシ系の樹脂などからなる封止
部材１０６が充填されており、この封止部材１０６を充
填することで、前記絶縁基板１０１の表面及び裏面に後
述する導電膜が形成できるものとなっている。[0004] The through hole 104 is formed in the insulating substrate 10.
After forming a conductive layer of copper or the like in a round shape by etching or the like on the front and back surfaces of 1, a through hole reaching the front and back surfaces is formed at the center of the round, and a conductor such as copper or nickel is formed on the inner wall of the through hole. By forming the wall 105 by plating or the like, the conductive circuit patterns 102 and 103 formed on the front and back surfaces of the insulating substrate 101 are connected to each other. In addition, in order to improve the mounting density on the insulating substrate 101, a chip component 113 can be disposed on the through hole 104 and attached. The inside of the hole is filled with a sealing member 106 made of, for example, an epoxy-based resin. By filling the sealing member 106, a conductive film to be described later can be formed on the front surface and the back surface of the insulating substrate 101. It has become something.
【０００５】前記絶縁基板１０１に設けられた前記スル
ーホール１０４の表面及び裏面に表出された封止部材１
０６上には、前記導電回路パターン１０２、１０３と連
接されて、銅などの金属めっきを施すことにより導電膜
１０７、１０８が形成されている。また、この導電膜１
０７、１０８及び前記導電回路パターン１０２、１０３
上には、適宜、エポキシ系樹脂などからなる半田レジス
ト層１０９、１１０が形成されたものとなっている。前
記導電膜１０７、１０８上に、前記絶縁基板１０１上に
搭載されるチップ部品１１３の電極１１３ａ、１１３ａ
が配設されて、前記導電回路パターン１０２、１０３
と、クリーム半田１１４により接続がなされるものとな
っている。[0005] The sealing member 1 exposed on the front and back surfaces of the through holes 104 provided in the insulating substrate 101.
The conductive films 107 and 108 are formed on the substrate 06 by being plated with metal such as copper so as to be connected to the conductive circuit patterns 102 and 103. The conductive film 1
07, 108 and the conductive circuit patterns 102, 103
The solder resist layers 109 and 110 made of an epoxy-based resin or the like are appropriately formed thereon. The electrodes 113a, 113a of the chip component 113 mounted on the insulating substrate 101 are formed on the conductive films 107, 108.
Are provided, and the conductive circuit patterns 102 and 103 are provided.
The connection is made by the cream solder 114.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上述し
た従来のプリント基板のチップオンスルーホール部の構
造においては、チップ部品１１３の電極１１３ａと絶縁
基板１０１の表面及び裏面の導電回路パターン１０２、
１０３と接続するために、スルーホール１０４の貫通孔
内に封止部材１０６が充填され、その封止部材１０６上
を覆うように金属めっきを施すことにより導電膜１０
７、１０８が形成されている構成となっていることか
ら、封止部材１０６が樹脂であるため、絶縁基板１０１
上へチップ部品１１３などの電子部品を搭載する場合の
リフロー時の加熱によって、樹脂内の水分がガスとして
膨張することとなる。ここで、封止部材１０６の表面及
び裏面は、金属の導電膜１０７、１０８により蓋をされ
ていることから、発生したガスの逃げ場がなく、導電膜
１０７、１０８及びチップ部品が搭載された導電回路パ
ターン１０２、１０３（チップランド部）に押圧力が加
わり、この押圧力により、導電膜１０７、１０８及び導
電回路パターン１０２、１０３が膨れ上がり膨張部１１
５、１１６を形成するものとなる（図９参照）。これに
より、チップ部品１１３などの電子部品が押し上げられ
ることによりクリーム半田１１４が導電回路パターン１
０２、１０３から切断され、半田付け不良が発生した
り、場合によってはチップ部品１１３にクラック１１７
が生じるという問題があった。However, in the above-described conventional structure of the chip-on-through-hole portion of the printed circuit board, the electrodes 113a of the chip component 113 and the conductive circuit patterns 102 on the front and back surfaces of the insulating substrate 101 are formed.
In order to connect to the conductive film 103, the sealing member 106 is filled in the through hole of the through hole 104 and metal plating is applied to cover the sealing member 106.
7 and 108, the sealing member 106 is made of resin.
By heating at the time of reflow when electronic components such as the chip component 113 are mounted thereon, moisture in the resin expands as a gas. Here, since the front and back surfaces of the sealing member 106 are covered with metal conductive films 107 and 108, there is no escape for the generated gas, and the conductive film on which the conductive films 107 and 108 and the chip component are mounted is not provided. A pressing force is applied to the circuit patterns 102 and 103 (chip lands), and the pressing force causes the conductive films 107 and 108 and the conductive circuit patterns 102 and 103 to swell and expand.
5, 116 are formed (see FIG. 9). As a result, when the electronic components such as the chip component 113 are pushed up, the cream solder 114 is formed on the conductive circuit pattern 1.
02 and 103, soldering failure may occur, and in some cases, cracks 117
There was a problem that occurs.
【０００７】したがって、本発明では上述した問題点を
解決し、プリント基板上の実装密度を向上させるため
の、スルーホール上にチップ部品を配設して取り付けが
可能な、チップオンスルーホール構造であって、かつ、
リフロー時における熱の影響を受けない、チップオンス
ルーホール部のレジスト膨れ防止構造を提供することを
目的とする。Therefore, the present invention has a chip-on-through-hole structure which can solve the above-mentioned problems and improve the mounting density on a printed circuit board by disposing and mounting chip components on the through-hole. There and
An object of the present invention is to provide a resist swelling prevention structure in a chip-on-through-hole portion which is not affected by heat during reflow.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に本発明では第１の手段として、絶縁基板の表面及び裏
面に形成された複数の導電回路パターンと、前記絶縁基
板に設けられた貫通孔内に導体壁が形成されたスルーホ
ールと、このスルーホール内に充填された封止部材と、
この封止部材上に形成された導電膜と、この導電膜上に
被覆されたレジスト層と、前記導電回路パターン及び前
記スルーホール上に配設されるチップ部品とを備え、前
記絶縁基板の表面及び裏面に設けられた導電膜の少なく
とも一方の面の、前記封止部材上に位置する箇所には、
孔が形成されていることを特徴とする。According to the present invention, as a first means for solving the above-mentioned problems, a plurality of conductive circuit patterns formed on a front surface and a back surface of an insulating substrate and a through-hole provided on the insulating substrate are provided. A through-hole in which a conductor wall is formed in the hole, and a sealing member filled in the through-hole,
A conductive layer formed on the sealing member, a resist layer coated on the conductive layer, and a chip component disposed on the conductive circuit pattern and the through hole; And at least one surface of the conductive film provided on the back surface, at a location located on the sealing member,
It is characterized in that a hole is formed.
【０００９】また、第２の手段として、前記導電膜に形
成された孔は、前記絶縁基板の表面及び裏面の両方に形
成されていることを特徴とする。As a second means, the holes formed in the conductive film are formed on both the front surface and the back surface of the insulating substrate.
【００１０】また、第３の手段として、前記絶縁基板に
設けられた前記レジスト層の一方の面には、前記導電膜
に形成された前記孔に対向して、連通孔が形成されてい
ることを特徴とする。[0010] As a third means, a communication hole is formed on one surface of the resist layer provided on the insulating substrate so as to face the hole formed in the conductive film. It is characterized by.
【００１１】また、第４の手段として、前記レジスト層
に形成された連通孔は、前記絶縁基板の表面及び裏面の
両方に形成されていることを特徴とする。As a fourth means, the communication hole formed in the resist layer is formed on both the front surface and the back surface of the insulating substrate.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施例を図１乃至
図６に示す。図１乃至図３は本発明の第１の実施例であ
るチップオンスルーホール部のプリント基板の構造を示
し、図１はプリント基板の導電回路パターン及びスルー
ホールと導電膜部分を示す平面図、図２はプリント基板
の要部断面図、図３は図２の変形例を示すプリント基板
の要部断面図である。1 to 6 show an embodiment of the present invention. 1 to 3 show a structure of a printed circuit board in a chip-on-through-hole portion according to a first embodiment of the present invention. FIG. 1 is a plan view showing a conductive circuit pattern and a through hole and a conductive film portion of the printed circuit board. FIG. 2 is a cross-sectional view of a main part of the printed board, and FIG. 3 is a cross-sectional view of a main part of the printed board showing a modification of FIG.
【００１３】絶縁基板１は、両面に銅などの導電層が積
層された、フェノール樹脂などからなる積層板により形
成されている。この絶縁基板１の表面及び裏面には、銅
などの導電層の必要な部分にフィルムなどでマスキング
が施され、不要な部分がエッチング加工されることによ
り、絶縁基板１上に搭載される電子部品を、接続して導
通させる導電回路パターン２、３が適宜形成されたもの
となっている。The insulating substrate 1 is formed of a laminated plate made of a phenol resin or the like in which conductive layers such as copper are laminated on both sides. On the front and back surfaces of the insulating substrate 1, a necessary portion of a conductive layer such as copper is masked with a film or the like, and the unnecessary portion is etched to form an electronic component mounted on the insulating substrate 1. The conductive circuit patterns 2 and 3 for connecting and conducting the above are appropriately formed.
【００１４】スルーホール４は、前記絶縁基板１の表面
及び裏面にエッチング加工などで導電層がラウンド状に
形成された後、このラウンドの中心部に表裏両面に達す
る貫通孔が形成され、この貫通孔内壁に銅又はニッケル
などの導体壁５がめっき加工などの方法で形成されたも
のとなっている。前記貫通孔内壁に導体壁５が形成され
ることにより、前記絶縁基板１の表面と裏面に形成され
た導電回路パターン２、３間同士が接続されている。ま
た、前記絶縁基板１上へ搭載される、電子部品の実装密
度を向上させるため、即ち、前記スルーホール４上に電
子部品を配設して取り付けが可能な、チップオンスルー
ホール構造とするために、前記スルーホール４の貫通孔
内には、例えばエポキシ系の樹脂などからなる封止部材
６が充填されている構成となっている。この封止部材６
を前記貫通孔内に充填することで、前記絶縁基板１の表
面及び裏面に後述する導電膜が形成できるものとなって
いる。In the through hole 4, a conductive layer is formed in a round shape on the front and back surfaces of the insulating substrate 1 by etching or the like, and a through hole reaching the front and back surfaces is formed at the center of the round. A conductor wall 5 such as copper or nickel is formed on the inner wall of the hole by plating or the like. By forming the conductor wall 5 on the inner wall of the through hole, the conductive circuit patterns 2 and 3 formed on the front and back surfaces of the insulating substrate 1 are connected to each other. Further, in order to improve the mounting density of electronic components mounted on the insulating substrate 1, that is, to provide a chip-on-through-hole structure in which electronic components can be arranged and mounted on the through-holes 4. Further, the through hole 4 is filled with a sealing member 6 made of, for example, an epoxy resin. This sealing member 6
Is filled in the through holes, so that a conductive film described later can be formed on the front surface and the back surface of the insulating substrate 1.
【００１５】前記絶縁基板１に設けられた前記スルーホ
ール４の表面及び裏面に表出された封止部材６上には、
前記導電回路パターン２、３、と連接されて、銅などの
金属めっきにより、前記スルーホール４を覆うように導
電膜７、８が形成されている。また、この導電膜７、８
及び前記導電回路パターン２、３上には、適宜、エポキ
シ系樹脂などからなる半田レジスト層９ａ、１０ａが形
成されたものとなっている。前記導電膜７、８上に前記
絶縁基板１上に搭載される電子部品が配設されて、前記
導電回路パターン２、３と接続がなされるものとなって
いる。また、前記導電膜７、８の、少なくともその一方
側（例えば表面側の導電膜７）には、前記封止部材６が
外部雰囲気と連通される孔１１ａが設けられている。ま
た、図３に示すように、前記孔１１ａは前記スルーホー
ル４の一方側だけではなく、表面側の孔１１ａ及び裏面
側の孔１２ａのように両方に設けても良く、この場合に
は、外部雰囲気との連通が大きくとれることから、リフ
ロー時に前記封止部材６内に発生するガスを外部雰囲気
中へ逃がす効果が向上されるものとなる。On the sealing member 6 exposed on the front and back surfaces of the through holes 4 provided in the insulating substrate 1,
Conductive films 7 and 8 are formed so as to cover the through holes 4 by metal plating such as copper so as to be connected to the conductive circuit patterns 2 and 3. The conductive films 7 and 8
On the conductive circuit patterns 2 and 3, solder resist layers 9a and 10a made of an epoxy resin or the like are appropriately formed. Electronic components mounted on the insulating substrate 1 are disposed on the conductive films 7 and 8, and are connected to the conductive circuit patterns 2 and 3. At least one side of the conductive films 7 and 8 (for example, the conductive film 7 on the surface side) is provided with a hole 11a through which the sealing member 6 is communicated with an external atmosphere. Further, as shown in FIG. 3, the hole 11a may be provided not only on one side of the through hole 4 but also on both the front side hole 11a and the rear side hole 12a. In this case, Since the communication with the external atmosphere can be made large, the effect of releasing the gas generated in the sealing member 6 during the reflow to the external atmosphere is improved.
【００１６】チップ部品１３は、内部に抵抗体やキャパ
シタンスなどが封入され、その両側に外部回路と接続さ
れる電極１３ａ、１３ａ部分を備える既存の電子部品
で、前記導電回路パターン２、３及び導電膜７、８上に
搭載され、リフロー時の加熱により、クリーム半田１４
が溶けて、凝固時に、前記電極１３ａ、１３ａ部分が前
記導電回路パターン２、３と半田接続されるものとなっ
ている。The chip component 13 is an existing electronic component having electrodes 13a, 13a on both sides of which a resistor, a capacitance, and the like are sealed, and which has electrodes 13a, 13a connected to an external circuit. The cream solder 14 is mounted on the films 7 and 8 and heated by reflow.
Is melted and the electrodes 13a, 13a are solder-connected to the conductive circuit patterns 2, 3 during solidification.
【００１７】前記チップ部品１３が前記絶縁基板１に搭
載され、半田接続される場合には、リフロー時の加熱に
よって前記スルーホール４の貫通孔内に充填された封止
部材６が、樹脂のために、その内部の水分が熱によって
膨張され、ガスが発生する。この場合、本発明において
は、前記封止部材６の表面側及び／または裏面側を覆っ
ている前記導電膜７、８には、外部雰囲気と連通される
前記孔１１ａ、１２ａが設けられていることから、この
孔１１ａ、１２ａによって前記ガスは外部雰囲気中に放
出されることになり、前記導電膜７、８及び前記チップ
部品１３が搭載された前記導電回路パターン２、３（チ
ップランド部）に前記ガスによる押圧力が加わる恐れが
なく、前記チップ部品１３などの電子部品が、前記封止
部材６により押し上げられることによる半田付け不良が
発生することはなく、チップ部品１３にクラックが生じ
るということもない。When the chip component 13 is mounted on the insulating substrate 1 and connected by soldering, the sealing member 6 filled in the through hole of the through hole 4 by heating during reflow is made of resin. In the meantime, the moisture inside the gas expands due to the heat, and gas is generated. In this case, in the present invention, the conductive films 7 and 8 covering the front surface side and / or the back surface side of the sealing member 6 are provided with the holes 11a and 12a communicating with an external atmosphere. Therefore, the gas is released into the external atmosphere by the holes 11a and 12a, and the conductive circuit patterns 2, 3 (chip land portions) on which the conductive films 7, 8 and the chip component 13 are mounted are provided. There is no fear that the pressing force due to the gas will be applied to the chip component 13, no soldering failure will occur due to the electronic component such as the chip component 13 being pushed up by the sealing member 6, and cracks will occur in the chip component 13. Not even.
【００１８】図４乃至図６は本発明の第２の実施例であ
るチップオンスルーホール部のプリント基板の構造を示
し、図４はプリント基板の導電回路パターン及びスルー
ホールと導電膜部分を示す平面図、図５はプリント基板
の要部断面図、図６は図５の変形例を示すプリント基板
の要部断面図である。なお、図１乃至図３で説明した同
一部品については、同一符号を付してその説明を省略す
る。FIGS. 4 to 6 show a structure of a printed circuit board in a chip-on-through-hole portion according to a second embodiment of the present invention, and FIG. 4 shows a conductive circuit pattern of the printed circuit board and a through-hole and a conductive film portion. FIG. 5 is a plan view, FIG. 5 is a cross-sectional view of a main part of the printed circuit board, and FIG. 6 is a cross-sectional view of a main part of the printed circuit board showing a modification of FIG. 1 to 3 are denoted by the same reference numerals, and description thereof will be omitted.
【００１９】この場合、第１の実施例との相違点は、ス
ルーホール４の貫通孔内に充填された封止部材６の表面
側及び／または裏面側を覆っている導電膜７、８上に設
けられた孔１１ａ、１２ａの構成が若干異なっている点
である。即ち、本発明の第２の実施例では、前記スルー
ホール４の貫通孔内に充填された封止部材６を覆ってい
る導電膜７、８と、この導電膜７、８上を覆っている半
田レジスト層９ｂ、１０ｂの両方に貫通する、孔１１
ａ、１２ａ及び連通孔１１ｂ、１２ｂが設けられている
ものとなっている。In this case, the difference from the first embodiment is that the conductive members 7, 8 covering the front side and / or the back side of the sealing member 6 filled in the through holes 4 are different. Are slightly different from each other in the configuration of the holes 11a and 12a. That is, in the second embodiment of the present invention, the conductive films 7 and 8 covering the sealing member 6 filled in the through holes 4 and the conductive films 7 and 8 are covered. Hole 11 penetrating both solder resist layers 9b, 10b
a, 12a and communication holes 11b, 12b are provided.
【００２０】この場合、本発明の第１の実施例である、
前記導電膜７、８のみに孔１１ａ，１２ａを設けた構成
に比較して、前記封止部材６と外部雰囲気との連通がさ
らに改善されるものとなり、前記連通孔１１ｂ、１２ｂ
により、前記封止部材６内で発生したガスは、外部雰囲
気中に完全に放出されることとなる。したがって、前記
導電膜７、８及び前記チップ部品１３が搭載された前記
導電回路パターン２、３（チップランド部）に前記ガス
による押圧力が加わる恐れが全くなくなることから、前
記チップ部品１３などの電子部品の半田付け不良が発生
することや、チップ部品１３にクラックが生じるという
ことが回避できる。In this case, the first embodiment of the present invention,
The communication between the sealing member 6 and the external atmosphere is further improved as compared with a configuration in which the holes 11a and 12a are provided only in the conductive films 7 and 8, and the communication holes 11b and 12b are improved.
Thereby, the gas generated in the sealing member 6 is completely discharged into the external atmosphere. Therefore, there is no danger that the pressing force due to the gas is applied to the conductive circuit patterns 2 and 3 (chip lands) on which the conductive films 7 and 8 and the chip component 13 are mounted. It is possible to avoid the occurrence of soldering failure of the electronic component and the occurrence of cracks in the chip component 13.
【００２１】[0021]
【発明の効果】以上説明したように、本発明のプリント
基板は、スルーホールの貫通孔内に充填された封止部材
上に形成された導電膜の、少なくとも一方の面の、前記
封止部材上に位置する箇所には、孔が形成されているた
め、この孔によって前記封止部材から発生するガスは外
部雰囲気中に放出されることになり、前記導電膜及び導
電回路パターン（チップランド部）に前記ガスによる押
圧力が加わる恐れがなくなり、チップ部品などの電子部
品が、前記封止部材の膨張したガス圧により押し上げら
れることもなく、半田付け不良が発生したり、また、チ
ップ部品にクラックが生じるという問題もなくなる。As described above, the printed circuit board of the present invention is characterized in that at least one surface of the conductive film formed on the sealing member filled in the through-hole of the through-hole has the sealing member. Since a hole is formed in the upper portion, a gas generated from the sealing member is released into an external atmosphere by this hole, and the conductive film and the conductive circuit pattern (chip land portion) are released. ), The pressing force due to the gas is not applied, and the electronic component such as the chip component is not pushed up by the expanded gas pressure of the sealing member. There is no problem of cracks.
【００２２】また、導電膜に形成された孔は、絶縁基板
の表面及び裏面の両方に形成されているため、外部雰囲
気との連通が大きくとれることから、リフロー時に封止
部材内に発生するガスを外部雰囲気中へ逃がす効果が向
上される。Further, since the holes formed in the conductive film are formed on both the front surface and the back surface of the insulating substrate, the communication with the external atmosphere can be made large. To the outside atmosphere is improved.
【００２３】また、絶縁基板に設けられたレジスト層の
一方の面には、前記導電膜に形成された前記孔に対向し
て、連通孔が形成されているため、封止部材と外部雰囲
気との連通がさらに改善されるものとなり、この連通孔
によって前記ガスは外部雰囲気中に完全に放出されるこ
とになり、半田付け時の信頼性が更に向上される。Further, since a communication hole is formed on one surface of the resist layer provided on the insulating substrate so as to face the hole formed in the conductive film, the sealing member and the external atmosphere are not provided. The communication is further improved, and the gas is completely discharged into the external atmosphere by the communication holes, so that the reliability at the time of soldering is further improved.
【００２４】また、レジスト層に形成された連通孔は、
絶縁基板の表面及び裏面の両方に形成されているため、
外部雰囲気との連通が更に大きくとれることから、リフ
ロー時に封止部材内に発生するガスを外部雰囲気中へ逃
がす効果が更に向上される。The communication hole formed in the resist layer is
Because it is formed on both the front and back surfaces of the insulating substrate,
Since the communication with the external atmosphere can be further increased, the effect of releasing the gas generated in the sealing member at the time of reflow to the external atmosphere is further improved.
【図１】本発明の第１の実施例であるプリント基板の導
電回路パターン及びスルーホールと導電膜部分を示す平
面図である。FIG. 1 is a plan view showing a conductive circuit pattern, a through hole, and a conductive film portion of a printed circuit board according to a first embodiment of the present invention.
【図２】本発明の第１の実施例であるプリント基板の要
部断面図である。FIG. 2 is a sectional view of a main part of a printed circuit board according to a first embodiment of the present invention.
【図３】本発明の図２の変形例を示すプリント基板の要
部断面図である。FIG. 3 is a cross-sectional view of a main part of a printed circuit board showing a modification of FIG. 2 of the present invention.
【図４】本発明の第２の実施例であるプリント基板の導
電回路パターン及びスルーホールと導電膜部分を示す平
面図である。FIG. 4 is a plan view showing a conductive circuit pattern, a through hole, and a conductive film portion of a printed circuit board according to a second embodiment of the present invention.
【図５】本発明の第２の実施例であるプリント基板の要
部断面図である。FIG. 5 is a sectional view of a main part of a printed circuit board according to a second embodiment of the present invention.
【図６】本発明の図５の変形例を示すプリント基板の要
部断面図である。FIG. 6 is a sectional view of a principal part of a printed circuit board showing a modification of FIG. 5 of the present invention.
【図７】従来のプリント基板の導電回路パターン及びス
ルーホールと導電膜部分を示す平面図である。FIG. 7 is a plan view showing a conductive circuit pattern, a through hole, and a conductive film portion of a conventional printed circuit board.
【図８】従来のプリント基板の要部断面図である。FIG. 8 is a sectional view of a main part of a conventional printed circuit board.
【図９】従来のスルーホール部分の封止部材がリフロー
時の熱により膨れた状態を示す要部断面図である。FIG. 9 is a cross-sectional view of a main part showing a state where a conventional sealing member in a through-hole portion is swollen by heat during reflow.
１ 絶縁基板 ２，３ 導電回路パターン ４ スルーホール ５ 導体壁 ６ 封止部材 ７，８ 導電膜 ９ａ，９ｂ，１０ａ，１０ｂ レジスト層 １１ａ，１２ａ 孔 １１ｂ，１２ｂ 連通孔 １３ チップ部品 １４ クリーム半田 REFERENCE SIGNS LIST 1 insulating substrate 2, 3 conductive circuit pattern 4 through hole 5 conductive wall 6 sealing member 7, 8 conductive film 9 a, 9 b, 10 a, 10 b resist layer 11 a, 12 a hole 11 b, 12 b communication hole 13 chip component 14 cream solder
Claims (4)
数の導電回路パターンと、前記絶縁基板に設けられた貫
通孔内に導体壁が形成されたスルーホールと、このスル
ーホール内に充填された封止部材と、この封止部材上に
形成された導電膜と、この導電膜上に被覆されたレジス
ト層と、前記導電回路パターン及び前記スルーホール上
に配設されるチップ部品とを備え、前記絶縁基板の表面
及び裏面に設けられた導電膜の少なくとも一方の面の、
前記封止部材上に位置する箇所には、孔が形成されてい
ることを特徴とするプリント基板。1. A plurality of conductive circuit patterns formed on a front surface and a back surface of an insulating substrate, a through hole in which a conductor wall is formed in a through hole provided in the insulating substrate, and a filler filled in the through hole. A sealing member, a conductive film formed on the sealing member, a resist layer coated on the conductive film, and a chip component disposed on the conductive circuit pattern and the through hole. , At least one surface of the conductive film provided on the front surface and the back surface of the insulating substrate,
A printed circuit board, wherein a hole is formed at a position located on the sealing member.
基板の表面及び裏面の両方に形成されていることを特徴
とする請求項１記載のプリント基板。2. The printed circuit board according to claim 1, wherein the holes formed in the conductive film are formed on both the front surface and the back surface of the insulating substrate.
層の一方の面には、前記導電膜に形成された前記孔に対
向して、連通孔が形成されていることを特徴とする請求
項１、または２記載のプリント基板。3. A communication hole is formed on one surface of the resist layer provided on the insulating substrate so as to face the hole formed on the conductive film. 3. The printed circuit board according to 1 or 2.
前記絶縁基板の表面及び裏面の両方に形成されているこ
とを特徴とする請求項３記載のプリント基板。4. The communication hole formed in the resist layer,
4. The printed circuit board according to claim 3, wherein the printed circuit board is formed on both the front surface and the back surface of the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11047646A JP2000252599A (en) | 1999-02-25 | 1999-02-25 | Printed-circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11047646A JP2000252599A (en) | 1999-02-25 | 1999-02-25 | Printed-circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000252599A true JP2000252599A (en) | 2000-09-14 |
Family
ID=12781024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11047646A Withdrawn JP2000252599A (en) | 1999-02-25 | 1999-02-25 | Printed-circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000252599A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009010225A (en) * | 2007-06-28 | 2009-01-15 | Kyocera Corp | Circuit board and electronic equipment |
| US8198726B2 (en) | 2008-12-26 | 2012-06-12 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate and method of manufacturing the same |
| US8544169B2 (en) | 2009-09-09 | 2013-10-01 | Dai Nippon Printing Co., Ltd. | Method of manufacturing a through-hole electrode substrate |
| US9769927B2 (en) | 2014-09-09 | 2017-09-19 | Dai Nippon Printing Co., Ltd. | Structural body and method for manufacturing same |
-
1999
- 1999-02-25 JP JP11047646A patent/JP2000252599A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009010225A (en) * | 2007-06-28 | 2009-01-15 | Kyocera Corp | Circuit board and electronic equipment |
| US8198726B2 (en) | 2008-12-26 | 2012-06-12 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate and method of manufacturing the same |
| US8623751B2 (en) | 2008-12-26 | 2014-01-07 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate and method of manufacturing the same |
| US8544169B2 (en) | 2009-09-09 | 2013-10-01 | Dai Nippon Printing Co., Ltd. | Method of manufacturing a through-hole electrode substrate |
| US9443788B2 (en) | 2009-09-09 | 2016-09-13 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate |
| US10014244B2 (en) | 2009-09-09 | 2018-07-03 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate |
| US10600728B2 (en) | 2009-09-09 | 2020-03-24 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate |
| US9769927B2 (en) | 2014-09-09 | 2017-09-19 | Dai Nippon Printing Co., Ltd. | Structural body and method for manufacturing same |
| US9924596B2 (en) | 2014-09-09 | 2018-03-20 | Dai Nippon Printing Co., Ltd. | Structural body and method for manufacturing same |
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