JP2000277536A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure, wherein a field-effect transistor of a constitution, wherein a leakage of a current from a Schottky gate electrode to semiconductor layers is suppressed, can be formed with good reproducibility. SOLUTION: A buffer layer 102 for raising the quality of the crystal of its upper layer and an N-type first semiconductor layer 103 with carriers flowing in its interior are formed in order on a high-resistance substrate 101. A second semiconductor layer 104, which has an electron affinity weaker than that of the layer 103 and suppresses a current to flow in the layer 104 from a gate electrode on the layer 104 by a thermal excitation, is formed on the layer 103. Moreover, a third semiconductor layer 105, which has an electron affinity more weaker than that of the layer 104, is inserted in the vicinity of the gate electrode on the layer 104. A source electrode 106, a gate electrode 107 and a drain electrode 108 are formed on such a crystal structure. A leakage current from a field-effect transistor is prevented by barrier layers provided in the semiconductor layers, and the barrier layers are provided in the semiconductor layers to prevent the wear of the transistor due to etching and to modify the reproducibility of the process for forming the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a field effect transistor, and more particularly to a field effect transistor structure having a small gate leak current.

[0002]

2. Description of the Related Art Conventionally, in a field effect transistor of a type in which a gate electrode is brought into direct contact with a semiconductor to control a current flowing through the semiconductor, if the height of the Schottky barrier between the gate electrode and the semiconductor is low, heat is generated. Excited electrons flow from the electrode into the semiconductor, causing a gate leakage current,
There is a problem that device characteristics deteriorate. As a method for solving this problem, there is a method of introducing a semiconductor that forms a high barrier at the Schottky junction interface.

As a specific example, the case of an InGaP semiconductor will be described first. InGaP semiconductor is AlGa
Unlike an As semiconductor, it does not contain highly reactive Al, is chemically stable, and has no deep level such as a DX center. Therefore, it is expected as a highly reliable transistor semiconductor material. However, metal / InGa
The Schottky barrier height (0.65 eV) of P semiconductor is
It is lower than the Schottky barrier height (0.80 eV) of the metal / AlGaAs semiconductor. Therefore, there is a problem that a gate leak current is likely to flow and a withstand voltage is low, and applications have been limited to devices operating at a low voltage. As means for solving this, for example, as described in JP-A-62-252975, In _0.5 (Ga _1-x Al _x ) _0.5 As
A method of increasing the Schottky barrier height using a layer or In _x Ga _1-x P (x <0.5) has been proposed.

Next, as another specific example, a case of an InP semiconductor will be described. An InP semiconductor has an electron saturation speed equal to that of a GaAs semiconductor and a dielectric breakdown strength of G
Since it is twice as high as an aAs semiconductor, it is expected as a semiconductor material capable of high-voltage operation. However, the barrier height between InP and the Schottky gate metal is around 0.5 eV, and the breakdown voltage is low. As means for solving this, as described in the above-mentioned Japanese Patent Application Laid-Open No. 62-252975, an In _0.5 (Ga _1-x Al _x ) _0.5 As layer or an I _{0.5
n x Ga 1-x P (} x <0.5) a method of increasing the Schottky barrier height with have been proposed.

Next, the case of a GaN semiconductor will be described as another specific example. The energy band gap Eg of the GaN semiconductor is 3.4 eV, which is more than twice as high as 1.42 eV of GaAs, and the dielectric breakdown strength of the GaN semiconductor is five times higher than that of the GaAs semiconductor.
It is expected as a semiconductor material capable of high-temperature operation and high-voltage operation. However, the barrier height between the GaN semiconductor and the Schottky gate metal is 1.0 eV, and the conventional A
Although the barrier height of the lGaAs / GaAs material is the same as 1.0 eV, at a high temperature that makes use of the above-described feature of a large energy band gap, an increase in gate leakage current when the field effect transistor operates is problematic. Also,
As a method of suppressing gate leakage current during high-temperature operation, AlGaN / Ga in which a gate metal and an AlGaN semiconductor are in contact with each other is used.
A structure using an N-terror junction has been proposed.

[0006]

The first problem with the InGaP semiconductor described in the above-mentioned conventional example is that the current flowing through the manufactured device fluctuates during operation. The reason is that the deep level generated in the semiconductor by increasing the Al composition or lowering the In composition changes the potential in the device by trapping or releasing carriers. It is because.

[0007] The second problem is disclosed in Japanese Patent Application Laid-Open No. 62-252.
No. 975, a part of the surface In _x Ga _{1 -x} P (x <0.5) layer is etched during the process, and the film thickness decreases. The barrier height is reduced. The reason is that In _x Ga _1-x
Since the P (x <0.5) layer is a strained layer having a different lattice constant from that of the GaAs substrate, if the composition of x is reduced to increase the barrier height, the film thickness that can be formed without generating crystal defects becomes thin. In _x Ga _1-x P during the process (x <0.5)
This is because the layer is etched and the decrease in film thickness cannot be ignored, and the effect as a barrier layer is reduced.

Next, the first problem in the InP semiconductor described in the second specific example is that the (Al
Ga) Part of the InP layer is etched during the process to reduce the film thickness and decrease the effective barrier height.
The reason is that if the (AlGa) composition is increased to increase the barrier height, the lattice constant difference with respect to the InP substrate becomes large, the film thickness that can be grown without crystal defects becomes thin, and the (AlGa) This is because the InP layer is etched and the film thickness cannot be reduced and cannot be ignored, and does not work as a sufficient barrier.

Next, the first problem with the GaN semiconductor described in the third example is that Al _x Ga ₁ -xN (x
> 0.5) Part of the layer is etched during the process, reducing the film thickness and lowering the barrier height. The reason is that the lattice constant difference between AlN and GaN is as large as 2.4%,
When trying to increase the Al composition to increase the barrier height,
The thickness of the AlGaN layer that can be formed without crystal defects becomes thin. Then, the thinned AlGaN layer is etched during the process, and the thickness is further reduced, so that the AlGaN layer is insufficient as a barrier for reducing the gate leak current.

Accordingly, an object of the present invention is to provide a field effect transistor of a type in which a gate electrode is brought into direct contact with a semiconductor to control a current flowing in the semiconductor. It is an object of the present invention to provide a structure which can manufacture a field effect transistor with a high reproducibility, which solves the problem of deterioration of the transistor.

[0011]

In order to achieve the above object, the present invention provides a first semiconductor layer through which carriers flow, an electron affinity smaller than that of the first semiconductor layer, and the first semiconductor layer.
A field effect transistor having a heterojunction with the first semiconductor layer and a second semiconductor layer forming a Schottky junction with the gate electrode, wherein the second semiconductor layer has an electron affinity higher than that of the second semiconductor layer. A third semiconductor layer having a small thickness is inserted, and the insertion position is shifted from a hetero interface formed by the second semiconductor layer and the first semiconductor layer to a Schottky junction interface formed by the second semiconductor layer and the gate electrode. In the vicinity.

In this field effect transistor, a third semiconductor layer having a smaller electron affinity than the second semiconductor layer is inserted in the second semiconductor layer near the gate electrode. Therefore, electrons flowing from the gate electrode due to thermal excitation have a small electron affinity of the third semiconductor layer, so that the third semiconductor layer becomes a barrier layer and is greatly reduced. The surface is the second
And the third semiconductor layer is not thinned by etching during the process. Therefore, the gate leak current can be reduced with good reproducibility.

According to the present invention, there is provided a field effect transistor in which the first semiconductor layer is n-type or p-type, and the first semiconductor layer and the gate electrode form a Schottky junction.
A third semiconductor layer having an electron affinity smaller than that of the first semiconductor layer is inserted into the first semiconductor layer, and the inserted third semiconductor layer is inserted.
The interface between the semiconductor layer and the first semiconductor layer on the gate electrode side is し て of the depth of the end of the depletion layer formed at the Schottky junction when the potentials of the source electrode and the gate electrode are equalized. It is characterized by being located at the following depth and shallower than the depletion layer thickness on the substrate side.

In this field effect transistor, a third semiconductor layer having a smaller electron affinity than the first semiconductor layer is inserted near the gate electrode in a depletion layer formed at the Schottky junction between the gate electrode and the first semiconductor layer. Have been. Accordingly, electrons flowing from the gate electrode by thermal excitation have a small electron affinity of the third semiconductor layer, so that the third semiconductor layer becomes a barrier layer and is greatly reduced. The surface is the first
And the third semiconductor layer is not thinned by etching during the process. Therefore, the gate leak current can be reduced with good reproducibility.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the field effect transistor according to the present invention will be described. (First Embodiment) FIG. 1 is a sectional view showing a structural example of a field-effect transistor according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a structure under a gate electrode of the field-effect transistor shown in FIG. FIG. 4 is an explanatory diagram showing an energy band of FIG. The field-effect transistor shown in FIG.
A buffer layer 102 for improving the quality of the upper crystal,
First semiconductor layer 10 showing n-type conductivity through which carriers flow
3 and a second semiconductor layer 104 having a smaller electron affinity than the first semiconductor layer for suppressing a current flowing from the gate electrode due to thermal excitation. The third semiconductor layer 105 having a smaller electron affinity than the second semiconductor layer has a crystal structure in which the third semiconductor layer 105 is inserted near the gate electrode of the second semiconductor layer.
Then, on such a crystal structure, the source electrode 106,
The gate electrode 107 and the drain electrode 108 are formed.

In FIG. 2, the vertical axis indicates the energy level, and the horizontal axis schematically indicates the interval between the layers. Carriers flow through the first semiconductor layer 103. Then, the electrons 109 excited by heat try to flow over the Schottky barrier from the gate electrode 107 and flow into the first semiconductor layer 103, but have a smaller electron affinity than the second semiconductor layer 104. Third semiconductor layer 105 having a high barrier height
, The flowing current is greatly suppressed. In addition, since the second semiconductor layer 104 is present on the surface, the third semiconductor layer 105 is not etched during the process, and the barrier layer is not thinned. Therefore, a field effect transistor having a small gate leak current with good reproducibility can be obtained.

Further, since the third semiconductor layer 105 may be thinner than the second semiconductor layer 104, no crystal defects occur even if the semiconductor material of the substrate has a different lattice constant. Therefore, a semiconductor material having a smaller electron affinity can be selected. Conventionally, the electron 109 excited by heat in the second semiconductor layer 104 is prevented from flowing over the Schottky barrier from the gate electrode and flowing into the first semiconductor layer 103. Semiconductor layer 1
The current can be further reduced by inserting 05. Hereinafter, specific examples 1 to 5 in the present embodiment will be described.

Example 1 FIG. 3 is a cross-sectional view showing a specific example of the structure of a field effect transistor according to the first embodiment of the present invention. In FIG. 3, first, the high-resistance substrate 10
As 1, a GaAs substrate is used. An undoped GaAs buffer layer having a thickness of 1
In the range of μm to 100 nm, for example, 400 nm is laminated. Then, as the first semiconductor layer 103, a GaAs layer doped with an n-type impurity, for example, 1 × 10
A layer having a thickness of 300 nm to which ¹⁷ cm ^{-3 is} added is formed. Further, as the second semiconductor layer 104, for example, undoped I
An nGaP layer 40 nm is formed.

Further, as the third semiconductor layer 105, for example, undoped In _x Ga _{1 -x} P (x = 0.3, 10n
m) The layer was inserted into the second semiconductor layer 104 at a position 10 nm deeper than the gate electrode. The source electrode 106 and the drain electrode 108 are formed as a contact layer 110 on the second semiconductor layer 104 as GaAs doped with n-type impurities at a high concentration.
The s layer 110 is formed, for example, with a Si concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of 50 nm, and then, as an ohmic electrode thereon, for example, AuGe / Ni is deposited and then alloyed by heat treatment. The gate electrode 107 is formed of the second semiconductor layer 104
After removing the upper contact layer 110 by etching, the second
The undoped InGaP layer, which is the semiconductor layer 104, is exposed, and is manufactured by a registry lift-off method.

In the above configuration, the gate electrode 1
InGaP which is the second semiconductor layer 104 in contact with the
In _x Ga _{1 -x} P as a third semiconductor layer 105 below
(X = 0.3, 10 nm) layer, the conventional I
_{n x Ga 1-x P (} x = 0.3,10nm) layer compared to the structure which is exposed on the surface, the surface in the process is etched _{In x Ga 1-x P (} x = 0.3, 10 nm) layer is not thinned. Therefore, the gate leak current can be reduced with good reproducibility.

In this embodiment, the third semiconductor layer 1
A 10 nm thick (x = 0.3) was used as 05,
For example, it may be within the range satisfying the relationship between the In composition and the critical film thickness of InGaP described in the July 1990 Journal of Applied Physics, Vol. 68, No. 1, pages 107-111, and FIG. Also, desirably, the In composition is lower while the barrier thickness is 4 nm or more. In this embodiment, the third semiconductor layer 105 is inserted at a depth of 10 nm from the gate electrode 107 in the second semiconductor layer 104. However, in order to reduce the gate leakage current, the third semiconductor layer 105 is inserted at a position where the third semiconductor layer 105 is inserted. Is preferably closer to the gate electrode 107. Considering that the surface is etched by about 2 nm during the process, it is most effective to insert at a depth of 2 nm or more and less than 10 nm. Further, here, as the third semiconductor layer 105, In
_x Ga _1-x P has been described, but Al _x Ga _1-x As (x
= 0.5), I within a range where the critical film thickness satisfies 4 nm or more.
_{n x (Ga 1-y Al} y) 1-x P (x <0.51, y> 0) even with the same effect. Also, the second semiconductor layer 104
Is an AlGaAs layer, the same effect can be obtained.

(Embodiment 2) In Embodiment 2, after forming the first semiconductor layer 103 in the same manner as in Embodiment 1 described above, as the second semiconductor layer 104, for example, an InGaP layer 40n
m. And as the third semiconductor layer 105,
For example, an In _x Ga _{1 -x} P (x = 0.3, 10 nm) layer is formed at a depth 10 from the gate electrode 107 in the second semiconductor layer 104.
nm site. At this time, the two layers of the second semiconductor layer 104 and the third semiconductor layer 105 are p-type (2 × 1
0 ¹⁹ cm ^-3 ). After that, a transistor was formed in the same process as in Example 1.

Also in the second embodiment, the gate electrode 107
A third semiconductor layer 105 under the InGaP that is in contact with
As a result, there is an In _x Ga _{1 -x} P (x = 0.3, 10 nm) layer, so that the In _x Ga _{1 -x} P (x = 0.
Since the (3, 10 nm) layer is not thinned, the gate leak current can be reduced with good reproducibility. Further, in the second embodiment, the second semiconductor layer 104 and the third semiconductor layer 10
5 is doped with a p-type impurity (2 × 10 ¹⁹ cm ⁻³ ). For this reason, the built-in potential is increased, and an increase in the gate leak current that occurs when a positive voltage is applied to the gate electrode 107 can be suppressed.

In the second embodiment, the second semiconductor layer 1
04 and the third semiconductor layer 105 have p-type impurities (2 × 10
^{Although 19} cm ⁻³ ) was added, at least one or more of the three layers of the third semiconductor layer 105 and the second semiconductor layer 104 divided into two by the third semiconductor layer 105 were p-type. If the mold is doped, the built-in potential increases and the leakage current can be reduced. In the second embodiment, the other semiconductor materials described in the first embodiment can be applied.

(Embodiment 3) In Embodiment 3, as in Embodiment 1, after forming the first semiconductor layer 103 in FIG. 3, an InGaP layer, for example, having a thickness of 40 nm is formed as the second semiconductor layer 104. Then, for example, an In _x Ga _{1 -x} P (x = 0.3, 10 nm) layer is used as the third semiconductor layer 105 as the second semiconductor layer 105.
At a depth of 10 nm from the gate electrode 107 in the semiconductor layer. At this time, the second semiconductor layer 104 and the third
^Are doped into n-type (2 × 10 ¹⁷ cm ⁻³ ). After that, a transistor was formed in the same process as in Example 1.

In the third embodiment, the gate electrode 10
, A third semiconductor layer 105 under the InGaP that is in contact with
As there is an In _x Ga _1-x P (x = 0.3, 10 nm) layer, the structure is exposed as compared with the conventional structure exposed on the surface.
In _x Ga _1-x P (x =
0.3, 10 nm) layer does not become thin. Therefore, the gate leak current can be reduced with good reproducibility. In the third embodiment, an n-type impurity (2 × 10 ¹⁷ cm ⁻³ ) is added to the second semiconductor layer 104 and the third semiconductor layer 105. Therefore, the access resistance from the contact layer 110 to the first semiconductor layer 103 can be reduced, and a highly efficient transistor can be realized. In the third embodiment, the second semiconductor layer 104 and the third semiconductor layer 105 have n-type impurities (2
× 10 ¹⁷ cm ⁻³ ), but the third semiconductor layer 105
And at least one of the three layers of the second semiconductor layer 104 divided into two by the third semiconductor layer 105 is n.
If the mold is doped, the access resistance can be reduced. In the second embodiment, the other semiconductor materials described in the first embodiment can be applied.

(Embodiment 4) As the high resistance substrate 101, In
When a P substrate is used, the buffer layer 10
As the second layer, an undoped InP buffer layer is stacked with a thickness of 1 μm to 100 nm, for example, 200 nm, and an InP layer to which an n-type impurity is added as the first semiconductor layer 103 is a thickness in which, for example, a Si impurity is added at 1 × 10 ¹⁷ cm ^−3. 300
nm. Then, as the second semiconductor layer 104, for example, an undoped InAlAs layer 40 nm is formed, and as the third semiconductor layer 105, for example, In _x Ga _{1 -x}
The P (x = 0.3, 10 nm) layer is used as the second semiconductor layer 104
It was inserted at a position 10 nm deeper than the middle gate electrode 107. The source electrode 106 and the drain electrode 108 are InP layers in which an n-type impurity is added at a high concentration as the contact layer 110 on the second semiconductor layer 104, for example, a Si concentration of 2 ×
Using 10 ¹⁸ cm ⁻³ and a thickness of 50 nm, the same process as in Example 1 is used.

In the fourth embodiment, the gate electrode 10
A third semiconductor layer 10 under InAlAs in contact with
5, there is an In _x Ga _1-x P (x = 0.3, 10 nm) layer, so that the conventional In _x Ga _1-x P (x = 0.3, 1
In _x Ga _{1 -x} P (x = 0.3, 1
0 nm) layer is not thinned. For this reason, the gate leak current can be reduced with good reproducibility. In the fourth embodiment, the third semiconductor layer 105 has a thickness of 10 nm.
In _x Ga _1-x P (x = 0.3) was used in Example 1.
Other materials described in the above can also be applied. Further, as described in the second and third embodiments, n-type and p-type semiconductor layers can be used for the second semiconductor layer and the third semiconductor layer.

(Embodiment 5) When a sapphire substrate, a SiC substrate, or a GaN substrate is used as the high-resistance substrate 101, an undoped GaN buffer layer having a thickness of 3 μm to 100 n is used as the buffer layer 102 as in the first embodiment.
For example, a GaN layer to which an n-type impurity is added is formed as the first semiconductor layer 103 to have a thickness of, for example, 300 nm to which a Si impurity is added at 1 × 10 ¹⁷ cm ⁻³ . Further, as the second semiconductor layer 104, for example, an undoped Al _0.15 Ga _0.85 N layer is formed with a thickness of 40 nm, and as the third semiconductor layer 105, for example, Al _x Ga _1-x N (x
(= 0.7, 10 nm) layer was inserted into the second semiconductor layer 104 at a depth of 10 nm from the gate electrode 107. In addition, the source electrode 106 and the drain electrode 108 are formed by forming a GaN layer doped with a high concentration n-type impurity as a contact layer 110
It was manufactured in the same process as in Example 1 using 10 ¹⁸ cm ^-3 and a thickness of 50 nm.

In the fifth embodiment, the gate electrode 10
, A third semiconductor layer 105 under AlGaN in contact with
Since Al _x Ga _1-x N where (x = 0.7,10nm) layer is present as, conventional Al _0.15 Ga _0.85 N layer as compared to the structure exposed on the surface, A by etching in the process
The l _x Ga _1-x N (x = 0.7, 10 nm) layer is not thinned. Therefore, the gate leak current can be reduced with good reproducibility. In the fifth embodiment, as the third semiconductor layer 105, an undoped Al _x Ga _{1 -x} having a thickness of 10 nm is used.
Although N (x = 0.7) is used, n-type and p-type semiconductor layers can be used for the second semiconductor layer and the third semiconductor layer as described in the second and third embodiments.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described in detail with reference to the drawings.
FIG. 4 is a cross-sectional view showing a structural example of a field-effect transistor according to a second embodiment of the present invention, and FIG. 5 is an explanatory diagram showing an energy band below a gate electrode of the field-effect transistor shown in FIG. is there. In FIG. 4, the field-effect transistor according to the second embodiment includes a high-resistance substrate 2
01, a buffer layer 202 for improving the quality of an upper layer crystal, an undoped first semiconductor layer 203 through which carriers flow, and a first semiconductor layer 203 for supplying carriers to the first semiconductor layer 203. A second semiconductor layer 204 having an electron affinity smaller than that of 203 and to which an n-type impurity is added is sequentially formed. In addition, the third semiconductor layer 205 having a smaller electron affinity than the second semiconductor layer 204 has a crystal structure in which the third semiconductor layer 205 is inserted near the gate electrode 207 of the second semiconductor layer 204. Then, on this crystal structure, the source electrode 206, the gate electrode 207, and the drain electrode 208
Is formed.

In FIG. 5, carriers flow on the first semiconductor layer 203 side near a hetero interface formed by the first semiconductor layer 203 and the second semiconductor layer 204. The electrons 209 excited by heat try to flow over the Schottky barrier from the gate electrode 207 and flow into the first semiconductor layer 203, but have a third electron affinity smaller than that of the second semiconductor layer 204. In the structure without the semiconductor layer, the gate leakage current increases. On the other hand, in the structure of this embodiment, since the third semiconductor layer 205 having a high barrier height is present, the flowing current is significantly suppressed.

Further, since the second semiconductor layer 204 is present on the surface, the third semiconductor layer 205 is not etched during the process, and the barrier layer is not thinned.
Therefore, a field effect transistor having a small gate leak current with good reproducibility can be obtained. Further, in this structure, since the second semiconductor layer 204 is doped with n-type, the width of the depletion layer is small, and more electrons 209 are excited by heat than the field-effect transistor of the first embodiment, and the gate is gated. Over the semiconductor barrier from the electrode 207, the first
Flows into the semiconductor layer 203. Therefore, the effect of suppressing the gate leak current by inserting the third semiconductor layer 205 is large. Hereinafter, a specific example 6 of the present embodiment will be described.

(Embodiment 6) FIG. 6 is a sectional view showing a specific structure example of a field effect transistor according to a second embodiment of the present invention. In FIG. 6, undoped GaAs having a thickness of 1 μm to 100 nm, for example, 200 nm is stacked as a buffer layer 202 on a GaAs substrate as a high resistance substrate 201. Further, the first semiconductor layer 203
Undoped In _x Ga _1-x As layer, for example, x =
0.15, thickness of 300 nm, second semiconductor layer 2
As In 04, for example, an InGaP layer to which 1 × 10 ¹⁸ cm ⁻³ of Si is added is formed to a thickness of 30 nm. Further, for example, In _x Ga _{1 -x} P (x = 0.3,
10 nm) layer as the gate electrode 2 in the second semiconductor layer 204.
It was inserted at a site 10 nm deeper than 07.

The source electrode 206 and the drain electrode 2
Reference numeral 07 denotes a GaAs layer to which a high concentration of n-type impurity is added as the contact layer 210 on the second semiconductor layer 204, for example, having a Si concentration of 2 × 10 ¹⁸ cm ⁻³ and 50 nm, and an ohmic electrode formed thereon, for example. After vapor deposition of AuGe / Ni, it is alloyed by heat treatment. Gate electrode 20
7 is a method of removing the GaAs layer on the second semiconductor layer 204 to which a high concentration of n-type impurity is added by etching, exposing the InGaP layer to which the Si impurity is added as the second semiconductor layer 204, Prepared by In such a structure, the InG
In _x Ga _1-x P (x = 0.3, 10 nm) under aP
Due to the presence of the layer, the conventional In _x Ga _1-x P (x = 0.
(3, 10 nm) The gate leakage current can be reduced with good reproducibility compared to the structure where the layer is exposed on the surface.

In the sixth embodiment, as the third semiconductor layer 205, a 10 nm-thick In _x Ga ₁ -xP (x = 0.
3) was used, for example, in July 1990, Journal of Applied Physics, Vol. 68, No. 1, No. 10
It suffices that the thickness be within the range satisfying the relationship between the In composition and the critical film thickness of InGaP described in FIG. Desirably, the In composition is preferably as low as 4 nm or more is secured as the barrier thickness. Also, Al _x Ga _1-x As
(X0.5), In _x within the critical film thickness satisfies more than _{4nm (Ga 1-y Al y} ) 1-x P (x <0.51, y> 0)
Has the same effect. Also, the second semiconductor layer 20
The same effect was obtained even when No. 4 was an AlGaAs layer. Further, similar effects can be obtained in the combination of the substrate and the semiconductor material and the n-type and p-type doping layers shown in the above-described embodiments 2, 3, 4, and 5.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
An embodiment will be described in detail with reference to the drawings.
FIG. 7 is a cross-sectional view showing a structural example of the field-effect transistor according to the third embodiment of the present invention. FIG. 8 is an explanatory diagram showing an energy band below a gate electrode of the field-effect transistor shown in FIG. is there. In FIG. 7, the field-effect transistor according to the third embodiment includes a high-resistance substrate 3
01, a buffer layer 302 for improving the quality of the crystal of the upper layer, a first semiconductor layer 303 to which an n-type impurity through which carriers flow is added, and a first layer for supplying carriers to the first semiconductor layer 303. The second semiconductor layer 3 having a smaller electron affinity than the first semiconductor layer 303 and doped with an n-type impurity.
04 is formed. Then, the second semiconductor layer 30
Third semiconductor layer 305 having an electron affinity even smaller than 4
Are inserted in the vicinity of the gate electrode 307 of the second semiconductor layer on the crystal structure, and the source electrode 306, the gate electrode 307,
The drain electrode 308 is formed.

In FIG. 8, carriers flow on the first semiconductor layer 303 side near a hetero interface formed by the first semiconductor layer 303 and the second semiconductor layer 304. The first semiconductor layer 303 and the second semiconductor layer 304 are doped with an n-type impurity to increase the carrier concentration, the width of the depletion layer is reduced, and the electrons 309 excited by the heat are separated from the gate electrode 307 by a semiconductor barrier. Over the first semiconductor layer 30
3 easily flows into. However, the second semiconductor layer 3
Since there is the third semiconductor layer 305 having a smaller electron affinity and a higher barrier than that of the third semiconductor layer 03, the current flowing into the third semiconductor layer 305 is greatly suppressed. In addition, since the second semiconductor layer 304 is present on the surface, the third semiconductor layer 305 is not etched during the process, and the barrier layer is not thinned. Therefore, a field effect transistor having a small gate leak current with good reproducibility can be obtained.

In this structure, the first semiconductor layer 303
And the second semiconductor layer 304 is doped with an n-type impurity, the width of the depletion layer is small, more electrons 309 are excited by heat than in the field effect transistor of the second embodiment, and the Schottky barrier is higher than the gate electrode 307. And flows into the first semiconductor layer 303. Therefore,
The effect of reducing the gate leak current by inserting the third semiconductor layer 305 is large. Hereinafter, a specific example 7 of the present embodiment will be described.

(Embodiment 7) FIG. 9 is a sectional view showing a specific example of the structure of a field effect transistor according to a third embodiment of the present invention. In FIG. 9, a GaAs substrate is used as the high resistance substrate 301, and a buffer layer 302 is used as the high resistance substrate 301.
Undoped GaAs is stacked in a thickness range of 1 μm to 100 nm, for example, 200 nm. Further, as the first semiconductor layer 303, for example, an In _x Ga _{1 -x} As layer to which Si is added at ₁ × 10 ¹⁷ cm ⁻³ , for example, x = 0.15, and a thickness of 300
nm, and as the second semiconductor layer 304, for example, S
An InGaP layer to which i is added is formed to a thickness of 30 nm. Further, as the third semiconductor layer 305, for example, In _x Ga _1-x
The P (x = 0.3, 10 nm) layer is replaced with the second semiconductor layer 304
It was inserted at a depth of 10 nm from the middle gate electrode 307.

The source electrode 306 and the drain electrode 3
08 is a contact layer 310 on the second semiconductor layer 304.
For example, AuGe / Ni is deposited as a ohmic electrode on a GaAs layer to which a high concentration of n-type impurity is added, for example, with a Si concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of 50 nm, and then alloyed by heat treatment. In addition, the gate electrode 307
Is to remove the GaAs layer on the second semiconductor layer 304 to which a high concentration n-type impurity is added by etching, and then to expose the InGaP layer to which the Si impurity is added, which is the second semiconductor layer 304, by a registry lift-off method. Make it. In such a configuration, InGaP contacting the gate electrode 307
Existing in the lower layer, the conventional In _x Ga _1-x P (x =
(0.3, 10 nm) as compared with the structure in which the layer is exposed on the surface, the gate leak current can be reduced with high reproducibility.

In the seventh embodiment, a 10 nm-thick In _x Ga ₁ -xP (x = 0.
3) was used, for example, in July 1990, Journal of Applied Physics, Vol. 68, No. 1, No. 10
It suffices that the thickness be within the range satisfying the relationship between the In composition and the critical film thickness of InGaP described in FIG. Also, desirably, the In composition is lower while the barrier thickness is 4 nm or more. In addition, Al _x G
_{a 1-x As (x0.5)} , In x (Ga 1-y Al y) within the critical film thickness satisfies more than _{4nm 1-x P (x <} 0.5
1, y> 0), the same effect can be obtained. The same effect is obtained even when the second semiconductor layer 304 is an AlGaAs layer. Further, in the above-described embodiments 2, 3,
The same effect can be obtained with the combination of the substrate, the semiconductor material, and the p-type doping layer shown in FIG.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
An embodiment will be described in detail with reference to the drawings.
FIG. 10 is a sectional view showing a structural example of a field effect transistor according to a fourth embodiment of the present invention, and FIG. 11 is an explanatory diagram showing an energy band below a gate electrode of the field effect transistor shown in FIG. is there. In FIG. 10, the field-effect transistor according to the fourth embodiment has a buffer layer 402 for improving the quality of an upper crystal on a high-resistance substrate 401 and an n-type impurity in which carriers flow. One semiconductor layer 403 is sequentially formed, and a third semiconductor layer 405 having an electron affinity smaller than that of the first semiconductor layer 403 is inserted in the vicinity of the gate electrode 407 of the first semiconductor layer 403. The interface between the inserted third semiconductor layer 405 and the gate electrode 407 is connected to the source electrode 406.
The third semiconductor layer 403 is located at a depth of 1/2 or less of the depth of the depletion layer formed at the Schottky junction with the first semiconductor layer 403 when the potential of the gate electrode 407 is equal to that of the third semiconductor layer. A source electrode 406 and a gate electrode 40 are formed on a crystal structure in which the substrate-side interface of the layer 405 is located at a point shallower than the thickness of the depletion layer.
7. A drain electrode 408 is formed.

In FIG. 11, carriers flow through the first semiconductor layer 403. Electrons 409 excited by heat
Crosses over the semiconductor barrier from the gate electrode 407 and
, The third semiconductor layer 405 having a smaller electron affinity and a higher barrier height than the first semiconductor layer 403 prevents the current from flowing to a large extent. . Further, the first semiconductor layer 40 is provided on the surface.
Since 3 exists, the third semiconductor layer 405 is not etched and thinned during the process, and the barrier layer does not become thin. Therefore, a field effect transistor having a small gate leak current with good reproducibility can be obtained.

(Eighth Embodiment) FIG. 12 is a sectional view showing a specific structure example of a field effect transistor according to a fourth embodiment of the present invention. In FIG. 12, a high-resistance substrate 401
As a buffer layer 402, a GaAs substrate is used as
Undoped GaAs is stacked in a thickness of 1 μm to 100 nm in a thickness of, for example, 200 nm, and a first semiconductor layer 403 is stacked in a GaAs layer to which an n-type impurity is added, for example, in a thickness of 300 nm to which a Si impurity is added at 1 × 10 ¹⁷ cm ^−3. I do. Further, as the third semiconductor layer 405, for example, an undoped In _x Ga _{1 -x} P (x = 0.3, 10 nm) layer is formed at a depth of 1 from the gate electrode 407 in the first semiconductor layer 403.
Insert at 0 nm.

The source electrode 406 and the drain electrode 4
08 is a contact layer 410 on the first semiconductor layer 403.
A GaAs layer to which a high concentration of n-type impurity is added is formed with, for example, a Si concentration of 2 × 10 ¹⁸ cm ^{−3 and a} thickness of 50 nm, and then, for example, AuGe / Ni is deposited thereon as an ohmic electrode and then alloyed by heat treatment. I do. The gate electrode 407 is formed by etching and removing the GaAs layer on the first semiconductor layer 403 to which a high concentration n-type impurity is added.
GaAs doped with n-type impurities, which is the semiconductor layer 403 of FIG.
The layer is exposed and manufactured by a registry lift-off method. With such a configuration, Ga in contact with gate electrode 407 is formed.
In _x Ga as a third semiconductor layer 405 under the As layer
_{Since the 1-x} P (x = 0.3, 10 nm) layer is present, the process is compared with the conventional structure in which the In _x Ga _1-x P (x = 0.3, 10 nm) layer is exposed on the surface. The surface is not etched and the In _x Ga _1-x P (x = 0.3, 10 nm) layer is not thinned. For this reason, the gate leak current can be reduced with good reproducibility.

In the eighth embodiment, a 10 nm-thick (x = 0.3) is used as the third semiconductor layer 405, but the In semiconductor described in various academic journals and articles (publications) is used.
What is necessary is just to be in the range which satisfies the relationship between the In composition of GaP and the critical film thickness. Further, it is desirable that the In composition is lower while the barrier thickness is 4 nm or more. In the eighth embodiment, the insertion position of the third semiconductor layer 405 is 1 depth from the gate electrode 407 in the first semiconductor layer 403.
Although it is inserted at 0 nm, in order to reduce the gate leakage current, it is desirable that the insertion position is closer to the gate electrode 407, and considering that the surface is etched by about 2 nm during the process, a depth of 2 nm or more and less than 10 nm is considered. It is most effective to insert the

Here, as the third semiconductor layer 405, I
Although description has been made using n _x Ga _1-x P, for example, Al _x Ga 1
_1-x As (x0.5) _{and, In x (Ga 1-y} Al y) within the critical film thickness satisfies more than _{4nm 1-x P (x <} 0.5
1, y> 0) has the same effect. In the eighth embodiment, an undoped In _x Ga _{1 -x} P (x = 0.3, 10 nm) layer is used as the third semiconductor layer 407. However, a high-concentration P-type impurity, for example, carbon ¹⁹ cm
In _x Ga _1-x P added at ^-3 (x = 0.3, 10 nm)
If a layer is used, the leak current can be further reduced. Therefore, it can be used for a high-output transistor. Further, as the third semiconductor layer 407, In _x G doped with a high concentration of n-type impurity, for example, Si at 1 × 10 ¹⁸ cm ^−3.
If an a _1-x P (x = 0.3, 10 nm) layer is used, the source resistance can be reduced. Therefore, it can be used for a high-efficiency transistor.

[0049]

As described above, according to the present invention, a first semiconductor layer through which carriers flow, an electron affinity smaller than that of the first semiconductor layer, and a heterojunction with the first semiconductor layer are formed. A field effect transistor having a gate electrode and a second semiconductor layer forming a Schottky junction, wherein a third semiconductor layer having a smaller electron affinity than the second semiconductor layer is provided in the second semiconductor layer. The second semiconductor layer was inserted, and the insertion position was located closer to the Schottky junction interface formed by the second semiconductor layer and the gate electrode than the hetero interface formed by the second semiconductor layer and the first semiconductor layer. For this reason, it is possible to prevent the thermally excited electrons flowing from the gate electrode by the barrier layer provided in the semiconductor near the gate electrode, and since the barrier layer is in the semiconductor, it is etched during the gate electrode formation process. In addition, since the process has good reproducibility, a field-effect transistor having a small gate leak current can be manufactured with good reproducibility.

According to the present invention, there is provided a field effect transistor in which the first semiconductor layer is n-type or p-type, and the first semiconductor layer and the gate electrode form a Schottky junction.
A third semiconductor layer having an electron affinity smaller than that of the first semiconductor layer is inserted into the first semiconductor layer, and the inserted third semiconductor layer is inserted.
The interface between the semiconductor layer and the first semiconductor layer on the gate electrode side is し て of the depth of the end of the depletion layer formed at the Schottky junction when the potentials of the source electrode and the gate electrode are equalized. It is characterized by being located at the following depth and shallower than the depletion layer thickness on the substrate side. For this reason, it is possible to prevent the thermally excited electrons flowing from the gate electrode by the barrier layer provided in the semiconductor near the gate electrode, and since the barrier layer is in the semiconductor, it is etched during the gate electrode formation process. In addition, since the process has good reproducibility, a field-effect transistor having a small gate leak current can be manufactured with good reproducibility.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structural example of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an energy band below a gate electrode of the field effect transistor shown in FIG.

FIG. 3 is a sectional view showing a specific structure example of the field-effect transistor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a structural example of a field-effect transistor according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an energy band below a gate electrode of the field effect transistor shown in FIG.

FIG. 6 is a cross-sectional view illustrating a specific structure example of a field-effect transistor according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a structural example of a field-effect transistor according to a third embodiment of the present invention.

8 is an explanatory diagram showing an energy band below a gate electrode of the field effect transistor shown in FIG.

FIG. 9 is a cross-sectional view illustrating a specific structure example of a field-effect transistor according to a third embodiment of the present invention.

FIG. 10 is a sectional view showing a specific structure example of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 11 is an explanatory diagram showing an energy band below a gate electrode of the field-effect transistor shown in FIG.

FIG. 12 is a sectional view showing a specific structure example of a field-effect transistor according to a fourth embodiment of the present invention.

[Explanation of symbols]

101: high-resistance substrate, 102: buffer layer, 103
... First semiconductor layer, 104... Second semiconductor layer, 10
5... Third semiconductor layers 105 and 106... Source electrodes,
107: a gate electrode; 108: a drain electrode.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F102 GB01 GC01 GD01 GJ02 GJ04 GJ05 GJ06 GJ10 GK04 GK05 GN04 GN05 GQ01 GR04 HC15 HC19

Claims (19)

[Claims] A first semiconductor layer through which carriers flow; an electron affinity smaller than the first semiconductor layer; a heterojunction with the first semiconductor layer; and a gate electrode and a Schottky junction And a second semiconductor layer forming a second semiconductor layer, wherein a third semiconductor layer having an electron affinity smaller than that of the second semiconductor layer is inserted into the second semiconductor layer, and the insertion position is changed to a third position. A field effect transistor, which is disposed closer to a Schottky junction interface formed by the second semiconductor layer and the gate electrode than a hetero interface formed by the second semiconductor layer and the first semiconductor layer. 2. The field effect transistor according to claim 1, wherein the first semiconductor layer is a semiconductor exhibiting n-type or p-type conductivity. 3. The first semiconductor layer is a semiconductor to which an impurity is not added, and a region between the third semiconductor layer and the first semiconductor layer in the second semiconductor layer has an n-type or a p-type. The field effect transistor according to claim 1, wherein the field effect transistor is a semiconductor exhibiting conductivity. 4. The semiconductor device according to claim 1, wherein the second semiconductor layer of the second semiconductor layer sandwiched between the third semiconductor layer and the first semiconductor layer has the same conductivity as the first semiconductor layer. 3. The field effect transistor according to 2. 5. The semiconductor device according to claim 1, wherein at least one of the third semiconductor layer and the second semiconductor layer of the second semiconductor layer which is interposed between the third semiconductor layer and the gate electrode is formed of the first semiconductor layer. 5. The field effect transistor according to claim 2, wherein the field effect transistor exhibits conductivity opposite to that of carriers flowing in the semiconductor. 6. A method according to claim 6, wherein at least one of the third semiconductor layer and the second semiconductor layer of the second semiconductor layer which is interposed between the third semiconductor layer and the gate electrode has impurities. 4. A semiconductor which is not added.
Or the field-effect transistor according to 4. 7. A semiconductor device according to claim 1, wherein at least one of the third semiconductor layer and the second semiconductor layer of the second semiconductor layer which is interposed between the third semiconductor layer and the gate electrode is formed of the first semiconductor layer. 5. The field effect transistor according to claim 2, wherein the semiconductor has the same conductivity as carriers flowing in the semiconductor. 8. A field effect transistor in which the first semiconductor layer is n-type or p-type and the gate electrode and the first semiconductor layer form a Schottky junction, wherein the first semiconductor layer is formed in the first semiconductor layer. A third semiconductor layer having an electron affinity smaller than that of the third semiconductor layer, and the inserted third semiconductor layer;
The interface between the semiconductor layer and the first semiconductor layer on the gate electrode side is し て of the depth of the end of the depletion layer formed at the Schottky junction when the potentials of the source electrode and the gate electrode are equalized. A field-effect transistor, which is located at the following depth, and is located at a point shallower than a depletion layer thickness on a substrate side. 9. The field effect transistor according to claim 8, wherein the third semiconductor layer is free of impurities. 10. The semiconductor device according to claim 1, wherein at least one of the third semiconductor layer and the first semiconductor layer on the side of the first semiconductor layer sandwiched between the third semiconductor layer and the gate electrode is formed of the third semiconductor layer. 9. The field effect transistor according to claim 8, wherein the field effect transistor exhibits conductivity opposite to that of carriers flowing through the first semiconductor layer below the semiconductor layer. 11. A region between the third semiconductor layer and the gate electrode in the first semiconductor layer and the third semiconductor layer are formed by the third semiconductor layer.
9. The field effect transistor according to claim 8, wherein the field effect transistor has the same conductivity as carriers flowing through the first semiconductor layer below the semiconductor layer. 12. The first semiconductor layer is made of InGaAs, the second semiconductor layer is made of InGaP, and the third semiconductor layer is made of In _0.5 (Ga _1-y Al) lattice-matched to a GaAs substrate.
_8. The field effect transistor according to claim 1, wherein _y ) _0.5 P (1> y ≧ 0). A 13. A first semiconductor layer is InGaAs, a second semiconductor layer InGaP, the third semiconductor layer _{In x (Ga 1-y Al} y) 1-x P (x <0. 5, 1> y
≧ 0), characterized in that it is a strained layer.
8. The field effect transistor according to 3, 4, 5, 6, or 7. 14. The first semiconductor layer is made of InGaAs, and the second semiconductor layer is made of Al _x Ga _{1 -x} As (x <0.3).
And the third semiconductor layer is made of Al _x Ga _{1 -x} As (x ≧ 0.
5. The strained layer according to 5), wherein
The field-effect transistor according to 4, 5, 6, or 7. 15. The semiconductor device according to claim 15, wherein the first semiconductor layer is In _x Ga ₁ -xN.
(0.3 ≧ x ≧ 0), and the second semiconductor layer is made of Al _x G
a _1−x N (0 ≦ x <0.5), and the third semiconductor layer is A
8. The field effect transistor according to claim 1, wherein the field effect transistor is a strain layer of l _x Ga ₁ -xN (0.5 ≦ x ≦ 1). 16. A semiconductor device comprising: a first semiconductor layer made of InGaAs; and a third semiconductor layer made of InGaAs lattice-matched to a GaAs substrate.
12. The field effect transistor according to claim 8, 9, 10 or 11, wherein _0.5 (Ga _1-y Al _y ) _0.5 P (1> y ≧ 0) is a semiconductor layer. 17. The method according to claim 17, wherein the first semiconductor layer is made of InGaAs, and the third semiconductor layer is made of In _x (Ga _1-y Al _y ) _1-x P (x
12. The field effect transistor according to claim 8, 9, 10 or 11, wherein the strain layer has a strain of <0.5, 1> y≥0). 18. The method according to claim 1, wherein the first semiconductor layer is InGaAs, and the third semiconductor layer is Al _x Ga _{1 -x} As (0.5 ≦ x).
The field effect transistor according to claim 8, 9, 10 or 11, wherein the field effect transistor is a strained layer. 19. The method according to claim 19, wherein the first semiconductor layer is made of In _x Ga ₁ -xN.
(0.3 ≧ x ≧ 0), and the third semiconductor layer is made of Al _x
The field effect transistor according to claim 8, 9, 10, or 11, wherein the field effect transistor is a strained layer of Ga1 _-xN (0.5≤x≤1).