JP2000277652A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a package where an IC chip is mounted on a circuit board to be lessened in size and provided at a low cost by a method wherein a through-hole is filled up with resin, and the surface of resin exposed through the through-hole is set to be flush with the surface of a copper pattern formed on a circuit board. SOLUTION: A through-hole 4 is filled up with a UV-curing resin 6 through a printing method. At this point, a projection 12 is formed on each surface of a substrate 1. The UV-curing resin 6 filled into the through-hole 4 is exposed to UV for a certain time and pre-cured because the projections 12 of UV-cured resin 6 are easily flattened by cutting later. Then, a copper layer 5 is uniformly cut at the same time when the projections 12 of UV-cured resin 6 are flattened, by which the copper layer 5 is uniformly lessened in thickness. The copper layer 5 is set nearly as thick as a copper layer formed inside the through-hole 4, so that the through-hole 4 can be ensured of electrical connection reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the structure of a semiconductor package, and more particularly to the structure of a semiconductor package mounted on a high-density wiring circuit board.

[0002]

2. Description of the Related Art In recent years, a circuit board for mounting electronic devices at a high density has been limited due to the limit of the wiring density of the circuit board.
It has been multilayered. Further, build-up substrates have been developed to realize high-density wiring and multilayering. on the other hand,
A plastic ball grid array (hereinafter referred to as “PB”) has been developed to reduce the size and density of semiconductor packages.
The circuit board used for "GA" has been responded to by increasing the wiring density of the circuit board as the pitch of IC chip bonding is reduced.

FIG. 5 is a cross-sectional view of a substrate showing a method of manufacturing a conventional PBGA substrate. The substrate shown in FIG.
3A shows a member for mounting the IC chip of FIG. The copper foil 3 is laminated on both sides of the base material 2 to complete the substrate 1.

In the drilling step shown in FIG.
Through holes 4 are opened by the C driller.

In the EL + 1st copper plating step shown in FIG. 5C, the upper surface and the lower surface of the substrate 1 are electrically connected to the through holes 4 by electroless copper plating, and the copper is thickened by electric copper plating to provide connection reliability. Copper 5 is formed.

In the pattern forming step shown in FIG. 5D, a photosensitive dry film (hereinafter abbreviated as "DF") is laminated on copper, and the DF is exposed and developed, and the copper is cupric chloride. The copper pattern 7 is completed by etching with an etchant and removing the remaining DF. At this time, the copper is etched by the combined thickness of the copper foil 3 and the copper 5 to form the copper pattern 7. Therefore, since the thickness of copper is large, a fine pattern cannot be formed.

In the resist forming step shown in FIG. 5E, the copper pattern 7 is covered with a solder resist 9 except for a bonding portion of the copper pattern 7 with the IC and an external connection terminal portion.

In the Ni + Au plating step shown in FIG. 5F, Ni + Au8 is deposited by plating the bonding portion of the copper pattern 7 and the external connection terminal.

In the frame forming step shown in FIG. 5 (g), the completed circuit board is cut into a package manufacturing size from a circuit board manufacturing size to form a frame 10.

FIG. 6 is a sectional view of a substrate showing another conventional method for manufacturing a PBGA substrate. After copper plating, the through hole is filled with a thermosetting resin first, and the copper to be etched is thinned to form a fine pattern.
6A, the drilling step of FIG. 6B and FIG.
The EL + 1st copper plating step (c) is the same as the step shown in FIG. In the thermosetting resin filling step shown in FIG. 6D, the thermosetting resin 11 is filled in the through holes 4 by screen printing, and the thermosetting resin 11 is thermoset.

In the projection flattening step shown in FIG. 6E, the protrusions 12 of the thermosetting resin projecting from the through holes 4 are polished and shaved off.

The pattern forming step shown in FIG.
6G, the resist forming step shown in FIG.
The + Au plating step and the frame forming step shown in FIG. 6I are the same as the steps shown in FIG.

FIG. 7 is an enlarged sectional view of the thermosetting resin shown in FIGS. 6 (d) and 6 (e) after filling and polishing. FIG.
(A) shows a state where the thermosetting resin 11 is filled in the through holes 4. Since it is difficult to control the filling amount of the thermosetting resin filled by the screen printing method, the thermosetting resin jumps out of the through hole 4 to form the convex portion 12 or the concave portion 13 in the through hole 4. The convex portions 12 and the concave portions 13 are mixed on one surface of the substrate 1.

FIG. 7B shows a state after the protrusions 12 of the thermosetting resin are polished and flattened. Since the thermosetting resin 11 is thin, the shoulder portion 16 of the through-hole corresponding to the concave portion 12 is polished to the copper 5 of the shoulder portion 16 when polishing the convex portion 12 in the other through-hole 4 and is disconnected. Therefore, the copper 5 cannot be thinned.
Therefore, since the thickness of copper is large, a fine pattern cannot be formed.

[0015]

However, the structure of the semiconductor package using the above-described circuit board has the following problems. That is, a fine pattern could not be formed because the thickness of copper to be patterned was large. for that reason,
When increasing the number of pins of an IC chip, the circuit board becomes large and the cost cannot be reduced. In addition, it has not been possible to reduce the size of the circuit board and the size of the semiconductor package.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a low-cost and small-sized semiconductor package in which an IC chip is mounted on a circuit board. .

[0017]

In order to achieve the above object, in a semiconductor package in which an IC chip is mounted on a circuit board that electrically connects a surface opposite to one surface with a through hole, the through hole includes: The resin is filled with the resin and the surface of the resin exposed from the through hole is substantially the same as the copper pattern surface formed on the circuit board.

Further, there is substantially no gap between the side surface of the through hole and the resin.

The linear expansion coefficient of the resin is substantially the same as the linear expansion coefficient of the circuit board in the Z-axis direction.

Further, the resin is an organic resin.

Further, the organic resin is a UV-curable resin.

Further, the resin is a conductive resin.

Further, the conductive resin is a silver paste resin.

Further, the conductive resin is a copper paste resin.

Further, the thickness of the copper pattern is substantially the same as the thickness of copper adhered to the through hole.

Further, the copper pattern is covered with copper adhered to the through hole.

Further, the surface of the copper pattern is covered with a metal.

Further, the metal is nickel.

Further, the circuit board is a core board of a build-up board.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a semiconductor package according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a substrate showing a process of manufacturing a circuit substrate of a semiconductor package according to the present invention. FIG. 2 is an enlarged sectional view of a through hole portion of a circuit board of a semiconductor package according to an embodiment of the present invention. FIG. 3 is a sectional view of another embodiment of the present invention, in which a circuit board of the present invention is used as a core material of a build-up board of a semiconductor package. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor package of the present invention. The same members as those in the prior art are denoted by the same reference numerals.

FIG. 1 shows a process of manufacturing a circuit board of a semiconductor package according to the present invention. 1 (a), 1 (b), 1
(C) is the same as the prior art, and thus the description is omitted. In the UV-curable resin filling step shown in FIG. 1D, the UV-curable resin 6 is filled in the through holes 4 by a printing method. At this time, the protrusions 12 are formed on both surfaces of the substrate 1.

The UV-curable resin used in the present invention is, for example, an epoxy acrylate resin.

In the temporary curing step of the UV-curable resin shown in FIG. 1E, the filled-in UV-curable resin 6 is exposed and cured by UV.
In order to make the UV-curable resin 6 easier to flatten, the curing is temporarily stopped while the UV-curable resin 6 is temporarily cured.

The projection flattening step shown in FIG.
At the same time as the protrusions 12 of the curable resin 6 are flattened by shaving, the copper 5 is also shaved at the same time, so that the thickness of the copper is reduced uniformly. By making the thickness of the copper at this time substantially the same as the thickness of the copper in the through hole 4, it is possible to secure the reliability of the electrical connection of the through hole 4.

In the UV-curable resin main curing step shown in FIG. 1 (g), the remaining UV-curable resin is completely cured by heating.

In the pattern forming step shown in FIG. 1 (h), a copper pattern 7 is formed by laminating DF on thinned copper, exposing, etching, and stripping DF. Since the copper thickness is small, high-density wiring can be formed.

In the Ni + Au plating step shown in FIG. 1 (i), Ni plating necessary for bonding to the IC is performed on the copper pattern.
Cover + Au8 with plating.

The term “Ni” used in this specification
+ Au plating step ”means that after Ni plating, A
u refers to the step of further plating.

The resist forming step shown in FIG.
A solder resist 9 is formed so as to expose a bonding portion with C and an external connection terminal portion. In the case of a circuit board for a semiconductor package requiring high reliability because the thickness of the copper pattern 7 is small, the entire copper pattern 7 is covered with Ni + Au8. It is also possible to put before.

In the frame forming step shown in FIG. 1 (k), the completed circuit board is cut into a package manufacturing size from a circuit board manufacturing size to form a frame 10.

FIG. 2 is an enlarged cross-sectional view showing steps of filling and polishing of a UV curable resin in a through-hole portion of a circuit board for a semiconductor package according to the present invention. FIG. 2A is an enlarged view after the UV curable resin is temporarily cured. UV curable resin 6
Protrudes from the through-hole 4 and forms a projection 12 on the copper 5. A glass cloth organic substrate used for a circuit board for a semiconductor package has a linear expansion coefficient of about 14 PPM / CM in the X-axis direction and the Y-axis direction and a linear expansion coefficient of about 6 in the Z-axis direction.
0 PPM / CM, with a difference in linear expansion coefficient. Because UV curing resin is filled in the through hole,
By matching the linear expansion coefficient of the UV-curable resin with the linear expansion coefficient of the glass cloth organic substrate in the Z-axis direction, a reliable circuit board can be obtained.

FIG. 2B is an enlarged cross-sectional view of the substrate after polishing the UV curable resin. The UV curable resin 6 has the convex portion 12 cut off and the through hole 4 becomes flat, and at the same time, the electrolytic copper 15 in the copper 5 on the base material 2 is evenly cut, and the electroless copper 14 in the through hole 4 It is almost the same as the copper thickness of the side surface including the copper 15. Since the UV-curable resin 6 is semi-cured and shaved from the portion protruding from the through-hole, there is no shaving of the copper in the shoulder portion of the through-hole 4 and the shaved surfaces of the copper 5 and the UV-curable resin 6 It remains the same and flat. In addition, since the copper 5 covers the through hole 4 and the copper foil 3, the interface between the copper 5 and the copper foil 3 is not exposed, so that good electrical connection reliability can be secured.

Table 1 shows the wiring density actually formed on the copper pattern by the substrate structure of the present invention.

[0044]

[Table 1]

The copper foil of the base material of the present invention and the prior art is 1
The thickness is 2 microns, and a total thickness of 27 microns is obtained by adding 15 microns of electroless copper and electrolytic copper. Thereafter, in the present invention, the thickness of the copper is reduced to about 15 microns by shaving the UV-curable resin and the copper. On the other hand, in the prior art, since copper can hardly be removed, the thickness is about 25 microns. Due to this difference in thickness, by using the same process for pattern formation, the present invention was able to form a wiring of 40 micron space in a 40 micron pattern. On the other hand, in the prior art, 57
A wiring having a space of 57 microns was formed in a micron pattern. This translates to a 0.45
While the conventional technology can form six patterns with respect to the milliland pattern, the present invention shows that nine patterns can be formed and a pattern density of about 1.5 times is possible. In this description, a UV-curable resin is used as an example of the filling resin. However, by using a conductive resin such as a silver paste or a copper paste for the filling resin, a portion of the electrical connection above and below the substrate can be performed by the conductive resin. By making up, the diameter of the through hole can be reduced, so that the effect can be further increased.

FIG. 3 is a sectional view of a build-up substrate when the substrate structure of the present invention is applied to a core material of the build-up substrate. In this example, the core substrate 17 is a four-layer plate,
The core substrate 17 has an inner layer pattern 19. Core substrate 17
The through hole 4 is filled with a UV curable resin 6, and the copper 5 and the UV curable resin 6 are uniformly and thinly shaved so that a fine pattern can be formed, and a copper pattern 7 is formed. A build-up pattern 22 is formed on the core substrate 17 via an inner insulating film 21 and a via hole 20, and a build-up portion 18 is formed by covering the surface with a solder resist 9. Because the thickness of copper on the surface of the conventional core substrate is large, a fine pattern cannot be formed, and it is necessary to multiply the pattern of the build-up part,
By reducing the build-up pattern in the substrate structure of the present invention, the number of layers to be multilayered can be reduced.

FIG. 4 is a sectional view showing a semiconductor package manufacturing process of the present invention. The frame substrate shown in FIG. 4A is a semiconductor package frame substrate completed in the substrate manufacturing process shown in FIG.

The die bonding step shown in FIG.
24 is fixed on the frame 10 by the die bonding material 23.

In the wire bonding step shown in FIG. 4C, the pads on the IC 24 and the bonding patterns on the frame 10 are electrically connected by wires 25. Since a circuit board for a semiconductor package having high wiring density wiring is used, the pitch of the bonding pattern is also reduced.

In the sealing step shown in FIG. 4D, the IC 24 is covered with the sealing resin 26 in order to secure the reliability of the IC 24.

In the ball attaching step shown in FIG. 4E, a solder ball 27 serving as an external terminal is formed by placing the solder ball on an external terminal pad of the frame 10 and performing reflow.

In the singulation step shown in FIG. 4F, the semiconductor package 28 is formed by cutting the semiconductor package formed on the frame 10 into individual pieces. Although the above-mentioned semiconductor package is exemplified by a PBGA, the external terminals do not need to be protruding electrodes, and there is no problem if the external terminals are planar external terminals such as a land grid array or through-hole external terminals such as a plastic leadless chip carrier. There is no. Needless to say, there is no problem even with a multi-chip package.

Table 2 shows an example of package design when the semiconductor package of the present invention is applied to a PBGA.

[0054]

[Table 2]

Conventionally, a 326-pin PBG using a two-layer substrate
The A package has 27 external terminals at 1.27 mm pitch.
Although the size was a millimeter square, the external terminals of the semiconductor package of the present invention were 1.0 mm and the package size was 2 mm.
The size was 1 mm square, and the package size could be reduced by about 40%. 456-pin P using a 4-layer board
The BGA package has external terminals of 1.27 mm pitch and a size of 35 mm square, whereas the semiconductor package of the present invention has external terminals of 1.0 mm and a package size of 2 mm.
It was 9 mm square, and the package size could be reduced by about 30%.

[0056]

As described above, the semiconductor package having the structure of the present invention can be reduced in package size and can provide a low-cost semiconductor package.

Since there is almost no gap between the side surface of the through hole and the filling resin, a high-density package substrate can be provided, and a small semiconductor package can be manufactured at low cost.

The coefficient of linear expansion of the resin is
With a coefficient of linear expansion approximately equal to the axial direction, a reliable semiconductor package can be provided.

Further, since the resin is an organic resin, an inexpensive material can be used.

Further, since the organic resin is a UV-curable resin, the resin can be shaved in a semi-cured state, and copper and the resin can be uniformly shaved.

Further, since the resin is a conductive resin, the diameter of the through hole can be reduced, so that a semiconductor package using a high-density circuit board can be provided.

Further, since the conductive resin is a silver paste, it is possible to easily fill the through holes.

Further, since the conductive resin is a copper paste, it is possible to easily fill the through holes.

Further, by making the thickness of the copper pattern substantially equal to the thickness of the copper adhering to the holes, it is possible to provide a semiconductor package using a circuit board having high reliability and high density wiring.

Further, by covering the copper pattern with copper plated on the through holes, the interface between the plated copper and the copper pattern is not exposed, so that a semiconductor package using a reliable circuit board can be provided.

Further, since the copper pattern is covered with the metal, a reliable pattern can be formed.

Also, by using nickel for the covering metal,
It is the same as the base metal for IC mounting, and can be manufactured at low cost.

Also, by using the general circuit board as the core board of the build-up board, it becomes an inexpensive package board,
An inexpensive semiconductor package can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a substrate showing a method for manufacturing a circuit board for a semiconductor package according to the present invention.

FIG. 2 is a sectional view of a through-hole portion of the circuit board for a semiconductor package according to the present invention.

FIG. 3 is a cross-sectional view of a circuit board showing another circuit board for a semiconductor package according to the present invention.

FIG. 4 is an explanatory view of a semiconductor package showing a method of manufacturing a semiconductor package according to the present invention.

FIG. 5 is a cross-sectional view of a substrate showing a conventional method for manufacturing a circuit board for a semiconductor package.

FIG. 6 is a cross-sectional view of a substrate showing a method of manufacturing another conventional circuit board for a semiconductor package.

FIG. 7 is an explanatory view showing a cross section of a hole portion of another conventional circuit board for a semiconductor package.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Base material 3 Copper foil 4 Through hole 5 Copper 6 UV curing resin 7 Copper pattern 8 Ni + Au 9 Solder resist 10 Frame 11 Thermosetting resin 12 Convex part 13 Concave part 14 Electroless copper 15 Electric copper 16 Shoulder part 17 Core substrate Reference Signs List 18 Build-up part 19 Inner layer pattern 20 Via hole 21 Interlayer insulating film 22 Build-up pattern 23 Die bond material 24 IC 25 Wire 26 Sealing resin 27 Solder ball 28 Semiconductor package

Claims (13)

[Claims] 1. A semiconductor package in which an IC chip is mounted on a circuit board for electrically connecting a surface opposite to one surface by a through hole, wherein the through hole is filled with a resin, and A semiconductor package, wherein an exposed surface of the resin is substantially the same as a copper pattern surface formed on the circuit board. 2. The side surface of the through hole and the resin,
The semiconductor package according to claim 1, wherein there is substantially no gap. 3. The resin according to claim 1, wherein the coefficient of linear expansion is
2. The method according to claim 1, wherein the coefficient of linear expansion is substantially the same as the coefficient of linear expansion in the axial direction.
3. The semiconductor package according to 2. 4. The semiconductor package according to claim 1, wherein the resin is an organic resin. 5. The semiconductor package according to claim 4, wherein the organic resin is a UV-curable resin. 6. The semiconductor package according to claim 1, wherein the resin is a conductive resin. 7. The semiconductor package according to claim 6, wherein the conductive resin is a silver paste resin. 8. The semiconductor package according to claim 6, wherein the conductive resin is a copper paste resin. 9. The semiconductor package according to claim 1, wherein the thickness of the copper pattern is substantially the same as the thickness of copper attached to the through hole. 10. The semiconductor package according to claim 9, wherein the copper pattern is covered with copper attached to the through hole. 11. The semiconductor package according to claim 1, wherein a surface of the copper pattern is covered with a metal. 12. The semiconductor package according to claim 10, wherein said metal is nickel. 13. The semiconductor package according to claim 1, wherein the circuit board is a core board of a build-up board.