JP2000292523A - Display processing device - Google Patents

Abstract

(57) [Problem] To provide a display processing device for reducing deterioration of visibility due to moire or the like. SOLUTION: Polar coordinates of an input video signal are represented by XY coordinates (R
sin θ, Rcos θ) and the pixel (Rsin θ + 1, Rcos
The coordinates are added so that data is displayed also in θ). Then, the amplitude data of the XY coordinates is interpolated to the additional coordinates to reduce the number of pixels to which no data is written.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display processing device for visually displaying image data obtained by, for example, radar.

[0002]

2. Description of the Related Art As a radar display system used for distant surveillance, air defense surveillance, etc., for example, Japanese Unexamined Patent Publication No. 62-1321.
There is a radar scan conversion device disclosed in Japanese Patent Publication No. 84-84. FIG. 9 is a block diagram showing the configuration of this conventional radar scan conversion device. The device shown in the figure is an A / D converter 1p,
Serial / parallel converter 2p, image memory 3p, comparator 4p, first parallel / serial converter 5p, second parallel / serial converter 6p, rising / falling detecting circuit 7p, synthesizing circuit 8p, raster scanning Y It is constituted by an axis address generator 9p.

Next, the operation of the above-mentioned conventional radar scan converter will be described. An analog video signal input to this device is first converted into a digital video signal by an A / D converter 1p. The converted signal is applied to the serial / parallel converter 2, where the serial signal is converted into a parallel signal for each distance unit and then input to the image memory 3p. The image memory 3p is a memory composed of a large number of pixel storage elements having addresses defined by distance axis (X-axis) coordinates and amplitude axis (Y-axis) coordinates.

A raster scanning Y-axis address generator 9p generates a Y-axis address when performing raster scanning,
This is added to the comparators 4p provided for the number of pixels on the distance axis. Further, to these comparators, a Y-axis address (referred to as a sample value) corresponding to the X-axis scan (address) of the raster scan is sequentially read from the image memory 3p.

Each comparator compares the raster scan Y-axis address with the sample value, and outputs a "video presence signal" when they match and when the raster scan Y-axis address is smaller than the sample value. Then, of these output videos, those at the time of matching with the sample value are put together, and the first parallel / serial converter 5
Output to p.

On the other hand, the second parallel / serial converter 6
In p, when the video output is equal to or smaller than the sample value, that is, when the video output is equal to or smaller than the sample value,
Below the sample value is added as a video group.

For example, when the output of the first parallel / serial converter 5p is displayed on the monitor instruction device 111p, as shown in FIG. 10, the information is stored in the image memory 3p as shown in FIG. Image appears.
However, in this image, a gap exists in the Y-axis direction.

On the other hand, when the output of the second parallel / serial converter 6p is displayed on the monitor instruction device 111p, in this case, since all signals exist at the Y-axis address equal to or less than the sample value, the displayed image is displayed. Is as shown in FIG. Therefore, the signal at the periphery of this image is
Taken out by the falling detection circuit 7p,
As a result, when combined with the sample matching video sequence, an A-scope display in which the gap in the Y-axis direction of the sample values is filled is obtained as shown in FIG.

[0009]

However, in the case of a coordinate system in which an input video signal is input in a polar coordinate system (R, θ), as shown in FIG. 13, an image memory composed of an XY coordinate system is used. Need to convert the data. At this time, when the distance from the center increases (R →
Large), even if only the input data direction (that is, the R direction) is continuously written to the image memory in the same way as in the past,
There is a problem that a pixel to which data is not written occurs between the R direction and the next R direction, and a geometric pattern (referred to as moiré) is formed, and visibility as an image is deteriorated. .

Therefore, in order to suppress the occurrence of moire,
It is first conceivable to reduce the value of θ. However, when the value of θ is reduced, there is a problem that the amount of data processing increases accordingly and high-speed processing cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to perform processing for making moiré or the like inconspicuous in real time on an input video signal, and to improve visibility by this moiré or the like. An object of the present invention is to provide a display processing device that reduces deterioration.

[0012]

According to the present invention, there is provided a display processing apparatus for displaying an input image signal on a display, wherein the coordinates of the image signal indicate a predetermined pixel position. First conversion means for converting the first XY coordinates into first XY coordinates, second conversion means for converting the first XY coordinates into second XY coordinates indicating a pixel position adjacent to the pixel position, and Means for writing pixel data indicated by the first XY coordinate as interpolation data at a pixel position indicated by the second XY coordinate; means for storing the pixel data indicated by the first XY coordinate and the interpolation data in an image memory; A display processing device for visually displaying the image data stored in the image memory.

Preferably, the second conversion means converts the first XY coordinates in the X and / or Y axis directions to obtain the second XY coordinates.

According to the present invention, in a display processing device for displaying an input image signal on a display, a first conversion for converting coordinates of the image signal into first XY coordinates indicating a predetermined pixel position. Means for converting the first XY coordinates to second XY coordinates indicating a pixel position adjacent to the pixel position; and converting the first XY coordinates to the pixel position and one pixel A third converting means for converting the image data into a third XY coordinate indicating a pixel position adjacent to the first XY;
Means for obtaining average pixel data of pixel data indicated by coordinates and pixel data indicated by the third XY coordinates; means for writing the average pixel data as interpolation data at a pixel position indicated by the second XY coordinates; First and second XY
Means for storing pixel data indicated by coordinates and the interpolation data in an image memory, wherein the display provides a display processing device for visually displaying the image data stored in the image memory.

Preferably, the second and third conversion means convert the first XY coordinates in the X and / or Y axis directions to obtain the second and third XY coordinates.

The display processing device according to the present invention further comprises means for storing the XY coordinates after the coordinate conversion, means for determining the difference between the pixel positions indicated by the stored XY coordinates, and Means for determining the presence or absence of a pixel position requiring interpolation. Preferably, when the difference is 0, pixel data having a predetermined value or less is invalidated.

Preferably, the image memory is a plurality of memories arranged in parallel, and the display unit displays image data by a PPI scope method. Writing and reading are switched every time the PPI scans.

Preferably, the plurality of image memories include:
The converted XY coordinates are parallelized for even Y coordinates and odd Y coordinates. Further, image data is written in the plurality of image memories in a predetermined order, and the written image data is read out by simultaneously accessing the plurality of image memories.

Preferably, the display visually displays the peak value of the read image data. The image memory is a dual addressable memory that can simultaneously write and read image data.

[0020]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 FIG. First, Embodiment 1 of the present invention will be described. FIG. 1 is a block diagram showing a configuration of the display processing device according to the present embodiment. The apparatus shown in FIG. 1 includes an interpolation coordinate generation circuit 100 including a pixel coordinate converter 1, a delay circuit 2, an adder 3, and a multiplexer 4, a FIFO 5,
Amplitude comparator 6, timing controller 7, raster address generator 8, multiplexer 9, image memory 10, output register 11, parallel / serial converter 12, D /
An A converter 13 and a monitor 14.

The coordinates (R, θ) of the video signal input to the apparatus according to the present embodiment are converted from polar coordinates to XY coordinates (Rsin θ, Rcos θ) corresponding to the pixel unit of the screen by the pixel coordinate converter 1. Is done. Note that a delay circuit 2 is provided to delay a video signal in order to match delays caused by the coordinate conversion.

The address converted into the XY coordinate system is input to the FIFO 5 together with the amplitude data having passed through the delay circuit 2, but before that, the X coordinate is selected by the adder 3 by the multiplexer 4 before the X coordinate. Value 0,
After adding 1 (length per unit pixel), FIFO5
Is input to

The switching of the multiplexer 4 is performed by the timing controller 7 at twice the frequency of the input video signal. That is, (Rsin θ + 1, Rcos θ) is added to the coordinates of the video signal input to the FIFO 5. The added coordinates (R sin θ + 1, Rco
sθ) is represented by (Rsinθ, Rcos
Use the amplitude data corresponding to θ).

The video data written in the FIFO 5 is written to the image memory 10 in the following procedure. That is, the video data is read from the FIFO 5, the previous amplitude data at the address is read from the image memory 10, and the read data and the FIFO data are read.
The data from the FO 5 is compared with the amplitude comparator 6. Then, the data read from the image memory 10 is
If the data from the FO5 is larger, the data from the FIFO5 is written into the image memory 10.

The above comparison is performed by the image memory 10
This is because the maximum value data is always written to the As described above, the data is sequentially read from the FIFO 5, the data is compared with the previous amplitude data, and when the data from the FIFO 5 is larger, the data is sequentially written into the image memory 10.

Next, a procedure for reading data from the image memory 10 will be described. The raster display is usually performed by repeating the scanning of the screen at a constant cycle (about 60 Hz). The raster address generator 8 generates a screen address for this scanning. Then, the address generated by the raster address generator 8 is provided to the image memory 10 via the multiplexer 9.

Data corresponding to the above address is read out from the image memory 10 and is read out from the output register 11.
Sent to The output register 11 includes the image memory 1
Data read from 0 is held for a moment. The output register 11 is parallelized in order to reduce the number of accesses to the image memory 10. For example, a parallel configuration of 192 bits (RGB 8 bits × 8 pixels)
It has become.

The data described above is sent from the output register 11 to the parallel / serial converter 12, where it is converted into serial data. As a result, the data becomes RGB luminance data in pixel units. Then, the luminance data is converted into an analog signal by the D / A converter 13 at the next stage, and is finally displayed on the monitor 14.

The timing controller 7 includes a control timing of the pixel coordinate converter 1, a switching signal of the multiplexer 4, a FIFO 5
In addition, as the timing control on the reading side, a start control of the raster address generator 8 and a synchronization signal to the monitor 14 are output.

As described above, according to the present embodiment, polar coordinates are converted to XY coordinates (R sin θ, R sin
cos θ), and by adding coordinates so that data is displayed on the next pixel (Rsin θ + 1, Rcos θ) in the direction of + in the X-axis direction, the number of pixels to which data is not written is reduced. As a result, the occurrence of moire can be reduced.

In the display processing apparatus according to the first embodiment shown in FIG. 1, only an X coordinate is provided with an adder and a multiplexer for transforming the X coordinate. However, the present invention is not limited to this. That is, an adder and a multiplexer may be similarly provided not only for the X coordinate but also for the Y coordinate so as to interpolate pixels in the Y axis direction.

In the first embodiment, the inputs to the multiplexer are 0 and 1, but they are added as 2, 3,... As necessary, and the addresses of the original addresses +2 and +3 are further added. Interpolation may be performed. At that time, the multiplexer switching timing in the timing controller is also added accordingly.

Embodiment 2 FIG. Hereinafter, Embodiment 2 of the present invention will be described. FIG. 2 is a block diagram showing a configuration of a display processing device according to Embodiment 2 of the present invention. In the figure, the same components as those of the device according to the first embodiment shown in FIG.
A description thereof will be omitted.

In the device according to the first embodiment, the value for which the next pixel (X + 1 or Y + 1) is to be interpolated is the amplitude data of the input video signal. However, the value to be interpolated is not limited to this, and may be the average value of the input video signal and the value when the previous frame of the next two pixels (X + 2 or Y + 2) is drawn.

In the display processing device according to the second embodiment,
In the pixel coordinate converter 1, the coordinates of the input video signal are converted from polar coordinates to XY coordinates, which are written to the FIFO 5. On the other hand, the amplitude data is the same as in the first embodiment.
For the same reason as described above, the timing with the coordinate data is adjusted by the delay circuit 2 and then written into the FIFO 5.

In the adder 3, 0 selected by the multiplexer 4 is added to the coordinate data read from the FIFO 5 to obtain (Rsin θ, Rcos θ).
At this time, the coordinates (R sin θ, R
cos θ) is read out, and the previously written coordinates (Rsin θ, Rco
sθ) is read out.

These amplitude data are compared by the amplitude comparator 6 and the amplitude data from the FIFO 5 is stored in the image memory 1.
If it is larger than the amplitude data read from 0, it is written to the image memory 10 as the amplitude data of the coordinates (Rsinθ, Rcosθ). That is, in this case, the multiplexer 17 selects the input (a).

Next, the adder 3 adds 2 selected by the multiplexer 4 to the coordinate data read from the FIFO 5, and sets the coordinates to (Rsin θ + 2, Rcos
θ). Then, the previous amplitude data of this address is read out from the image memory 10, the data is added by the adder 15 to the amplitude data read out from the FIFO 5, and the obtained data is halved by the divider 16. The result is input to the amplitude comparator 6 through the multiplexer 17.

The adder 3 simultaneously adds 1 selected by the multiplexer 4 to the coordinate data read from the FIFO 5 to obtain (Rsin θ + 1, Rcos θ).
Then, the previous amplitude data at this address is read from the image memory 10 and input to the amplitude comparator 6.

The amplitude comparator 6 has the image memory 1
0 is compared with the amplitude data read from the FIFO 5 and processed by the divider 16 and obtained through the multiplexer 17. If the data obtained through the multiplexer 17 is larger, the data Is written into the image memory 10 as amplitude data of coordinates (Rsin θ + 1, Rcos θ) (that is, the multiplexer 17 selects the input (b)).

As described above, when the coordinates of the input video are (X, Y), the display processing device according to the present embodiment, the input amplitude data and the previous (X + 2, Y) or (X, Y)
+2) and a circuit for taking an average value with the amplitude data of (X + Y) or (X + Y + Y).
1)) is the amplitude data to be interpolated.

As described above, according to the present embodiment, the average value of the input data and the data of the coordinates apart from the input data is set at the adjacent coordinates of the input video as a value for interpolating the next pixel. Find the value, that is, the input video signal and
By interpolating to the intermediate coordinates using the average value of the previous frame of the two adjacent pixels and the value when the previous frame was drawn, it is possible to reduce the gap between the pixels and consequently reduce the occurrence of moire it can.

Note that the display processing device according to the second embodiment shown in FIG. 2 also includes an adder and a multiplexer for converting only the X coordinate, but the present invention provides The configuration is not limited, and for example, X
It goes without saying that an adder and a multiplexer may be similarly provided not only for the coordinates but also for the Y coordinates to interpolate pixels in the Y-axis direction.

Embodiment 3 FIG. Hereinafter, Embodiment 3 of the present invention will be described. FIG. 3 is a block diagram showing a configuration of a display processing device according to Embodiment 3 of the present invention. In the figure, the same components as those of the device according to the first embodiment shown in FIG.
A description thereof will be omitted.

In the first embodiment, data is interpolated to surrounding pixels regardless of the presence or absence of a pixel to which data is not written. In the present embodiment, the presence or absence of a pixel to which data is not written is checked. Then, data is interpolated only when it exists.

In the display processing device according to the present embodiment, the coordinates of the input video signal are
After being converted from polar coordinates to XY coordinates, they are input to the FIFO 5. Then, the coordinate data read from the FIFO 5 is input to the sweep buffer A18. Note that the sweep buffer A18 and the sweep buffer B
19 is a buffer for storing coordinate data for one sweep.

The coordinate comparator 20 has a sweep buffer A1
8 and the X coordinate stored in the sweep buffer B19,
The Y-coordinates are compared, and when the difference is 1 or less, the multiplexer 4 selects 0. When the difference between the X coordinate and the Y coordinate is n (n ≧ 2) or more, a signal is sent from the coordinate comparator 20 so that the multiplexer 4 sequentially selects 1, 2,..., N−1.

At this time, the adder 3 sequentially generates coordinates obtained by adding 1, 2,..., N−1 to the original coordinates.
From the image memory 10, amplitude data corresponding to the coordinates is sequentially read. Then, the amplitude comparator 6 compares the amplitude data with the amplitude data of the original coordinates,
If the data from the FIFO 5 is larger, the data is written to the image memory 10 as the amplitude of the coordinates.

As described above, in the present embodiment, the X and Y coordinates of successive sweeps are compared with each other, and when a gap is formed in a pixel (when the difference between the X and Y coordinates becomes 2 or more, respectively), The open pixel is provided with a dual sweep buffer for interpolating the amplitude data.
By determining the pixel position requiring interpolation from the difference between the two points of the coordinates, the generation of data requiring interpolation can be reduced.

Embodiment 4 Hereinafter, Embodiment 4 of the present invention will be described. FIG. 4 is a block diagram showing a configuration of a display processing device according to Embodiment 4 of the present invention. In the figure, the same components as those of the device according to the first embodiment shown in FIG.
A description thereof will be omitted.

Also in the device according to the fourth embodiment shown in FIG. 4, the coordinates of the input video signal are converted from polar coordinates to XY coordinates by the pixel coordinate
Input to FO5. These XY coordinates and amplitude data are
Sweep buffer 1 (34) and sweep buffer 2
Written in (35), the coordinate and amplitude comparator 33
First, the coordinates are compared, and if they are the same, the amplitudes are compared. Then, as a result of the amplitude comparison, the larger amplitude data is sent to the amplitude comparator 6.

The amplitude comparator 6 inputs the video data of the coordinates from the image memory 10, and if the video data from the coordinates and amplitude comparator 33 is larger than the data, the larger is input to the image memory 10. Write to. In addition,
The smaller amplitude data is invalid and is not written in the image memory 10.

As described above, according to the present embodiment, when the same coordinates occur in successive sweeps, the respective amplitude data are compared, and the smaller one of them is invalidated, so that the image data is stored in the image memory. The number of data to be written can be reduced. In other words, since the number of accesses to the image memory is reduced by reducing the number of data, it is possible to reduce the occurrence of noise and to allow time for accessing the image memory.

Embodiment 5 FIG. FIG. 5 is a block diagram showing a configuration of a display processing device according to Embodiment 5 of the present invention. In the figure, the same components as those of the device according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here.

The apparatus according to the first embodiment uses one image memory 10 to simultaneously write data, read data for display, and erase data. When the data amount increases, the data is read from the memory. And the time for writing is limited. Therefore, the apparatus according to the present embodiment employs a configuration in which image memories are provided in parallel to allow a margin for access time.

In the apparatus according to the present embodiment shown in FIG. 5, the image memory A24 and the image memory B25 store the PPI
(Plan position indicator)
Is switched between writing, reading for display, and erasing every scan (repetition of θ). The scan flag generator 23 sets the scan flag to 1 and 0 each time the PPI is scanned (repeated θ).
And output alternately.

For example, when the scan flag is 0, the multiplexer 9b switches to the FIFO 10 side, and the image memory A24 performs an operation of writing amplitude data obtained by amplitude comparison. At this time, a scan flag is attached to the video data, and the video data is attached to the image data for writing, and is used for an erasing operation at the time of reading described later.

At this time, the multiplexer 9d
Has been switched to the raster address generator 8 side, and the image memory B25 performs a read operation.

When the display operation is completed for one scan, the operation of the image memory A24 and the operation of the image memory B25 are switched, and the data of the memory is written by writing 0 data to the memory that was performing the display operation. clear. In the case of a memory having a signal terminal capable of clearing all memory elements, a clear operation is performed using the signal terminal.

As described above, according to the present embodiment, by providing the image memories in parallel and switching between writing and reading each time the PPI is scanned, there is ample time for memory access.

Embodiment 6 FIG. Hereinafter, Embodiment 6 of the present invention will be described. FIG. 6 is a block diagram showing a configuration of a display processing device according to Embodiment 6 of the present invention. In the figure, the same components as those of the apparatus according to the fifth embodiment shown in FIG.
A description thereof will be omitted.

In the apparatus according to the fifth embodiment, the erasing operation of the image memory A24 and the image memory B25 is performed using the raster address. However, in the present embodiment, the erasing (attenuating) operation is performed on the writing side. Is performed, the parallel operation is enabled.

The device according to the present embodiment has a configuration in which the image memory has not only the parallel output of the pixels on the X side but also the pixels on the Y side in parallel. That is, the Y image memory 28 has an image memory of an odd address, and Y + 1
The image memory 29 has an even number of Y image address memories.

When a write address is input from the FIFO 10, the trail address generator 27 generates a Y-side input address +1 of the FIFO 10, and when writing, Y is advanced by one with respect to the input address.
Accessing the memory on the side also enables parallelization.

The X side is originally parallelized (for example, if a 16-bit length memory is used for 8 bits of video data, it has two parallel addresses of X and X + 1). In this case, in one writing, four pixel points are simultaneously trailed in synchronization with the writing side.

The trail data is generated by setting the scan flag attached to the video data (in the case where the scan flag needs to be more finely attenuated than for each scan, for example, the trail attenuated every 45 ° rotation). If so, a 3-bit flag of 45 °, 90 °, and 180 ° is used) and the following operation is performed.

First, the video data from the FIFO 10 is read out from the Y image memory 28 or the Y + 1 image memory 29 at the same address.
The comparison is performed by the comparator B37. If the video data from the FIFO 10 is larger, the data is written to the corresponding Y image memory 28 or Y + 1 image memory 29.

When the scan flags are different,
Comparator A36 provides video data from FIFO 10 with:
The data read from the image memory is compared with the data after being attenuated by the trail coefficient generation circuit 26, and the current scan flag is attached to the larger data, and the larger data is stored in the corresponding Y image memory 28 or Y + 1 image memory 29. Write to.

Similarly, if the scan flags are different,
The memory on the trail address side updates the scan flag to the current scan flag together with the data from the image memory side attenuated by the trail coefficient generation circuit 26 by the comparator A36, and writes it to the memory. Note that the image memory on the trail address side does nothing with the same scan flag.

As described above, according to the present embodiment, two Y-side image memories are provided in parallel at odd addresses and even addresses, that is, with respect to converted XY coordinates, even Y coordinates By arranging and parallelizing the image memories for the odd-numbered Y coordinates, it is possible to allow time for accessing the memories.

Embodiment 7 FIG. Hereinafter, a seventh embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration of the display processing device according to the seventh embodiment. The device shown in the figure is an example in which the image memory of the device according to the first embodiment shown in FIG. 1 is parallelized, and FIG. 7 shows the same configuration as the device according to the first embodiment. Elements have the same reference numerals. In addition, illustration of portions common to the device according to the first embodiment and the device according to the present embodiment is omitted.

As described above, the first embodiment shown in FIG.
The image memory of the device according to (1) is one, and therefore, when the amount of write data increases, there is no room in the memory access time. Therefore, in the seventh embodiment, the image memory is configured by a plurality (n) of memories.

In the apparatus according to this embodiment, the FIFO 5
The read first video data is written by the distributor 31 via the multiplexer 6-1 to the corresponding XY coordinate address of the first image memory 10-1. Next, the video data read from the FIFO 5 is written by the distributor 31 via the multiplexer 6-2 to the corresponding XY coordinate address of the second image memory 10-2.

Similarly, the video data read from the n-th FIFO 5 through the multiplexer 6 is written by the distributor 31 to the corresponding XY coordinate address of the n-th image memory 10-n. Although the illustration of the amplitude comparison circuit 6 and the like is omitted here as described above, they are arranged at the input stage of each image memory, similarly to the device according to the first embodiment.

The image memory into which the video data is written operates as follows during the display time. First, the raster address output from the raster address generator 8 is simultaneously input to all the image memories 10-1 to 10-n through the multiplexers 6-1 to 6-n. Then, the peak value of the video data output from the image memory is selected by the OR circuit 30.

That is, the OR circuit 30 selects the peak value of the video data from each image memory and outputs it to the output register 11. In FIG. 7, the trail coefficient generating circuit for performing the attenuation process is omitted.
This processing is performed by subtracting the trail coefficient from the value read when the raster address is given to the image memory and writing the result.

As described above, according to this embodiment, a plurality of image memories are arranged in parallel, video data is sequentially distributed and written, and at the time of display, these image memories are accessed simultaneously. Then, by displaying the peak value of the data, the access time to the memory can be spared.

Embodiment 8 FIG. Hereinafter, an eighth embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration of the display processing device according to the eighth embodiment. FIG.
Here, the same components as those of the device according to the first embodiment are denoted by the same reference numerals. In addition, illustration of portions common to the device according to the first embodiment and the device according to the present embodiment is omitted.

In the apparatus according to the first embodiment shown in FIG. 1, the image memory is described as a single address memory. However, the present invention is not limited to this, and the image memory may be a dual addressable memory. A memory (one having two write and read sense lines for one storage element constituting the memory) may be used.

In the apparatus according to the present embodiment shown in FIG. 8, first, an XY address is input from the FIFO 5 to the dual addressable memory 32, and the previously written video data is read according to the address. Then, the amplitude comparator 6 determines the amplitude of the data read in this way and the video data read from the FIFO 5. Here, the data is written into the dual addressable memory 32 only when the data from the FIFO 5 is larger.

On the other hand, on the display side, since the memory used here is the dual addressable memory 32, the raster address generator 8 operates asynchronously with the reading on the FIFO 5 side to generate a raster address, and Is given to the memory 32.

The dual addressable memory 32
After the data corresponding to the above address is given to the output register 11, the trail coefficient generation circuit 2
Attenuation is added by the dual addressable
Writing to the memory 32 is performed.

When the XY address of the write from the FIFO 5 and the XY address of the write from the trail coefficient generating circuit 26 completely match, usually, the dual addressable
Do arbitration (priority processing) in memory,
Alternatively, a time difference is generated under the control of the timing controller 7 so that they do not completely match.

As described above, according to the present embodiment, a dual addressable memory is used as an image memory, and a raster address system for writing and displaying video data is temporally separated, and these can be simultaneously processed. By doing
It is possible to allow time margin for memory access.

[0085]

As described above, according to the present invention,
A display processing device for displaying an input image signal on a display, a first conversion means for converting the coordinates of the image signal into first XY coordinates indicating a predetermined pixel position;
A second conversion unit for converting the XY coordinate of the first pixel into a second XY coordinate indicating a pixel position adjacent to the pixel position;
Means for writing the pixel data indicated by the XY coordinates as the interpolation data at the pixel position indicated by the second XY coordinates, and means for storing the pixel data indicated by the first XY coordinates and the interpolation data in the image memory. In addition, the display device can reduce the number of pixels to which data is not written by visually displaying the image data stored in the image memory, thereby reducing the occurrence of moire.

The second conversion means converts the first XY coordinates in the X and / or Y-axis directions to obtain the second XY coordinates, so that the pixels to which no data is written can be obtained. Can be reduced.

According to the present invention, in a display processing device for displaying an input image signal on a display device, a first XY coordinate for converting the coordinates of the image signal into first XY coordinates indicating a predetermined pixel position is provided. Conversion means for converting the first XY coordinates to second XY coordinates indicating a pixel position adjacent to the pixel position; and converting the first XY coordinates to the pixel position. A third conversion unit that converts the pixel data into third XY coordinates indicating pixel positions adjacent to each other by one pixel;
Means for calculating average pixel data of pixel data indicated by the XY coordinates and pixel data indicated by the third XY coordinates, means for writing the average pixel data as interpolation data at a pixel position indicated by the second XY coordinates, , The first and second
Means for storing the pixel data indicated by the XY coordinates and the interpolation data in the image memory, and the display reduces the gap between pixels by visually displaying the image data stored in the image memory. As a result, the occurrence of moire can be reduced.

Further, the second and third conversion means may include:
Since the first and second XY coordinates are converted in the X and / or Y axis directions to obtain the second and third XY coordinates, the gap between pixels can be significantly reduced.

The display processing apparatus according to the present invention further comprises means for storing the XY coordinates after the coordinate conversion, means for determining the difference between the pixel positions indicated by the stored XY coordinates, And means for judging the presence or absence of a pixel position requiring interpolation can reduce the amount of data requiring interpolation.

When the difference is 0, the generation of data requiring interpolation can be greatly reduced by invalidating the pixel data having a predetermined value or less.

The image memory is constituted by a plurality of parallel memories, and the display device displays image data by a PPI scope method. By switching between writing and reading, there is a margin in time for memory access.

Further, by parallelizing the plurality of image memories for the even-numbered Y coordinates and the odd-numbered Y coordinates with respect to the coordinate-converted XY coordinates, a time margin is provided for memory access. Can be made.

Further, the image data is distributed to the plurality of image memories in a predetermined order, and the image data is written. It is possible to allow time to spare.

[0094] Further, the display unit visually displays the peak value of the read image data, so that the access time to the memory can be spared.

The image memory is a dual addressable memory that can simultaneously process writing and reading of image data, so that a time margin can be provided for memory access.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a display processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a display processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a display processing device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a display processing device according to Embodiment 4 of the present invention.

FIG. 5 is a block diagram showing a configuration of a display processing device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a display processing device according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a display processing device according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a display processing device according to Embodiment 8 of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a conventional radar scan conversion device.

FIG. 10 is a diagram showing an example of display pixels using only sample value matching video of a conventional radar scan conversion device.

FIG. 11 is a diagram showing pixels by a video sequence below a sample value in a conventional radar scan conversion device.

FIG. 12 is a diagram illustrating an example of display pixels on which interpolation processing has been performed by a conventional radar scan conversion device.

FIG. 13 is a diagram showing a display example of moiré.

[Explanation of symbols]

1: pixel coordinate converter, 2: delay circuit, 3, 15, 2
DESCRIPTION OF SYMBOLS 1 ... Adder, 4, 9, 17, 22, 38 ... Multiplexer, 5 ... FIFO, 6 ... Amplitude comparator, 7 ... Timing controller, 8 ... Raster address generator, 10, 24,
25 image memory, 11 output register, 12 parallel / serial converter, 13 D / A converter, 14 monitor, 16 divider, 18, 19, 34, 35 sweep buffer, 20 coordinate comparison Container, 23 ... scan flag
Generator, 26: trail coefficient generator, 27: trail address generator, 28: Y image memory,
29 ... Y + 1 image memory, 30 ... OR circuit, 31 ... Distributor, 32 ... Dual addressable memory, 33 ...
Coordinate and amplitude comparator, 36, 37 ... Comparator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J070 AC01 AC02 AC11 AE04 AH01 AH19 AH31 AH33 AH50 AJ03 AJ04 AJ06 AJ08 AJ14 AK21 AK28 AK39 AK40 BG06

Claims (11)

[Claims] 1. A display processing device for displaying an input image signal on a display device, wherein the coordinates of the image signal are represented by a first X indicating a predetermined pixel position
A first conversion unit for converting into a Y coordinate, a second conversion unit for converting the first XY coordinate into a second XY coordinate indicating a pixel position adjacent to the pixel position, and the first XY Means for writing pixel data indicated by coordinates as interpolation data at a pixel position indicated by the second XY coordinates, and means for storing the pixel data indicated by the first XY coordinates and the interpolation data in an image memory, The display processing device, wherein the display visually displays the image data stored in the image memory. 2. The image processing apparatus according to claim 1, wherein the second conversion unit is configured to output the first XY
The display processing device according to claim 1, wherein the second XY coordinates are obtained by converting the coordinates in the X and / or Y axis directions. 3. A display processing device for displaying an input image signal on a display device, wherein the coordinates of the image signal are represented by a first X indicating a predetermined pixel position
A first conversion unit for converting into a Y coordinate, a second conversion unit for converting the first XY coordinate into a second XY coordinate indicating a pixel position adjacent to the pixel position, and the first XY Third conversion means for converting the coordinates into third XY coordinates indicating a pixel position which is one pixel away from and adjacent to the pixel position; and pixel data indicated by the first XY coordinates and the third XY
Means for calculating average pixel data with pixel data indicated by coordinates; and the second XY using the average pixel data as interpolation data.
Means for writing to a pixel position indicated by coordinates; means for storing pixel data indicated by the first and second XY coordinates and the interpolation data in an image memory, wherein the display is stored in the image memory. A display processing device for visually displaying the displayed image data. 4. The method according to claim 1, wherein the second and third conversion means convert the first XY coordinate in the X and / or Y axis directions to obtain the second and third XY coordinates. The display processing device according to claim 3. 5. A means for storing the XY coordinates after the coordinate conversion, a means for calculating a difference between pixel positions indicated by the stored XY coordinates, and a pixel position requiring interpolation based on the difference. 5. The display processing device according to claim 2, further comprising: means for judging presence / absence of the display. 6. The display processing device according to claim 5, wherein when the difference is 0, the pixel data of a predetermined value or less is invalidated. 7. The image memory is a plurality of parallel memories, and the display displays image data by a PPI scope method. 5. The writing and reading are switched every time the scanning is performed.
The display processing device according to the above. 8. The display according to claim 7, wherein the plurality of image memories are arranged in parallel for the even-numbered Y coordinate and the odd-numbered Y coordinate with respect to the coordinate-transformed XY coordinates. Processing equipment. 9. The image data is distributed to the plurality of image memories in a predetermined order and written therein, and the written image data is read out by simultaneously accessing the plurality of image memories. The display processing device according to claim 7, wherein: 10. The display processing device according to claim 9, wherein the display visually displays the peak value of the read image data. 11. The display processing device according to claim 2, wherein said image memory is a dual addressable memory capable of simultaneously processing writing and reading of image data.