JP2000293402A - Microprocessor and debugging method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the operation speed of a monitor program by holding the base address of an interrupt vector which jumps when an interrupt or exception for moving to the monitor program is generated. SOLUTION: For example, a monitor exception by the execution of a breakpoint instruction or a monitor interrupt by external terminal input is generated in a user program execution state, a return to a debugger execution step is made. At this time, a microprocessor 1 jumps to the specific address corresponding to the monitor interrupt regarding an address set in a monitor interrupt base address register 9 as a base address. The monitor program 6' is assigned to the address and enters a debugger execution step by executing the program from that address. Therefore, when the monitor interrupt is initiated, the place that the executed monitor program fetches can be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a microprocessor and a debugging method for efficiently debugging a user program by executing a monitor program.

[0002]

2. Description of the Related Art A conventional debugging device is disclosed in Japanese Patent Application Laid-Open No. Hei 8-255096.
No. 6,009,045.

FIG. 3 shows a conventional debugging device provided with a conventional microprocessor. This conventional example is generally ROM
This is a debugging system called a monitor.

In FIG. 3, 1 is a microprocessor, 2 is a serial interface, 4 is a host computer, 6 is a monitor program, 7 is a memory, and 8 is an I / O
The / O device and 100 indicate a user target system, respectively.

In this conventional example, a serial interface 2 for connecting to a host computer 4 is prepared on a target system 100, and a monitor program 6 is stored in a memory 7. The microprocessor 1 executes the monitor program 6 and accesses the memory 7 and the like.
Further, the execution of the user program is controlled using a software break instruction or the like.

[0006] The monitor program 6 can be stored by using a ROM emulator or by stopping the microprocessor 1 and using the serial interface 2 and the DMA function.
There is a method such as downloading the monitor program 6 from the host computer to the memory 7.

FIG. 5 shows an operation flowchart of the conventional debug system. In FIG. 5, 11 indicates an initialization step, 12 indicates a debugger execution step, 13 indicates a transition step to a user program, and 14 indicates a user program execution state.

(Initialization Step 11) The monitor reset causes the microprocessor 1 to jump to the address of the monitor reset handler. Here, there is a monitor program 6 at the address of the monitor reset handler, and there is an initialization code of the system as the monitor reset handler. Therefore initialization step 11
Will be executed.

(Debugger execution step 12) The monitor program 6 executes a program for debugging.
This is, for example, setting of an execution start address of a user program, setting of a breakpoint, reading or setting of a memory and a register. Also, it is waiting for a debug command from the user.

(Step 13 for transition to user program)
After completing the setting, the monitor program 6 jumps to the execution start address of the user program, and enters the user program execution state.

In the user program execution state, for example, if a monitor exception occurs due to execution of a breakpoint instruction or a monitor interrupt occurs due to an external terminal input, the process returns to the debugger execution step 12. At this time, microprocessor 1
Jumps to a specific address corresponding to the monitor interrupt or exception address. The monitor program 6 is allocated to the address, and the program is executed from the specific address to reenter the debugger execution step 12.

By executing such steps, the debugging system can debug the user program.

However, in the conventional example, the monitor program 6
Is executed in the memory 7 used by the user, and when the operation of the memory 7 of the user target system 100 is not perfect, the execution of the monitor program 6 itself may not operate stably.

FIG. 4 shows another conventional example of a debugging device. In FIG. 4, 3 indicates a debug interface, and 5 indicates a debug module. The other components are the same as those of FIG. The debug interface 3 is directly connected to the microprocessor 1 by a built-in interface. In addition, the debug module
Connected to 5. The monitor program 6 is arranged in the debug module 5.

The microprocessor 1 accesses the debug interface 3 when receiving a request to execute the monitor program 6, that is, when a monitor interrupt or exception occurs, and the debug interface 3 sends the access to the debug module 5. Fetching the monitor program 6 and the user target system 100
The monitoring result and setting value of the resource are passed.

In this conventional example, the operation of the memory 7 of the user target system 100 described with reference to FIG. 3 is not complete by placing the monitor program 6 in the debug module 5 dedicated to debugging instead of the memory 7 used by the user. Even in this case, the execution of the monitor program 6 can be performed stably. Also, this conventional example performs the same operation as the operation described in the operation flowchart shown in FIG.

However, in this conventional example, since the debug interface 3 is mounted in the microprocessor 1 and the terminals are directly connected to the debug module 5, the number of connected terminals increases and the cost increases, or the number of terminals increases. , The execution speed of the monitor program 6 may be reduced.

[0018]

As described above,
In a conventional debugging system that performs debugging by arranging a monitor program in a memory on a user target system, there is a problem that the operation of the debugging system itself is affected by the influence of the user target system.

In a debug system in which a microprocessor has a debug interface directly connected to a debug module and is configured to execute a monitor program arranged in the debug module, the number of terminals is increased or the number of terminals is increased. There is a problem in that the efficiency of debugging using the debugging system is adversely affected by the delay in execution of the monitor program due to the thinness of the connection path due to the lack of memory.

[0020]

SUMMARY OF THE INVENTION To solve this problem, a microprocessor of the present invention executes a monitor program for debugging, and supplies an external monitor program after monitor reset, and an interface for executing a user program. A means for holding a base address of an interrupt vector that jumps when an interrupt or an exception occurs for shifting to a monitor program.

A debugging method according to the present invention includes the above-mentioned microprocessor, at least a step of performing a system initial diagnosis by a monitor program executed after a monitor reset, and if the initial diagnosis is normal, the monitor program is executed by the microprocessor. Load the memory into a directly accessible memory, and set the base address of the monitor interrupt to the base address of the monitor interrupt handler in the monitor program loaded into the memory.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram of a debug system according to an embodiment of the present invention. In FIG. 1, 1 is
Microprocessor, 3 is a debug interface, 5 is a debug module, 6, 6 'is a monitor program, 7 is a memory, 8 is an I / O device, 9 is a monitor interrupt base register, 10 is a debug interface 3 and the connection line of the debug module are shown.

The user target system 100 mainly includes a microprocessor 1, a memory 7, and an I / O 8. The microprocessor 1 executes a user program on the memory 7 to access the memory 7 and the I / O 8. It is a system that works by doing

The microprocessor 1 has a built-in debug interface 3 and a specific address space (for example, 0xfffff000-0xffffffff. 0x represents a hexadecimal number; the same applies hereinafter) is allocated to the debug interface 3. The debug interface 3 is connected to an external debug module 5, and the microprocessor 1 can access the debug module 5 via the debug interface 3.

The microprocessor 1 handles two types of interrupts or exceptions. One is the monitor interrupt or monitor exception required for debugging, and the other is
User interrupt or user exception required by the user program. Here, since it is not necessary to distinguish between an exception and an interrupt, hereinafter, the term “interrupt” includes the exception. A typical example of a monitor interrupt is an interrupt generated by execution of a breakpoint instruction. A typical example of a user interrupt is
This is an interrupt from an I / O device such as a timer.

When a monitor interrupt occurs, the processor
1 jumps to the base address of the monitor interrupt vector stored in the monitor interrupt base register 9. Then, the monitor program 6 or 6 'is executed. The monitor program jumps to the user program by performing operations required for debugging, for example, setting a start address of the user program, setting / reading data of the user program, setting a break point, and the like. This makes it possible to debug the user program.

The operation of the debug system thus configured will be described with reference to FIG. FIG. 2 is an operation flowchart of the debug system. In FIG. 2, 11 is an initialization step, 12 is a debugger execution step by a monitor program, 13 is a transition step to a user program, 14 is a user program execution state,
Reference numeral 15 denotes a system initial diagnosis step, 16 denotes a step of loading the monitor program 6 into the memory 7, and 17 denotes a step of changing the base address of the monitor interrupt.

(Initialization Step 11) By the debug reset, the monitor interrupt base register 9 is initialized to, for example, 0xfffff000 to indicate the address of the monitor interrupt vector of the monitor program 6 in the debug module 5 via the debug interface 3. Is done. Therefore, the microprocessor 1 jumps to the address 0xfffff000 of the debug reset handler indicated by the monitor interrupt base register 9. Here, the monitor program 6 in the debug module 5 is located at the address 0xfffff000 of the debug reset handler, and the system initialization code exists as the debug reset handler there. Therefore, an initialization step 11 is performed.

(System Initial Diagnosis Step 15) The monitor program 6 performs an initial diagnosis of the user target system 100. Here, the access to the memory 7 is diagnosed.
If the initial diagnosis step 15 is NG, for example,
When an access timeout or the like is detected due to a malfunction of the user target system 100, for example, the monitor interrupt base register 9 points to the debug module 5, so that the access timeout processing handler in the monitor program 6 operates, and FIG. Go to the debugger execution step 12 (in the NG direction of 2).

If the system initial diagnosis is OK, the process proceeds to the step of loading the monitor program 6 into the memory 7.

(Step 16 for loading the monitor program into the memory) The monitor program 6 downloads a monitor program 6 'having a function equivalent to the monitor program 6 to a specific address on the memory 7, for example, 0x8000f000.

(Step 17 for Changing Base Address of Monitor Interrupt) Next, the monitor program 6 sets the base address 0x8000f000 of the monitor interrupt handler in the downloaded monitor program 6 'in the monitor interrupt base register 9, Debugger execution step 1
Move to 2.

(Debugger execution step 12) The monitor program 6 executes a program for debugging. This is, for example, setting of an execution start address of a user program, setting of a breakpoint, reading or setting of a memory and a register. Also, it is waiting for a debug command from the user.

(Step 13 for transition to user program)
After completing the setting, the monitor program 6 jumps to the execution start address of the user program, and enters the user program execution state.

In the user program execution state, for example, when a monitor exception occurs due to execution of a breakpoint instruction or a monitor interrupt occurs due to an external terminal input, the process returns to the debugger execution step 12. At this time, microprocessor 1
Jumps to a specific address corresponding to the monitor interrupt using the address set in the monitor interrupt base address register 9 as the base address. The monitor program 6 'is allocated to the address, and the debugger execution step is started by executing the program from the specific address.

Therefore, the memory 7 of the monitor program 6
After loading, the monitor interrupt base register 9 contains
According to the set address, it is possible to change a fetch location of a monitor program to be executed when a monitor interrupt occurs. Here, after the monitor reset, the monitor program 6 is executed via the connection line 10 which is relatively slow but hardly influenced by the user target system 100, and the access to the memory 7 is confirmed by the system initial diagnosis step 15. Later, connection line 10
Monitor program 6 'using a faster memory bus
Can be performed.

From the viewpoint of the reliability of the debugging system, the setting of the monitor interrupt base register 9 should be changed only in the execution state of the monitor program.

In executing the monitor program,
In order to eliminate the influence of the operation of the user program, if a specific range from the value set in the monitor interrupt base register 9 is made inaccessible from the user program,
Improve the reliability of the debugging system. As a method of making access inaccessible, for example, a monitor exception may be generated. Further, there may be a register for setting a range in which access is disabled.

In the description of the present invention, the monitor program 6 'is downloaded to the memory 7 used by the user. However, the memory may be any memory that can be accessed from the microprocessor and is not limited to the present invention. Absent.

As described above, after the monitor is reset, the monitor program in the debug module is executed via the highly reliable debug interface, the system initial diagnosis step, and the monitor program is downloaded to the memory in the user target system. Steps to
By executing the step of changing the base address of the monitor interrupt, the subsequent debugger execution is performed by fetching the monitor program from the diagnosed memory in the user target system, thereby causing the memory system of the user target system to fail. Even if the system is stable, debugging can be performed. If the memory system of the user target system is stable, the monitor program can be executed at a high speed, and the response speed to the user can be increased. Debugging efficiency can be maintained.

[0042]

When the monitor program is started, the monitor program is supplied from the stable interface means to operate the monitor program, thereby increasing the reliability of debugging. After the initial system diagnosis, the monitor program is loaded on the memory. By operating, the operation speed of the monitor program can be improved, which is extremely effective.

[Brief description of the drawings]

FIG. 1 is a block diagram of a debugging system according to a first embodiment of the present invention;

FIG. 2 is an operation flowchart of the debug system according to the first embodiment of the present invention shown in FIG. 1;

FIG. 3 is a schematic block diagram of main parts constituting a conventional debugging system.

FIG. 4 is a schematic block diagram of main parts constituting a conventional debugging system.

FIG. 5 is an operation flowchart of a conventional debugging system.

[Explanation of symbols]

 1 Microprocessor 3 Debug interface 9 Monitor interrupt base register

Claims (3)

[Claims] An interface means for executing a monitor program for debugging and supplying the monitor program from the outside after a monitor reset, and when an interrupt or an exception for shifting to the monitor program occurs during execution of a user program. A microprocessor comprising means for holding a base address of an interrupt vector to be jumped. 2. The system according to claim 1, wherein at least a step of performing a system initial diagnosis by a monitor program executed after a monitor reset, and if the initial diagnosis is normal, the monitor program can be directly accessed by the microprocessor. A debugging method comprising the steps of: loading a memory into a memory; and setting a base address of a monitor interrupt to a base address of a monitor interrupt handler in a monitor program loaded into the memory. 3. The microprocessor according to claim 1, wherein an exception occurs when a user accesses a specified memory area using the processing start address of the interrupt as a base address.