JP2000294741A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the leakage current of a capacitor with a capacitance insulating film consisting of a ceramic thin film with perovskite structure, and to enhance a breakdown voltage. SOLUTION: On a foundation insulating film 12 being formed on a semiconductor substrate 11, a ferro-electric capacitor is formed, where the ferro-electric capacitor is composed of a lower electrode 13A, a ceramic capacitance film 14A consisting of a ferroelectric, and an upper electrode 15A. An interlayer insulation 16 is formed on the semiconductor substrate 11 so that the ferro- electric capacitor is covered, and electrode wiring 17 is formed on the interlayer insulation 16. A relationship of L>=2D is established between length L of the surface of the ceramic capacitance film 14A existing between the intersection of the side surface of the upper electrode 15A and the upper surface of the ceramic capacitance film 14A and the intersection of the side surface of the ceramic capacitance film 14A and the upper surface of the lower electrode 13A, and thickness D of the ceramic capacitance film 14A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a method of forming a capacitor on a semiconductor substrate having a ceramic thin film having a perovskite structure known as a material having a very high dielectric constant together with a transistor and a resistor. The present invention relates to an improvement in the structure of a capacitor in a semiconductor integrated circuit device in which a capacitor used as an insulating film is integrated.

[0002]

2. Description of the Related Art With the advance of the information and communication field, high-speed processing of large-capacity data has been demanded.
2. Description of the Related Art High integration of semiconductor integrated circuits such as semiconductor memories has been progressing. Further, for the purpose of downsizing and cost reduction of information and communication equipment, reduction in chip area and reduction in the number of components due to high integration are being promoted.

Under these circumstances, in recent years, techniques for forming a capacitor on a semiconductor integrated circuit using a ceramic material having a perovskite structure (for example, barium strontium titanate, lead titanate, etc.) have been actively studied. ing. Generally, a capacitor insulating film made of a ceramic thin film formed of the above-described ceramic material has a high dielectric constant, and a capacitor insulating film made of a silicon oxide film or a silicon nitride film formed in a conventional integrated circuit device. It has a dielectric constant several tens to several hundreds times that of the film.

[0004] By arranging a capacitor using such a capacitor insulating film made of a ceramic thin film, the area occupied by the capacitor in the semiconductor integrated circuit device can be reduced to several tenths to one hundredth of a conventional one. Therefore, high integration of the semiconductor integrated circuit device can be realized.

Further, when a capacitor insulating film is formed using a ferroelectric ceramic (hereinafter referred to as a ferroelectric) having a property that spontaneous polarization remains even when an applied electric field is removed, stored contents are maintained even when the power is turned off. A nonvolatile memory that does not disappear can be realized.

Hereinafter, a conventional semiconductor integrated circuit device and a method of manufacturing the same will be described with reference to the drawings.

FIG. 11 shows a cross-sectional structure of a conventional semiconductor integrated circuit device. As shown in FIG.
1 a base insulating film 5 of a capacitor made of a silicon oxide film
2 are formed, and a capacitor is formed on the base insulating film 52, which is composed of a lower electrode 53A made of platinum, a capacitive insulating film 54A made of a ceramic thin film having a perovskite structure, and an upper electrode 55A made of platinum. ing. Further, an interlayer insulating film 56 made of a silicon oxide film is formed on the semiconductor substrate 51 so as to cover the capacitor, and an electrode wiring 57 is formed on the interlayer insulating film 56, and the lower electrode 53A and the upper electrode Electrode 55A and electrode wiring 5
7 is connected via an opening formed in the interlayer insulating film 56.

Hereinafter, a method for manufacturing the conventional semiconductor integrated circuit device will be described with reference to FIG.

First, as shown in FIG. 12A, a base insulating film 52 of a capacitor is deposited on a semiconductor substrate 51, and then, as shown in FIG. A first metal layer 53 serving as a lower electrode of the capacitor, a ceramic thin film 54 serving as a capacitor insulating film having a perovskite structure, and a second metal layer 55 serving as an upper electrode of the capacitor are sequentially formed.

Next, as shown in FIG. 12C, the second metal layer 55 and the ceramic thin film 54 are formed by ion milling or RIE using a photoresist mask.
After the upper electrode 55A and the capacitive insulating film 54A are formed by etching the
As shown in (1), the lower electrode 53A is formed by etching the first metal layer 53.

Next, as shown in FIG. 1E, after depositing an interlayer insulating film 56, an opening is formed in a predetermined region of the interlayer insulating film 56. Thereafter, as shown in FIG. 12F, when an electrode wiring 57 is formed on the interlayer insulating film 56,
Lower electrode 53A, capacitance insulating film 54A, and upper electrode 55A
Is completed.

In the above-described structure, the capacitor including the upper electrode 55A, the capacitor insulating film 54A and the lower electrode 53A is formed by etching using ion milling or RIE. Since the 55 and the ceramic thin film 54 are continuously etched by using the same mask, the peripheral edge of the upper electrode 55A and the peripheral edge of the capacitive insulating film 54A have the same structure.

[0013]

By the way, when a voltage is applied to the capacitor, the path of the leakage current is a crystal grain constituting the capacitive insulating film 54A or a first grain passing through the grain boundary thereof.
And a second path passing through the peripheral end (side surface) of the capacitive insulating film 54A. The withstand voltage of the capacitor is determined by the path having the larger leakage current among the two paths.

On the side surface of the capacitive insulating film 54A, the crystal structure is disturbed at the time of etching, and when a silicon oxide film or a silicon nitride film is used as the interlayer insulating film 56, a silane gas, a hydrogen gas or the like is deposited at the time of deposition. Since it is directly exposed to a reducing atmosphere and undergoes a reduction reaction to have oxygen vacancies, it is in a state in which a leak current is very easy to flow.

In the capacitor having the conventional structure,
Since the peripheral edge of the upper electrode 55A coincides with the peripheral edge of the capacitive insulating film 54A, a large amount of leak current flows through a path passing through the side surface of the capacitive insulating film 54A, and the withstand voltage of the capacitor is reduced by the capacitance insulation. Since it is governed by the path through the side surface of the film 54A, there is a problem that the withstand voltage of the capacitor is greatly reduced.

Therefore, as shown in, for example, Japanese Patent Application Laid-Open No. 2-229661, the surfaces of the capacitor insulating film and the electrode wiring are made to be S
Although a method of improving reliability by coating with iN has been proposed, according to this structure, since formation of a SiN film is indispensable, it cannot be said that this method is necessarily excellent in workability.

Further, as disclosed in, for example, Japanese Patent Application Laid-Open No. 4-356958, there has been proposed a device in which a capacitor insulating film is formed so as to cover a lower electrode to take measures against leakage. Since it is necessary to cover the entire lower electrode with the insulating film, it cannot be applied to the case where the electrode wiring is formed directly on the lower electrode.

An object of the present invention is to solve the above-mentioned problem and to suppress the generation of a leak current through the side surface of a capacitive insulating film made of a ceramic material, thereby greatly reducing the leak current of the entire capacitor. An object of the present invention is to improve the withstand voltage of a capacitor and eliminate the influence of the side surface of the ceramic capacitance film on the withstand voltage of the capacitor, thereby improving the yield and reliability of the semiconductor integrated circuit device.

[0019]

In order to achieve the above object, the invention according to claims 1 to 5 is directed to a method of forming a crystal film or a crystal grain constituting a capacitance film in a path of a leakage current when a voltage is applied to a capacitor. By making the second path passing through the side surface of the capacitor film longer than the first path passing through the grain boundary, the withstand voltage of the capacitor is determined by the first path.

[0020] Specifically, a solution taken by the invention of claim 1 is a ceramic capacitor film comprising a semiconductor substrate, a lower electrode sequentially formed on one main surface of the semiconductor substrate, and a ceramic thin film having a perovskite structure. And a side surface of the upper electrode is located inside a side surface of the ceramic capacitor film, and a side surface of the ceramic capacitor film is located on the lower side. It is located on the inner side than the side surface of the electrode, and exists between the intersection of the side surface of the upper electrode and the upper surface of the ceramic capacitance film and the intersection of the side surface of the ceramic capacitance film and the upper surface of the lower electrode. The length L of the surface of the ceramic capacitance film and the thickness D of the ceramic capacitance film
And the relationship of L ≧ 2D is established between them.

[0021] The solution means specifically taken by the invention of claim 2
Are sequentially formed on one main surface of the semiconductor substrate.
Formed lower electrode, ceramic with perovskite structure
Composed of a ceramic capacitor film consisting of
Semiconductor integrated circuit device having a multilayer capacitor
It is intended to be applied to a part of the peripheral portion of the multilayer capacitor.
In this case, the side surface of the upper electrode is the ceramic capacitor film.
The ceramic is located inside the side of the
The side surface of the capacitance film is located inside the side surface of the lower electrode.
Between the side surface of the upper electrode and the ceramic capacitor film.
Intersection with the upper surface, the side surface of the ceramic capacitor film, and the lower portion
The ceramic volume present between the intersection with the top surface of the electrode;
Length of film surface L₁And the thickness of the ceramic capacitance film
L between D₁≧ 2D holds, and the laminated capacity
In the remaining area of the periphery of the sita, the upper electrode
The side surface is the same as the side surface of the ceramic capacitor film or the side surface of the ceramic capacitor film.
It is located inside the side of the mic capacitance film,
The periphery of the ceramic capacitor film is closer to the side surface of the lower electrode.
Provided on one main surface of the semiconductor substrate outside
The side surface of the ceramic capacitor film and the semiconductor substrate
Point of intersection with one main surface of the semiconductor device, the side surface of the lower electrode, and the semiconductor substrate.
The ceramic container present between the intersection with one principal surface of the plate;
Length of film surface L_TwoAnd the thickness of the ceramic capacitance film
L between D _Two≧ D
It is.

According to a third aspect of the present invention, in the configuration of the first or second aspect, an intersection between the side surface of the upper electrode and the upper surface of the ceramic capacitance film, and an intersection between the side surface of the ceramic capacitance film and the upper surface of the lower electrode are provided. The surface of the ceramic capacitance film existing between the first region between the side surface of the upper electrode and the side surface of the ceramic capacitance film on the surface of the ceramic capacitance film, and the side surface of the ceramic capacitance film The second
Is added.

In a fourth aspect of the present invention, a method of manufacturing a semiconductor integrated circuit device includes the steps of: depositing a first metal film on one main surface of a semiconductor substrate; Patterning a metal film to form a lower electrode, depositing a ceramic thin film having a perovskite structure on the lower electrode, and forming the ceramic thin film such that a side surface of the ceramic thin film is larger than a side surface of the lower electrode. Forming a ceramic capacitor film by patterning to be located inside; depositing a second metal film on the ceramic capacitor film; and forming the second metal film on the second metal film. Is located inside the side surface of the ceramic capacitance film, and the intersection of the side surface of the second metal film and the upper surface of the ceramic capacitance film, the side surface of the ceramic capacitance film, and the upper surface of the lower electrode And an upper electrode is formed by patterning such that a relationship of L ≧ 2D is established between the length L of the surface of the ceramic capacitance film existing between the intersections of the two and the thickness D of the ceramic capacitance film. And a process.

[0024] Specifically, according to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising the steps of: depositing a first metal film on one main surface of a semiconductor substrate; A step of forming a lower electrode by patterning a metal film, a step of depositing a ceramic thin film having a perovskite structure on the lower electrode, and the step of depositing the ceramic thin film in a partial region of a peripheral portion of the ceramic thin film. The side surface of the ceramic thin film is located inside the side surface of the lower electrode, and the peripheral portion of the ceramic thin film remains on the semiconductor substrate in the remaining region of the peripheral portion of the ceramic thin film. Of the surface of the ceramic thin film existing between the intersection of the side surface of the semiconductor substrate and the intersection of the side surface of the lower electrode and the one main surface of the semiconductor substrate. Is a L _2, a step of forming a ceramic capacitor film is patterned such that the relationship of L ₂ ≧ D is satisfied between the thickness D of said ceramic capacity film, the second on the ceramic capacity film Depositing a metal film;
The second metal film is formed such that a side surface of the second metal film is located inside a side surface of the ceramic capacitor film, and a part of a peripheral portion of the ceramic thin film is formed of the second metal film. The side surface of the film is located inside the side surface of the ceramic capacitance film, and the intersection of the side surface of the second metal film and the upper surface of the ceramic capacitance film, the side surface of the ceramic capacitance film, and the upper surface of the lower electrode. An upper electrode is formed by patterning such that the relationship of L ₁ ≧ 2D is established between the length L ₁ of the surface of the ceramic capacitance film existing between the intersection and the thickness D of the ceramic capacitance film. And a step of performing the above.

According to a sixth aspect of the present invention, the number of steps is reduced by forming the ceramic capacitor film and the lower electrode by one patterning.

[0026] In accordance with a sixth aspect of the present invention, a method of manufacturing a semiconductor integrated circuit device includes the steps of sequentially depositing a first metal film, a ceramic thin film, and a second metal film on a semiconductor substrate. Forming a top electrode by patterning the second metal film so that a lower electrode lead-out region in the ceramic thin film is exposed; and forming a ceramic film by simultaneously patterning the ceramic thin film and the first metal film. Forming a capacitor film and a lower electrode, depositing an insulating film on the entire surface of the semiconductor substrate, etching the insulating film and the ceramic capacitor film, and drawing an upper electrode on the insulating film. And forming a lower electrode lead-out opening in the insulating film and the ceramic capacitor film.

[0027]

According to the first aspect of the present invention, the length of the surface of the ceramic capacitance film existing between the intersection of the side surface of the upper electrode and the upper surface of the ceramic capacitance film and the intersection of the side surface of the ceramic capacitance film and the upper surface of the lower electrode. Since the relationship of L ≧ 2D is established between the height L and the thickness D of the ceramic capacitance film, the length of the region between the side surface of the upper electrode and the side surface of the ceramic capacitance film on the surface of the ceramic capacitance film. Is larger than the thickness of the ceramic capacitance film, the path of the current flowing through the surface and the side surface of the ceramic capacitance film is longer than the path of the current flowing through the inside of the ceramic capacitance film.

According to the second aspect of the present invention, in a part of the peripheral portion of the multilayer capacitor, as in the first aspect, the gap between the side surface of the upper electrode and the side surface of the ceramic capacitor film on the surface of the ceramic capacitor film is formed. Is longer than the thickness of the ceramic capacitor film. In the remaining region of the peripheral portion of the multilayer capacitor, there exists between the intersection of the side surface of the ceramic capacitor film and one main surface of the semiconductor substrate and the intersection of the side surface of the lower electrode and one main surface of the semiconductor substrate. The length L ₂ of the surface of the ceramic capacitance film and the thickness D of the ceramic capacitance film
L ₂ ≧ D, the length of the region between the side surface of the ceramic capacitor film and the side surface of the lower electrode on the lower surface of the ceramic capacitor film is larger than the thickness of the ceramic capacitor film. .

According to the structure of the third aspect, the length of the region between the side surface of the upper electrode and the side surface of the ceramic capacitor film on the surface of the ceramic capacitor film is surely larger than the thickness of the ceramic capacitor film.

According to the structure of claim 4, the second metal film is formed by:
The length L of the surface of the ceramic capacitance film existing between the intersection of the side surface of the second metal film and the upper surface of the ceramic capacitance film and the intersection of the side surface of the ceramic capacitance film and the upper surface of the lower electrode;
Since the upper electrode is formed by patterning so as to satisfy the relationship of L ≧ 2D with the thickness D of the ceramic capacitor film, the intersection of the side surface of the upper electrode with the upper surface of the ceramic capacitor film and the side surface of the ceramic capacitor film. The relationship of L ≧ 2D is established between the length L of the surface of the ceramic capacitance film existing between the point of intersection with the upper surface of the lower electrode and the thickness D of the ceramic capacitance film.

According to the fifth aspect of the present invention, the ceramic thin film is provided in the remaining region of the peripheral portion of the ceramic thin film.
The length L ₂ of the surface of the ceramic thin film which is present between the intersection of the side surface and one main surface of the semiconductor substrate of the intersection and the lower electrode between the side surface and one main surface of the semiconductor substrate of the ceramic thin film, a ceramic capacitor film Forming a ceramic capacitor film by patterning such that a relationship of L ₂ ≧ D is established with the thickness D; and forming a second metal film on a part of the peripheral portion of the ceramic thin film in the second region. 2, the length L ₁ of the surface of the ceramic capacitor film existing between the intersection of the side surface of the metal film and the upper surface of the ceramic capacitor film and the intersection of the side surface of the ceramic capacitor film and the upper surface of the lower electrode; L ₁ between the thickness D
A step of forming an upper electrode by patterning such that a relationship of ≧ 2D is established. Therefore, in a part of the peripheral portion of the multilayer capacitor, the side surface of the upper electrode and the upper surface of the ceramic capacitance film are The relationship of L ₁ ≧ 2D between the length L ₁ of the surface of the ceramic capacitance film existing between the intersection and the intersection of the side surface of the ceramic capacitance film and the upper surface of the lower electrode, and the thickness D of the ceramic capacitance film. Is established, and in the remaining region of the peripheral portion of the multilayer capacitor, the intersection between the side surface of the ceramic capacitor film and one main surface of the semiconductor substrate and the intersection of the lower electrode side surface and the one main surface of the semiconductor substrate is formed. The relationship of L ₂ ≧ D is established between the length L ₂ of the surface of the ceramic capacitance film existing in the above and the thickness D of the ceramic capacitance film.

According to the structure of claim 6, the second metal film is formed by:
After patterning so that the lower electrode lead-out region in the ceramic thin film is exposed to form an upper electrode, the ceramic thin film and the first metal film are simultaneously patterned to form a ceramic capacitor film and a lower electrode, so that one patterning is performed. Thereby, a ceramic thin film and a first metal film can be formed.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to one embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a capacitor structure of a semiconductor integrated circuit device according to a first embodiment of the present invention. In the first embodiment, a ceramic capacitor made of a ferroelectric thin film is formed on a semiconductor substrate. This is a structure in which a capacitor having a film is formed.

Semiconductor substrate 1 made of semi-insulating GaAs
1, a lower insulating film 12 of a capacitor made of a silicon oxide film is formed. On the lower insulating film 12, a lower electrode 13A made of platinum and a ferroelectric material, for example, a barium strontium titanate film (hereinafter, referred to as a barium strontium titanate film). A ferroelectric capacitor composed of a ceramic capacitor film 14A having a thickness of 0.2 μm and a top electrode 15A made of platinum is formed. On the semiconductor substrate 11, an interlayer insulating film 16 made of a silicon oxide film is formed so as to cover the ferroelectric capacitor. On the interlayer insulating film 16, an electrode wiring 17 is formed. Upper electrode 1
5A and the electrode wiring 17 are connected via an opening formed in the interlayer insulating film 16.

As a feature of the first embodiment, the upper electrode 15A
Intersection A between the side surface of the ceramic capacitor film 14A and the side surface of
The length of the surface of the ceramic capacitance film 14A existing between the intersection B between the side surface of the ceramic capacitance film 14A and the upper surface of the lower electrode 13A is 0.7 μm, and the side wall of the upper electrode 15A is It is located 0.5 μm inside the side wall.

Hereinafter, a first method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG.
A base insulating film 12 of a capacitor made of a silicon oxide film is formed on a semiconductor substrate 11 made of a silicon oxide film by a CVD method.
Thereafter, as shown in FIG. 2B, a photoresist 18 having a predetermined region opened is formed on the base insulating film 12, and then the first platinum film 1 is formed on the entire surface of the semiconductor substrate 11.
3 is deposited.

Next, as shown in FIG. 2C, the first platinum film 13 on the photoresist 18 is lifted off using an organic solvent to form a lower electrode 13A made of platinum. Next, a solution obtained by diluting a metal alkoxide of barium, strontium, and titanium with an organic solvent is spin-coated on the GaAs substrate 11, and then subjected to a high-temperature treatment at 700 ° C., as shown in FIG. , A ferroelectric film having a thickness of 0.2 μm (hereinafter referred to as a BST film) 14
To form

Next, using a hydrofluoric acid-based etching solution, BS
By etching the T film 14, as shown in FIG. 3A, the lower electrode 13A is formed on the lower electrode 13A.
A ceramic capacitor film 14A is formed in a region inside A. Next, by the same steps as in FIGS. 2B and 2C,
After forming a second platinum film (not shown), the second platinum film is lifted off, and as shown in FIG. 3B, the ceramic capacitance film on the ceramic capacitance film 14A is formed. An upper electrode 15A is formed in a region inside the upper electrode 14A such that the side surface of the upper electrode 15A is located 0.5 μm inside the side surface of the ceramic capacitor film 14A.

Next, as shown in FIG. 3C, after an interlayer insulating film 16 made of a silicon oxide film is deposited by the CVD method, as shown in FIG. Thereafter, an opening is formed, and then an electrode wiring 17 is formed on the interlayer insulating film 16. Next, if necessary, a protective film (not shown) made of a silicon nitride film is formed on the electrode wiring 17, and a bonding pad portion is opened in the protective film.

The operation of the capacitor of the semiconductor integrated circuit device according to the first embodiment will be described below with reference to the drawings.

FIG. 4 is a diagram showing a cross-sectional structure of a peripheral portion of a capacitor of the semiconductor integrated circuit device according to the first embodiment, where an intersection between a side surface of an upper electrode 15A and one main surface of a ceramic capacitance film 14A. (A) and the ceramic capacitance film 14A
Between the length (L) of the surface of the ceramic capacitance film 14A existing between the side surface of the ceramic capacitor film 14A and the intersection (B) of one main surface of the lower electrode 13A, and the thickness (D) of the ceramic capacitance film 14A. Shows a case where the relationship of L ≧ 2D is established.

In the capacitor structure of the semiconductor integrated circuit device according to the first embodiment, as the leakage current path of the capacitor, the crystal grains and the grain boundaries of the ceramic capacitance film 14A between the upper electrode 15A and the lower electrode 13A are used. First pass
(For example, EF), the intersection A between the side surface of the upper electrode 15A and one main surface of the ceramic capacitance film 14A, and the intersection B between the side surface of the ceramic capacitance film 14A and one main surface of the lower electrode 13A. There is a second path (A-C-B) passing through the surface of the ceramic capacitance film 14A existing between them. In the second path (ACB), the ceramic capacitance film 14
The leakage current is very easy to flow at the side (CB) of A, but even if this part is short-circuited,
Since the distance (L) between B and B is at least twice the thickness (D) of the ceramic capacitance film 14A, the distance between A and C is CB
Between the two routes (A-C-
The leakage current passing through B) is equal to or less than the leakage current passing through the first path (E-F). Therefore, the influence of the side surface of the ceramic capacitance film 14A, which has conventionally caused a large amount of leakage current, can be removed, so that the leakage current can be significantly reduced. In addition, the withstand voltage of the capacitor is determined by the first path (E-F), so that it is significantly improved, so that the yield and reliability of the semiconductor integrated circuit device are improved.

Hereinafter, the above contents will be conceptually described with reference to FIGS. 5 (a) and 5 (b). FIG. 5A is a cross-sectional view of the conventional capacitor structure, and FIG. 5B is a cross-sectional view of the capacitor structure of the first embodiment. Ceramic capacitance film 1
4A are shown in FIGS. 5 (a) and 5 (b).
As shown in (1), since the crystal grains are cut during etching, the defect levels are large, leak current easily flows, and the reliability tends to easily deteriorate. Therefore, FIG.
In the conventional structure shown in (a), since the side surface of the upper electrode 15A is flush with the side surface of the ceramic capacitance film 14A, a large amount of leak current easily flows through the side surface of the ceramic capacitance film 14A. On the other hand, in the structure of the first embodiment shown in FIG. 5B, the side surface of the upper electrode 15A is larger than the side surface of the ceramic capacitance film 14A.
A region (a portion shown by b) between the side surface of the upper electrode 15A and a side surface of the lower electrode 13A on the surface of the ceramic capacitor film 14A by a distance (a portion shown by b) which is equal to or more than the thickness of A. Is a region where crystallinity is complete, and the ceramic capacitor film 14A is easy to leak current.
Can be regarded as equivalent to a region between the upper electrode 15A and the lower electrode 13A in the inside. Therefore, the influence of the side portion of the ceramic capacitance film 14A on the leakage current can be avoided, and high reliability can be obtained.

FIG. 6 shows the leakage current and breakdown voltage characteristics of the capacitor of the semiconductor integrated circuit device according to the first embodiment. FIG. 6 also shows the leakage current and breakdown voltage characteristics of the capacitor of the conventional semiconductor integrated circuit device for comparison. As shown in FIG. 6, the leak current of the first embodiment is reduced to about one thousandth as compared with the conventional example.

FIG. 7 shows a change in leakage current (hereinafter referred to as TDD) when a DC voltage of 10 V is continuously applied to the capacitor of the semiconductor integrated circuit device of the first embodiment at 125 ° C.
B characteristic) and the TDDB characteristic of the capacitor of the conventional semiconductor integrated circuit device. While the capacitor of the conventional semiconductor integrated circuit device is destroyed in several tens of hours, the capacitor of the semiconductor integrated circuit device of the first embodiment has only one capacitor.
It operates stably for up to 000 hours, and has a practical withstand voltage of 10 V or more.

As described above, the intersection (A) between the side surface of the upper electrode 15A and the upper surface of the ceramic capacitance film 14A and the intersection (B) between the side surface of the ceramic capacitance film 14A and the upper surface of the lower electrode 13A. Existing ceramic capacitance film 14A
L ≧ 2D is established between the length (L) of the surface of the ceramic capacitor film 14A and the thickness (D) of the ceramic capacitor film 14A, so that the influence of the leak path passing through the side wall of the ceramic capacitor film 14A is eliminated. Therefore, the breakdown voltage of the capacitor is improved.

In the first manufacturing method described above, the capacitor is formed by forming the lower electrode 13A, the ceramic capacitor film 14A and the upper electrode 15A only in predetermined regions by using a lift-off method or a wet etching method. Alternatively, a first platinum film, a ceramic thin film, and a second platinum film are sequentially deposited on the entire surface of the semiconductor substrate 11, and then the layers are sequentially etched by using an ion milling method or an RIE method. Even if a capacitor having the same structure as described above is formed, exactly the same effect can be obtained.

Further, in the above-mentioned first manufacturing method,
Although the thermal decomposition method of the metal alkoxide is used for depositing the BST film 14, the same effect can be obtained by using any other deposition method such as a sputtering method or an MOCVD method instead.

When the thermal decomposition method of metal alkoxide is used for depositing the BST film 14, pinholes or microcracks are generated in the BST film 14 due to stress caused by shrinkage of the film due to the thermal decomposition, and the breakdown voltage is deteriorated. Easy to get up. In this case, the second step in which the BST film 14 is formed by the following process
Is very effective in improving the breakdown voltage.

Hereinafter, the BST film 1 in the second manufacturing method will be described.
The formation process of No. 4 will be described. That is, after spin-coating a solution obtained by diluting a metal alkoxide with an organic solvent, the organic solvent is evaporated to deposit a metal alkoxide film. Thereafter, the metal alkoxide film is etched using a hydrofluoric acid-based etchant to leave the metal alkoxide film only in a necessary region, and then a BST film 14 is formed by a high-temperature treatment at 700 ° C.

According to the second manufacturing method, since the metal alkoxide film is previously formed in the minute region, the stress due to the contraction of the metal alkoxide film due to the thermal decomposition during the high-temperature treatment can be greatly reduced. Thus, pinholes and microcracks in the obtained BST film 14 can be reduced.

The leakage current of the capacitor having the ceramic capacitance film 14A formed by the second manufacturing method is equal to the first leakage current.
The leakage current of the capacitor having the ceramic capacitor film 14A formed by the method described in the above was reduced to one tenth. Regarding the TDDB characteristics at 125 ° C. and 15 V, the capacitor formed by the first manufacturing method was broken in several hundred hours, whereas the capacitor formed by the second manufacturing method operated stably after 1000 hours. And
It was confirmed that the withstand voltage was further improved.

The structure of the present invention is indispensable for improving the withstand voltage of the capacitor by the second manufacturing method. In the conventional structure, since the withstand voltage of the capacitor is determined by the second path passing through the side wall of the ceramic capacitance film, the effect of reducing pinholes and microcracks in the ceramic capacitance film does not appear.

FIG. 8 is a sectional view showing a capacitor structure of a semiconductor integrated circuit device according to a second embodiment of the present invention.

Semiconductor substrate 2 made of semi-insulating GaAs
1, a lower insulating film 22 of a capacitor made of a silicon oxide film is formed, and a lower electrode 23A made of platinum and a ceramic capacitor film 24A made of a ferroelectric material having a thickness of 0.2 μm are formed on the base insulating film 22. A ferroelectric capacitor composed of an upper electrode 25A made of platinum is formed, an interlayer insulating film 26 made of a silicon oxide film is formed so as to cover the ferroelectric capacitor, and an electrode is formed on the interlayer insulating film 26. Wiring 2
7 are formed, and the lower electrode 23A and the upper electrode 25A are connected to the electrode wiring 27 via an opening formed in the interlayer insulating film 26.

As a feature of the second embodiment, in a part of the peripheral portion of the capacitor (region indicated by x),
Surface of the ceramic capacitance film 24A existing between the intersection (A) between the side surface of the upper electrode 25A and the upper surface of the ceramic capacitance film 24A and the intersection (B) between the side surface of the ceramic capacitance film 24A and the upper surface of the lower electrode 23A. Is 0.7 μm, but in the remaining region (region indicated by y) of the peripheral portion of the capacitor, the intersection (C) between the side surface of the ceramic capacitance film 24A and the main surface of the semiconductor substrate 21 is formed. , Lower electrode 23A
The length of the surface of the ceramic capacitor film 24A existing between the side surface of the ceramic capacitor film 24A and the intersection (D) of the main surface of the semiconductor substrate 21 is 0.7
μm.

In the second embodiment, in a part of the peripheral portion of the capacitor, similar to the first embodiment,
Surface of the ceramic capacitance film 24A existing between the intersection (A) between the side surface of the upper electrode 25A and the upper surface of the ceramic capacitance film 24A and the intersection (B) between the side surface of the ceramic capacitance film 24A and the upper surface of the lower electrode 23A. the length of the (L _1), together with the relationship of L ₁ ≧ 2D between the thickness of the ceramic capacity film 24A (D) is satisfied, in the region of the rest of the peripheral portion of the capacitor upper electrode The side surface of 25A is located on the same side or inside the side surface of the ceramic capacitance film 24A, the intersection (C) between the side surface of the ceramic capacitance film 24A and the main surface of the semiconductor substrate 21, the side surface of the lower electrode 23A and the semiconductor substrate the length of the ceramic capacity film 24A surface that is present between the intersection (D) of the 21 main surface of the (L _2), the L ₂ ≧ D between the thickness of the ceramic capacity film 24A (D) Relationship is established.

In the second embodiment, as in the first embodiment, the influence of the side wall of the ceramic capacitance film 24A on the leakage current can be avoided, so that the reliability of the semiconductor integrated circuit device can be improved.

The semiconductor integrated circuit device according to the second embodiment is
As in the first embodiment, it can be formed by a lift-off method or etching.

Hereinafter, a third method for manufacturing a semiconductor integrated circuit device will be described with reference to FIGS.

First, as shown in FIG.
After a base insulating film 32 of a capacitor made of a silicon oxide film is formed on a semiconductor substrate 31 made of, for example, a CVD method, the first insulating film 32 is formed on the base insulating film 32 as shown in FIG. A platinum film 33, a BST film 34, and a second platinum film 35 are sequentially deposited.

Next, as shown in FIG. 9C, an upper electrode 35A was formed by etching the second platinum film 35 by ion milling or RIE using a photoresist mask. Later, by the same method,
As shown in FIG. 9D, the BST film 34 and the first platinum film 33 are simultaneously etched to form the ceramic capacitance film 34A and the lower electrode 33A.

Next, as shown in FIG.
After depositing an interlayer insulating film 36 made of a silicon oxide film by a method, as shown in FIG. 10B, a predetermined region in the interlayer insulating film 36 is formed by RIE or wet etching.
That is, an opening is simultaneously formed in a region where the upper electrode 35A is exposed and a region where the lower electrode 33A is exposed, and thereafter, the electrode wiring 37 is formed on the interlayer insulating film 36.

According to the first or second manufacturing method,
Since the lower electrode, the ceramic capacitor film, and the upper electrode were sequentially formed separately, the number of required steps was increased as compared with the conventional manufacturing method, and the cost could be increased. A semiconductor integrated circuit device having the same effects as the first embodiment can be obtained without increasing the number of steps required for formation.

In the first or second embodiment,
Although a semi-insulating GaAs substrate was used as the semiconductor substrate,
Instead, a silicon substrate may be used.

In the first or second embodiment, the ferroelectric BST film is used as the ceramic thin film serving as the capacitor insulating film of the capacitor. However, the ferroelectric BST film need not be a BST film. A similar effect can be obtained with a ceramic thin film having the following. That is, the present invention is irrelevant to the presence or absence of spontaneous polarization which is a feature of the ferroelectric material, and is exposed to a reducing atmosphere at the time of deposition of the interlayer insulating film, and has an oxygen defect, so that a leak current easily flows. In view of the above, it can be easily understood that the same effect can be obtained by using strontium titanate having a high dielectric constant but having no spontaneous polarization or other general ceramic materials having a perovskite structure.

[0069]

According to the semiconductor integrated circuit device of the first aspect, the length of the region between the side surface of the upper electrode and the side surface of the ceramic capacitor film on the surface of the ceramic capacitor film is larger than the thickness of the ceramic capacitor film. Since the path of the current flowing through the surface and side surfaces of the ceramic capacitor film is longer than the path of the current flowing through the inside of the ceramic capacitor film, the withstand voltage of the capacitor is smaller than that of the ceramic capacitor film. Determined by the leakage current flowing through it,
The influence of the side wall of the ceramic capacitance film on the withstand voltage of the capacitor can be eliminated.

According to the semiconductor integrated circuit device of the second aspect of the present invention, in a part of the peripheral portion of the multilayer capacitor, a portion between the side surface of the upper electrode on the surface of the ceramic capacitor film and the side surface of the ceramic capacitor film is provided. The length of the region is larger than the thickness of the ceramic capacitor film, and in the remaining region of the periphery of the multilayer capacitor, the length of the region between the side surface of the ceramic capacitor film on the lower surface of the ceramic capacitor film and the side surface of the lower electrode Is larger than the thickness of the ceramic capacitor film, so that in all regions around the periphery of the multilayer capacitor,
The path of the current flowing through the surface and the side surface of the ceramic capacitor film is longer than the path of the current flowing through the inside of the ceramic capacitor film.

According to the semiconductor integrated circuit device of the third aspect, the length of the region between the side surface of the upper electrode and the side surface of the ceramic capacitor film on the surface of the ceramic capacitor film is more reliable than the thickness of the ceramic capacitor film. Therefore, the path of the current flowing through the surface and the side surface of the ceramic capacitor film is surely longer than the path of the current flowing through the inside of the ceramic capacitor film.

Therefore, according to the first to third aspects of the present invention,
Since the withstand voltage of the capacitor is greatly improved, the yield and reliability of the semiconductor integrated circuit device are greatly improved.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, by patterning the second metal film, the intersection between the side surface of the upper electrode and the upper surface of the ceramic capacitor film, the side surface of the ceramic capacitor film, and the lower portion are formed. The length L of the surface of the ceramic capacitance film existing between the intersection with the upper surface of the electrode
And the thickness D of the ceramic capacitor film satisfies the relationship of L ≧ 2D, so that the semiconductor integrated circuit device according to the first aspect of the present invention can be reliably manufactured.

According to the method of manufacturing a semiconductor integrated circuit device according to the fifth aspect of the present invention, by patterning the ceramic thin film and the second metal film, the side surface of the upper electrode is partially removed from the peripheral region of the multilayer capacitor. Between the length L1 of the surface of the ceramic capacitance film existing between the intersection with the upper surface of the ceramic capacitance film and the intersection between the side surface of the ceramic capacitance film and the upper surface of the lower electrode, and the thickness D of the ceramic capacitance film In addition to the relationship of L1 ≧ 2D being established, the intersection of the side surface of the ceramic capacitor film and one main surface of the semiconductor substrate, the side surface of the lower electrode, and the one main surface of the semiconductor substrate in the remaining region of the peripheral portion of the multilayer capacitor. And the thickness D of the ceramic capacitor film, which is located between the intersection of the two and the thickness D of the ceramic capacitor film, satisfies L2 ≧ D. It is possible to reliably manufacture the circuit arrangement.

According to the method of manufacturing a semiconductor integrated circuit of the present invention, the ceramic thin film and the first metal film are simultaneously patterned to form the ceramic capacitor film and the lower electrode. The number of steps is reduced as compared with the case where the films are separately patterned. Therefore, when the invention of claim 6 is applied to the method of manufacturing a semiconductor integrated circuit device according to the invention of claim 4, a semiconductor integrated circuit in which the withstand voltage of the capacitor is greatly improved can be reliably manufactured without increasing the number of steps. can do.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing each step of a first method for manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 3 is a sectional view showing each step of a first method of manufacturing the semiconductor integrated circuit device according to the first embodiment.

FIG. 4 is a sectional view showing a structure of a peripheral portion of a capacitor of the semiconductor integrated circuit device according to the first embodiment.

FIG. 5 is a view for explaining the operation of the capacitors of the semiconductor integrated circuit devices according to the first embodiment and the conventional example,
(A) is a sectional view of a capacitor of a conventional semiconductor integrated circuit device, and (b) is a sectional view of a capacitor of the semiconductor integrated circuit device according to the first embodiment.

FIG. 6 is a diagram showing a relationship between a voltage and a leakage current density in a capacitor of the semiconductor integrated circuit devices according to the first embodiment and the conventional example.

FIG. 7 is a diagram showing the relationship between time and leakage current density in one embodiment of the present invention in the capacitors of the semiconductor integrated circuit devices according to the first embodiment and the conventional example.

FIG. 8 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing each step of a third manufacturing method of the semiconductor integrated circuit device according to the present invention.

FIG. 10 is a sectional view showing each step of a third method for manufacturing a semiconductor integrated circuit device according to the present invention.

FIG. 11 is a sectional view of a conventional semiconductor integrated circuit device.

FIG. 12 is a cross-sectional view showing each step of the conventional method of manufacturing a semiconductor integrated circuit device.

[Explanation of symbols]

 Reference Signs List 11 semiconductor substrate 12 base insulating film 13 first platinum film 13A lower electrode 14 ferroelectric film 14A ceramic capacitor film 15 second platinum film 15A upper electrode 16 interlayer insulating film 17 electrode wiring 18 photoresist 21 semiconductor substrate 22 base insulating Film 23A Lower electrode 24A Ceramic capacitor film 25A Upper electrode 26 Interlayer insulating film 27 Electrode wiring 31 Semiconductor substrate 32 Base insulating film 33 First platinum film 33A Lower electrode 34 BST film (ferroelectric film) 34A Ceramic capacitor film 35 Second Platinum film 35A Upper electrode 36 Interlayer insulating film 37 Electrode wiring

[Procedure amendment]

[Submission date] April 27, 2000 (200.4.2
7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

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[Title of the Invention] Semiconductor device

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[Claims]

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[0019]

According to the present invention, there is provided a semiconductor device comprising:
A ceramic capacitor film formed on a semiconductor substrate; and an upper electrode formed on the ceramic capacitor film. The side surface of the upper electrode is separated from the side surface formed by etching the ceramic capacitor film to form the ceramic. It is formed to be spaced inward by the same distance or more than the thickness of the capacitance film.

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[0027]

According to the present invention, since the side surface of the ceramic capacitor film which is formed by etching and easily conducts a leak current is separated from the side surface of the upper electrode by the same distance or more as the thickness of the ceramic capacitor film, the ceramic capacitor film is formed. It is possible to prevent the leakage current passing through the side surface of the capacitance film from becoming dominant.

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[0069]

As described above, according to the present invention, the side surface of the ceramic capacitor film formed by etching and easily passing a leak current is formed at a distance from the side surface of the upper electrode at least the same distance as the thickness of the ceramic capacitor film. To be
The leakage current passing through the side surface of the ceramic capacitance film can be prevented from becoming dominant, and a high-performance capacitor can be manufactured.

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Claims (6)

[Claims] 1. A semiconductor comprising a multilayer capacitor formed on a semiconductor substrate, a lower electrode sequentially formed on one main surface of the semiconductor substrate, a ceramic capacitor film made of a ceramic thin film having a perovskite structure, and an upper electrode. An integrated circuit device, wherein a side surface of the upper electrode is located inside a side surface of the ceramic capacitance film, and a side surface of the ceramic capacitance film is located inside a side surface of the lower electrode; The length L of the surface of the ceramic capacitance film existing between the intersection of the side surface of the upper electrode and the upper surface of the ceramic capacitance film and the intersection of the side surface of the ceramic capacitance film and the upper surface of the lower electrode; A semiconductor integrated circuit device, wherein a relationship of L ≧ 2D is established with the thickness D of the capacitance film. 2. A semiconductor device comprising: a semiconductor substrate having one principal surface on the semiconductor substrate;
Lower electrode sequentially formed on top, has perovskite structure
Ceramic film and upper part of ceramic thin film
Semiconductor integration with multilayer capacitor composed of electrodes
In a circuit device, in a part of a peripheral portion of the multilayer capacitor,
The side surface of the upper electrode is closer to the side surface of the ceramic capacitor film.
Is also located inside and on the side of the ceramic capacitance film.
The surface is located inside the side surface of the lower electrode, and
Intersection between the side surface of the upper electrode and the upper surface of the ceramic capacitance film
A point, a side surface of the ceramic capacitor film, and an upper surface of the lower electrode
Surface of the ceramic capacitance film existing between the intersection of
Length L ₁ And the thickness D of the ceramic capacitance film
L₁ ≧ 2D holds, and in the remaining region of the peripheral portion of the multilayer capacitor,
The side surface of the upper electrode is the same as the side surface of the ceramic capacitor film.
At least one side of the ceramic capacitance film.
And the peripheral portion of the ceramic capacitor film is
Of the semiconductor substrate outside the side surfaces of the unit electrodes
Surface of the ceramic capacitor film and
Intersection with one main surface of the semiconductor substrate and side surface of the lower electrode
Before it exists between the point of intersection with the one principal surface of the semiconductor substrate
The length L of the surface of the ceramic capacitor film_Two And the ceramic
Between the thickness D of the capacitor film and L_Two ≧ D
A semiconductor integrated circuit device. 3. A surface of the ceramic capacitance film existing between an intersection of a side surface of the upper electrode and an upper surface of the ceramic capacitance film and an intersection of a side surface of the ceramic capacitance film and an upper surface of the lower electrode. It is characterized by comprising a first region between a side surface of the upper electrode and a side surface of the ceramic capacitance film on a surface of the ceramic capacitance film, and a second region composed of a side surface of the ceramic capacitance film. 3. The semiconductor integrated circuit device according to claim 1, wherein 4. A step of depositing a first metal film on one main surface of a semiconductor substrate; a step of patterning the first metal film to form a lower electrode; and a perovskite structure on the lower electrode. Depositing a ceramic thin film having: a step of patterning the ceramic thin film such that a side surface of the ceramic thin film is located inside a side surface of the lower electrode; and forming a ceramic capacitor film. Depositing a second metal film on the second metal film; and forming the second metal film such that a side surface of the second metal film is located inside a side surface of the ceramic capacitor film and the second metal film The length L of the surface of the ceramic capacitance film existing between the intersection of the side surface of the ceramic capacitance film and the upper surface of the ceramic capacitance film and the intersection of the side surface of the ceramic capacitance film and the upper surface of the lower electrode; Tsu L ≧ between the thickness D of the click capacitor film 2
Forming an upper electrode by patterning such that the relationship of D is established. 5. A first metal film is formed on one main surface of a semiconductor substrate.
Depositing; patterning the first metal film to form a lower electrode;
And a ceramic having a perovskite structure on the lower electrode.
Depositing a ceramic thin film; and attaching the ceramic thin film to a peripheral portion of the ceramic thin film.
In the region of the portion, the side surface of the ceramic thin film is
It is located inside the side of the electrode, and the ceramic
In the remaining region of the periphery of the ceramic thin film, the ceramic thin film is used.
The edge of the film remains on the semiconductor substrate and the ceramic
Intersection between the side surface of the thin film and one main surface of the semiconductor substrate
Intersection between the side surface of the lower electrode and one main surface of the semiconductor substrate
And the length L of the surface of the ceramic thin film existing between_Two 
And the thickness D of the ceramic capacitor film._Two ≧ D
Pattern the ceramic capacitor to establish the relationship
Forming a film; and depositing a second metal film on the ceramic capacitor film.
And the side surface of the second metal film is the ceramic.
It is located inside the side of the mic capacitance film,
In a part of the peripheral portion of the ceramic thin film,
Side surface of the second metal film and upper surface of the ceramic capacitance film
, The side surface of the ceramic capacitor film and the lower electrode
The ceramic capacitance film present between the intersection with the upper surface of the ceramic capacitor
Surface length L₁ And the thickness D of the ceramic capacitance film
L between ₁ Patterning to satisfy ≧ 2D
Forming an upper electrode by performing
Of manufacturing a semiconductor integrated circuit device. 6. A step of sequentially depositing a first metal film, a ceramic thin film and a second metal film on a semiconductor substrate, and exposing a lower electrode lead-out region of the ceramic thin film to the second metal film. Forming a ceramic capacitor film and a lower electrode by simultaneously patterning the ceramic thin film and the first metal film, and forming an insulating film on the entire surface of the semiconductor substrate. Depositing; etching the insulating film and the ceramic capacitor film to form an opening for leading an upper electrode in the insulating film; and forming an opening in the insulating film and the ceramic capacitor film for leading a lower electrode. Forming a semiconductor integrated circuit device.