JP2000294803A - Semiconductor device - Google Patents
Semiconductor deviceInfo
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- JP2000294803A JP2000294803A JP30851699A JP30851699A JP2000294803A JP 2000294803 A JP2000294803 A JP 2000294803A JP 30851699 A JP30851699 A JP 30851699A JP 30851699 A JP30851699 A JP 30851699A JP 2000294803 A JP2000294803 A JP 2000294803A
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- thin film
- film layer
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【課題】電界集中が発生しにくく、信頼性の高い耐圧構
造を有する半導体装置を提供すること。
【解決手段】ｐ基板１０の表面層にＮwell層９を形成
し、Ｎwell層９の表面層にｎ形の高電位領域８、ｐ形の
低電位領域１２およびＰoffset領域１４を形成し、ｐ基
板１０の表面側には、絶縁酸化膜１８を介して、第１導
電形薄膜層４と第２導電形薄膜層５の繰り返しからなる
渦巻き状薄膜層６を形成し、ｐ基板１０の裏面側には、
裏面側電極１１を形成する。この構造において、低電位
側電極３を基準にして、高電位側電極２に正電位ＶS を
印加すると、渦巻き状の薄膜層６の高電位側電極２と接
続する端にも電位ＶS が印加され、この渦巻き状の薄膜
層には均一な電位分布が形成される。
[PROBLEMS] To provide a semiconductor device having a highly reliable breakdown voltage structure in which electric field concentration hardly occurs. The N well layer 9 is formed on the surface layer of A p substrate 10, to form a N well layer low potential region 12 and P offset region 14 of the high potential region 8, p-type n-type surface layer of 9 On the surface side of the p-substrate 10, a spiral thin-film layer 6 composed of a repetition of the first conductive thin-film layer 4 and the second conductive thin-film layer 5 is formed via an insulating oxide film 18. On the back side,
The back electrode 11 is formed. In this structure, the low-voltage electrode 3 as a reference, high when the voltage electrode 2 for applying a positive potential V S, spiral potential V S to the end to be connected to the high potential electrode 2 of the thin-film layer 6 is A uniform potential distribution is formed on the spiral thin film layer.
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、プレーナ型の横
型および縦型の半導体装置に関し、特に、その半導体装
置の耐圧構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar type horizontal and vertical semiconductor device, and more particularly to a breakdown voltage structure of the semiconductor device.
【０００２】[0002]
【従来の技術】バイポーラトランジスタ、パワーＭＯＳ
ＦＥＴおよびＩＧＢＴ（絶縁ゲート型バイポーラトラン
ジスタ）に代表されるパワーデバイスにおいて、数十か
ら数千ボルトの耐圧構造（耐圧をもつ箇所の構造）が必
要とされる。また、これらのパワーデバイスを駆動する
ために、近年、高耐圧ＩＣの開発が盛んに行われ、この
高耐圧ＩＣもまたパワーデバイスと同等の耐圧が要求さ
れる。2. Description of the Related Art Bipolar transistors and power MOS
Power devices such as FETs and IGBTs (insulated gate bipolar transistors) require a withstand voltage structure (structure with a withstand voltage) of several tens to several thousand volts. In recent years, in order to drive these power devices, high-voltage ICs have been actively developed, and these high-voltage ICs are also required to have the same withstand voltage as the power devices.
【０００３】図７は、Ｄｏｕｂｌｅ ＲＥＳＵＲＦ構造
と抵抗性フィールドプレート構造を組み合わせた構造
で、同図（ａ）は要部断面図で、同図（ｂ）は電位分布
である。この耐圧構造は、高耐圧ＩＣの代表的な構造で
ある。図７（ａ）において、ｐ基板３５の表面層にＮ
well領域３４が設けられている。このＮwell領域３４の
表面層に高電位領域３３、低電位領域３７およびＰoffs
et領域３９がそれぞれ形成されている。高電位領域３３
上と低電位領域３７上には、高電位側電極３２と低電位
側電極３８がそれぞれ形成され、ｐ基板３５上に形成さ
れる絶縁酸化膜４１上に高比抵抗の抵抗性フィールドプ
レートである薄膜抵抗層４０が形成され、この薄膜抵抗
層４０により高電位側電極３２と低電位側電極３８とが
電気的に接続されている。また、低電位側電極３８と裏
面側電極３６は、ｐ基板３５の終端部で電気的に接続し
ている。尚、３５ａはｐ基板層である。FIG. 7 shows a structure in which a double RESURF structure and a resistive field plate structure are combined. FIG. 7A is a sectional view of a main part, and FIG. 7B is a potential distribution. This withstand voltage structure is a typical structure of a high withstand voltage IC. In FIG. 7A, the surface layer of the p substrate 35 is N
A well region 34 is provided. High potential region 33 in the surface layer of the N well region 34, the low potential region 37 and P offs
et regions 39 are formed respectively. High potential area 33
A high-potential-side electrode 32 and a low-potential-side electrode 38 are formed on the upper and lower-potential regions 37, respectively, and a high-resistance resistive field plate is formed on an insulating oxide film 41 formed on a p-substrate 35. A thin-film resistance layer 40 is formed, and the high-potential-side electrode 32 and the low-potential-side electrode 38 are electrically connected by the thin-film resistance layer 40. The low-potential-side electrode 38 and the back-surface-side electrode 36 are electrically connected at the end of the p-substrate 35. In addition, 35a is a p substrate layer.
【０００４】図７（ｂ）において、低電位側電極３８を
基準（例えば、ＧＮＤ）として、高電位側電極３２に正
電位ＶS を印加したときの、チップ表面の電位分布の様
子を図示している。電位分布は抵抗性フィールドプレー
ト４０の両端面付近で歪みが大きく、電界が集中してい
る。そのために、この個所で耐圧が低下する。FIG. 7 (b) shows a potential distribution on the chip surface when a positive potential V S is applied to the high potential side electrode 32 with the low potential side electrode 38 as a reference (eg, GND). ing. The potential distribution has large distortion near both end surfaces of the resistive field plate 40, and the electric field is concentrated. For this reason, the breakdown voltage is reduced at this point.
【０００５】図８は半導体内部の空乏層の拡がりを示し
た図である。図８の空乏層の拡がりを示した半導体装置
の要部断面図は、図７（ａ）の要部断面図と同一であ
る。従って、図中の符号は図７（ａ）と同じである。図
８において、低電位側電極３８と裏面側電極３６を基準
にして、高電位側電極３２に正電位ＶS が印加される
と、逆バイアスが印加される２つのｐｎ接合から空乏層
４７、４８が拡張していく。FIG. 8 is a diagram showing the spread of a depletion layer inside a semiconductor. The cross-sectional view of the main part of the semiconductor device showing the expansion of the depletion layer in FIG. 8 is the same as the cross-sectional view of the main part in FIG. Therefore, the reference numerals in the figure are the same as those in FIG. 8, when a positive potential V S is applied to the high potential side electrode 32 with reference to the low potential side electrode 38 and the back side electrode 36, the depletion layer 47 and the two pn junctions to which the reverse bias is applied are connected. 48 expands.
【０００６】１つのｐｎ接合は、Ｎwell領域３４とＰ
offset領域３９、低電位領域３７のｐｎ接合であり、も
う一つのｐｎ接合は、Ｎwell領域３４とｐ基板３５のｐ
ｎ接合である。一般的に、絶縁酸化膜４１と半導体界面
の固定電荷の影響で、半導体表面の空乏層内部には電界
の集中が起き易く、これがデバイスの破壊につながる。[0006] One pn junction is composed of an N well region 34 and a P well.
The offset region 39 is a pn junction of the low potential region 37, and the other pn junction is formed by the N well region 34 and the p substrate of the p substrate 35.
It is an n-junction. Generally, an electric field tends to concentrate inside the depletion layer on the semiconductor surface due to the effect of fixed charges at the interface between the insulating oxide film 41 and the semiconductor, which leads to destruction of the device.
【０００７】抵抗性フィールドプレート構造は、高電位
側電極３２に電位ＶS を印加すると、薄膜抵抗層４０に
も電位ＶS が印加され、薄膜抵抗層４０には、電位ＶS
と薄膜抵抗層４０の抵抗値に応じた電流が流れる。これ
によって、薄膜抵抗層４０に、均一な電位分布が生じれ
ば、この電位分布による電界が、絶縁酸化膜４１を介
し、半導体層に影響を及ぼし、半導体層表面の空乏層の
中の電界集中を緩和することができる。その結果、高い
耐圧を安定して確保することができる。[0007] resistive field plate structure, when applying a potential V S to the high-potential electrode 32, the potential V S in the thin film resistor layer 40 is applied, the thin film resistor layer 40, the potential V S
Then, a current according to the resistance value of the thin-film resistance layer 40 flows. As a result, if a uniform potential distribution is generated in the thin-film resistance layer 40, the electric field due to this potential distribution affects the semiconductor layer via the insulating oxide film 41, and the electric field concentration in the depletion layer on the surface of the semiconductor layer Can be alleviated. As a result, a high breakdown voltage can be stably secured.
【０００８】従来の構造においては、高電位領域３３と
低電位領域３７との間に大きな漏れ電流が発生しないよ
うに、フィールドプレートである薄膜抵抗層４０には、
数ＭΩｃｍの高比抵抗の層、例えば、ノンドープアモル
ファスシリコンや酸素ドープポリシリコン（ＳＩＰＯ
Ｓ）が使用されてきた。しかしながら、数ＭΩｃｍの高
比抵抗の層を安定して形成することは、この層に入り込
む不純物を極めて小さく抑制しなければならず、製造は
極めて困難である。また、場所による比抵抗の値にばら
つきが発生しやすい。In the conventional structure, the thin-film resistance layer 40 as a field plate is provided with a thin film resistance layer 40 so that a large leakage current does not occur between the high potential region 33 and the low potential region 37.
A layer having a high specific resistance of several MΩcm, for example, non-doped amorphous silicon or oxygen-doped polysilicon (SIPO)
S) has been used. However, it is extremely difficult to stably form a layer having a high specific resistance of several MΩcm in order to minimize the impurities that enter this layer, and it is extremely difficult to manufacture. In addition, the value of the specific resistance easily varies depending on the location.
【０００９】この薄膜抵抗層４０の抵抗値が低い場合に
は、抵抗値のばらつきは小さくなるが、大きな漏れ電流
が流れるため、発生損失が大きくなり、デバイスが破壊
し易くなる。また、抵抗値が高すぎる場合は、抵抗値の
ばらつきが発生して、漏れ電流は不均一に流れ易くな
り、高電位領域３３と低電位領域３７の間に、均一な電
位分布を形成することが困難となり、半導体層の空乏層
中に電界集中箇所が生じで、耐圧が低下する可能性があ
る。When the resistance value of the thin-film resistance layer 40 is low, the variation in the resistance value is small, but a large leakage current flows, so that the generated loss increases and the device is easily broken. If the resistance value is too high, a variation in the resistance value occurs, and the leakage current tends to flow unevenly, so that a uniform potential distribution is formed between the high potential region 33 and the low potential region 37. Is difficult, and an electric field concentration portion is generated in the depletion layer of the semiconductor layer, so that the breakdown voltage may be reduced.
【００１０】これらの問題点を解決するために、前記の
薄膜抵抗層４０の抵抗値を低くして、ばらつきを抑え、
この薄膜抵抗層４０を、島状のベース電極４３（高電位
側電極）とそれを取り囲む外周電極４４（低電位側電
極）との間に、渦巻き状に形成し、長い薄膜抵抗層（渦
巻き状の薄膜抵抗層４５）でベース電極４３と外周電極
４４を接続することで、抵抗値を増大させる、図９のよ
うな構造が特開平４−３３２１７３号公報に開示されて
いる。In order to solve these problems, the resistance of the thin-film resistance layer 40 is reduced to suppress variations.
The thin-film resistance layer 40 is formed in a spiral shape between the island-shaped base electrode 43 (high-potential-side electrode) and the peripheral electrode 44 (low-potential-side electrode) surrounding the base electrode 43, and a long thin-film resistance layer (spiral-shaped) is formed. JP-A-4-332173 discloses a structure as shown in FIG. 9 in which the resistance value is increased by connecting the base electrode 43 and the outer peripheral electrode 44 with the thin film resistance layer 45).
【００１１】この構造では、渦巻き状の薄膜抵抗層４５
の比抵抗を小さくして、ばらつきを抑制し、渦巻き状の
薄膜抵抗層４５の端から端の間の抵抗値を大きくして、
漏れ電流を抑制している。また、ベース電極４３と外周
電極４４とを直線で結ぶ線上の電位分布は、渦巻き状の
薄膜抵抗層４５の渦巻きの回数分だけ、階段状に変化す
るが、回数を多くすれば、階段の落差は小さくなり、平
均的な電位勾配は一定となる。In this structure, the spiral thin-film resistance layer 45 is formed.
The resistivity of the spiral thin film resistance layer 45 is increased by reducing the specific resistance of the
The leakage current is suppressed. Further, the potential distribution on a line connecting the base electrode 43 and the outer peripheral electrode 44 in a straight line changes stepwise by the number of spirals of the spiral thin film resistance layer 45. Becomes smaller, and the average potential gradient becomes constant.
【００１２】この構造によれば、外周電極４４とベース
電極４３を電気的に接続する渦巻き状の薄膜抵抗層４５
の比抵抗の値を、従来構造の抵抗性フィールドプレート
に比べ、低い値として実現できるというものである。こ
れによって、抵抗性フィールドプレートよりも抵抗値の
制御が容易になる利点を有する。According to this structure, a spiral thin-film resistance layer 45 for electrically connecting the outer peripheral electrode 44 and the base electrode 43 is formed.
Can be realized as a value lower than that of a resistive field plate having a conventional structure. This has the advantage that control of the resistance value is easier than with a resistive field plate.
【００１３】[0013]
【発明が解決しようとする課題】しかし、この渦巻き状
の薄膜抵抗層４５を形成する場合、半導体装置のチップ
サイズが大きくなると、前記渦巻き状の薄膜抵抗層４５
の距離が長くなり、抵抗値が大きくなる。チップサイズ
によらず同一の漏れ電流を流すには、チップサイズが大
きくなると、渦巻き状の薄膜抵抗層４５の幅を広げる必
要があり、必然的に周辺に配置される耐圧構造の幅が大
きくなる。 従って、同一の耐圧を有する半導体装置で
も、電流容量によって、つまり、活性領域の面積の変化
によって、耐圧構造の幅を変える必要がある。これは、
同一の耐圧系列の半導体装置を製作する場合、製造コス
ト上、不都合である。However, when the spiral thin-film resistance layer 45 is formed, when the chip size of the semiconductor device is increased, the spiral thin-film resistance layer 45 is reduced.
Becomes longer and the resistance value becomes larger. In order to allow the same leakage current to flow regardless of the chip size, as the chip size increases, it is necessary to increase the width of the spiral thin-film resistance layer 45, and the width of the withstand voltage structure disposed inevitably increases. . Therefore, even in semiconductor devices having the same breakdown voltage, the width of the breakdown voltage structure needs to be changed depending on the current capacity, that is, the change in the area of the active region. this is,
Manufacturing semiconductor devices of the same breakdown voltage series is inconvenient in terms of manufacturing cost.
【００１４】また、渦巻き状の薄膜抵抗層４５として採
用する薄膜の比抵抗の値が、比較的低い値に設定できる
ようになったとはいえ、まだまだ、均一な比抵抗の値を
渦巻き状の抵抗層に沿って、得ることは困難である。そ
のため、渦巻き状の薄膜抵抗層４５に場所によって抵抗
値のばらつきが発生して、耐圧構造部で局部的に電界が
集中し、素子耐圧の低下を招く。また、この抵抗値は温
度に対する変動が大きく、デバイスに、この渦巻き状の
抵抗層を用いることは、信頼性の確保の観点からも困難
である。Further, although the specific resistance of the thin film employed as the spiral thin-film resistance layer 45 can be set to a relatively low value, it is still possible to reduce the uniform specific resistance value to the spiral resistance. Along the layers, it is difficult to obtain. For this reason, the resistance value varies depending on the location in the spiral thin film resistance layer 45, and the electric field is locally concentrated in the breakdown voltage structure portion, which causes a decrease in the breakdown voltage of the element. Further, the resistance value greatly varies with temperature, and it is difficult to use the spiral resistance layer in a device from the viewpoint of ensuring reliability.
【００１５】また、ＵＳＰ５４７５２５８にパワーＭＯ
ＳＦＥＴのゲート・ドレイン間の絶縁膜上にツェナーダ
イオードを形成することが開示されているが、ソース・
ドレイン間の電位分布を均一化させるには、十分でな
い。また、ＵＳＰ５７２９０４４に、半導体基板内にｐ
領域、ｎ領域を設けて金属で接続し、ダイオードを直列
に形成することが開示されているが、このＵＳＰ５７２
９０４４の構造では、横型デバイスで広く適用されてい
るＲＥＳＵＲＦ構造との組合せは困難であり、従って、
横型デバイスには不向きである。US Pat. No. 5,475,258 has a power MO.
It is disclosed that a Zener diode is formed on an insulating film between the gate and drain of an SFET.
It is not enough to make the potential distribution between the drains uniform. Also, US Pat. No. 5,729,044 states that p
It is disclosed that a region and an n region are provided and connected by metal to form a diode in series.
The structure of 9044 is difficult to combine with the RESURF structure, which is widely applied in lateral devices, and
Not suitable for horizontal devices.
【００１６】また、ＵＳＰ５３８２８２５に、縦型デバ
イスを対象として、活性領域の外周部の不活性領域上
に、多数のダイオードを渦巻き状に直列接続することが
開示されている。このＵＳＰ５３８２８２５では、横型
デバイスで、しかも活性領域上にこの構造を配置するこ
とは開示されておらず、また、渦巻き状の直列ダイオー
ドの数は、素子に定格電圧になるように選定されてい
る。従って、定格電圧付近の電圧が素子に印加された場
合は、大きな漏れ電流が流れるという不都合を生じる。Further, US Pat. No. 5,382,825 discloses that a large number of diodes are spirally connected in series on an inactive region on an outer peripheral portion of an active region for a vertical device. US Pat. No. 5,382,825 does not disclose that this structure is a lateral device and that this structure is arranged on an active region, and the number of spiral series diodes is selected so that the element has a rated voltage. Therefore, when a voltage near the rated voltage is applied to the element, there is a disadvantage that a large leakage current flows.
【００１７】前記のことから、横型および縦型の双方の
半導体装置に適用できて、フィールドプレートの様な働
きをするダイオードを多数個直列した構造で、漏れ電流
が小さく、且つ、十分に電位分布の均一化が図れる耐圧
構造の提案は未だ成されていない。この発明の目的は、
前記の課題を解決して、電界集中が発生しにくく、信頼
性の高い耐圧構造を有する横型および縦型構造の半導体
装置を提供することにある。From the above, it is possible to apply the present invention to both the horizontal and vertical semiconductor devices and to form a structure in which a plurality of diodes acting like a field plate are connected in series. The leakage current is small and the potential distribution is sufficient. There has not yet been proposed a pressure-resistant structure capable of achieving uniformity. The purpose of this invention is
An object of the present invention is to provide a semiconductor device of a horizontal type and a vertical type that has a high withstand voltage structure in which electric field concentration hardly occurs and which has a high reliability.
【００１８】[0018]
【課題を解決するための手段】前記の目的を達成するた
めに、半導体基板上に形成された絶縁膜上に、互いに離
して形成された第１電極と第２電極とを有する半導体装
置において、両端がそれぞれ第１電極、第２電極に接続
され、且つ、第１電極を取り囲む渦巻き状の薄膜層が、
前記絶縁膜上に形成され、該渦巻き状の薄膜層の長手方
向に沿って、直列に複数個のｐｎダイオードが形成され
る構成とする。In order to achieve the above object, in a semiconductor device having a first electrode and a second electrode formed apart from each other on an insulating film formed on a semiconductor substrate, A spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, and surrounding the first electrode,
A plurality of pn diodes are formed on the insulating film and formed in series along the longitudinal direction of the spiral thin film layer.
【００１９】前記第１電極と前記第２電極との間の前記
半導体基板が、主電流が流れる活性領域となっていて、
その半導体基板上に前記絶縁膜を介して前記渦巻き状の
薄膜層が形成されている構成とする。前記薄膜層が、ポ
リシリコンで形成され、該ポリシリコンに第１導電形領
域と前記第２導電形領域が交互に複数個形成され、前記
第１導電形領域と前記第２導電形領域とでｐｎダイオー
ドが形成される構成とするとよい。The semiconductor substrate between the first electrode and the second electrode is an active region through which a main current flows,
The spiral thin film layer is formed on the semiconductor substrate via the insulating film. The thin film layer is formed of polysilicon, and a plurality of first conductivity type regions and the second conductivity type regions are alternately formed on the polysilicon, and the thin film layer is formed of the first conductivity type region and the second conductivity type region. A configuration in which a pn diode is formed is preferable.
【００２０】前記薄膜層が、第１導電形ポリシリコンで
形成され、該第１導電形ポリシリコンに選択的に第２導
電形領域が、離して複数個形成され、前記第１導電形ポ
リシリコンで形成された第１導電形領域と前記第２導電
形領域が交互に複数個形成され、前記第１導電形領域と
前記第２導電形領域とでｐｎダイオードが形成される構
成とするとよい。The thin film layer is formed of a first conductivity type polysilicon, and a plurality of second conductivity type regions are selectively formed on the first conductivity type polysilicon to be separated from each other. It is preferable that a plurality of the first conductivity type regions and the second conductivity type regions are formed alternately, and a pn diode is formed by the first conductivity type regions and the second conductivity type regions.
【００２１】前記ｐｎダイオードが、順直列もしくは逆
直列に前記薄膜層に形成されるとよい。前記ｐｎダイオ
ードがツェナーダイオードであると効果的である。前記
第１導電形領域および前記第２導電形領域の不純物濃度
が１×１０18ｃｍ -3以上であるとよい。The pn diode is connected in series or in reverse.
It is preferable that the thin film layer is formed in series. The pn dio
It is effective if the diode is a Zener diode. Said
Impurity concentrations of the first conductivity type region and the second conductivity type region
Is 1 × 1018cm -3It is good to be above.
【００２２】前記ポリシリコンが、ｐ形不純物もしくは
ｎ形不純物を１×１０18ｃｍ-3以上ドーピングして形成
されると好ましい。前記絶縁膜の厚みを０．０１以上で
１０μｍ以下とするとよい。前記半導体基板が第１導電
形であって、該半導体基板の表面層に第１導電形の第１
領域と第２導電形の第２領域が離して形成され、前記第
１領域と前記第２領域の間の前記半導体基板の表面層
に、前記第１領域から離し、且つ、前記第２領域に接す
るように第２導電形の第３領域が形成され、前記第１領
域と前記第１電極とが接続し、前記第２領域と前記第２
電極とが接続する構成としてもよい。It is preferable that the polysilicon is formed by doping a p-type impurity or an n-type impurity at 1 × 10 18 cm −3 or more. It is preferable that the thickness of the insulating film is not less than 0.01 and not more than 10 μm. The semiconductor substrate is of a first conductivity type, and a first layer of the first conductivity type is formed on a surface layer of the semiconductor substrate.
A region and a second region of the second conductivity type are formed apart from each other, on a surface layer of the semiconductor substrate between the first region and the second region, apart from the first region, and on the second region. A third region of the second conductivity type is formed so as to be in contact with the first region, the first region is connected to the first electrode, and the second region is connected to the second region.
It is good also as a structure connected with an electrode.
【００２３】前記半導体基板が第１導電形であって、該
半導体基板の表面層に第２導電形の第１領域と第２領域
が離してそれぞれ形成され、前記第１領域と前記第２領
域の間の前記半導体基板の表面層に、前記第１領域およ
び第２領域から離して、第２導電形の第３領域が、前記
第１領域を取り囲むようにリング状に形成され、前記第
１領域と前記第１電極とが接続し、前記第２領域と前記
第２電極とが接続する構成としてもよい。The semiconductor substrate is of a first conductivity type, and a first region and a second region of a second conductivity type are separately formed on a surface layer of the semiconductor substrate, and the first region and the second region are formed. A third region of a second conductivity type is formed in a ring shape on the surface layer of the semiconductor substrate between the first region and the second region so as to surround the first region. A configuration may be such that a region is connected to the first electrode, and the second region is connected to the second electrode.
【００２４】前記半導体装置の耐圧をＶB 、前記ｐｎダ
イオードの降伏電圧をＶZ 、前記渦巻き状の薄膜層の中
のｐｎダイオードを形成するｐｎ接合で、逆阻止状態に
あるｐｎ接合の数をｍとすると、 ＶB ＜ＶZ ×ｍ を満足するようにするとよい。The breakdown voltage of the semiconductor device is V B , the breakdown voltage of the pn diode is V Z , and the number of pn junctions forming a pn diode in the spiral thin film layer in a reverse blocking state is as follows. When m, may be configured to satisfy V B <V Z × m.
【００２５】前記のように、例えば、ｎ形ポリシリコン
にｐ形領域を離して複数個形成することで、ｐ形領域と
ｎ形領域が交互に形成される。このｐ形領域とｎ形領域
でｐｎダイオードを形成する。そうすると、例えば、ｐ
1 ｎ1 ｐ2 ｎ2 ・・・と並んだ構造で薄膜層が形成され
ることになる。この最初のｐ1 ｎ1 で第１のｐｎダイオ
ードが形成され、つぎのｎ1 ｐ2 で第２のｐｎダイオー
ドが形成され、つぎのｐ2 ｎ2 で第３のｐｎダイオード
が形成される。これは第１のｐｎダイオードと第２のダ
イオードは逆直列接続されたこととなり、また、第２の
ｐｎダイオードと第３のｐｎダイオードも逆直列に接続
されたことになる。つまり、薄膜層は互いに逆直列に接
続されたｐｎダイオードが、直列に複数個接続された構
造となる。As described above, for example, p-type regions and n-type regions are alternately formed by forming a plurality of p-type regions in n-type polysilicon at a distance. The p-type region and the n-type region form a pn diode. Then, for example, p
The thin film layer is formed in a structure arranged in line with 1 n 1 p 2 n 2 . The first p 1 n 1 forms a first pn diode, the next n 1 p 2 forms a second pn diode, and the next p 2 n 2 forms a third pn diode. This means that the first pn diode and the second diode are connected in anti-series, and that the second pn diode and the third pn diode are also connected in anti-series. That is, the thin film layer has a structure in which a plurality of pn diodes connected in anti-series are connected in series.
【００２６】また、前記のｎ1 とｐ2 を金属膜などで接
続すると、ｐ1 ｎ1 のｐｎダイオードとｐ2 ｎ2 のｐｎ
ダイオードとが順直列に接続されたことになる。つま
り、薄膜層はｐｎダイオードが順直列に複数個接続され
た構造となる。このｐｎダイオードをツェナーダイオー
ドとするために、ノンドープのポリシリコンに１×１０
18ｃｍ-3以上の第１導電形の不純物をドープして、第１
導電形ポリシリコンを形成する。この第１導電形ポリシ
リコンに、不純物濃度が１×１０18ｃｍ-3以上である第
２導電形領域を形成して、ツェナーダイオードを形成す
る。勿論、この不純物濃度が１０18ｃｍ-3から１０19ｃ
ｍ-3ではアバランシェ降伏とツェナー降伏が混在し、１
０19ｃｍ-3以上でツェナー降伏が支配的になると推定さ
れる。When the above n 1 and p 2 are connected by a metal film or the like, the pn diode of p 1 n 1 and the pn diode of p 2 n 2
This means that the diode and the diode are connected in series. That is, the thin film layer has a structure in which a plurality of pn diodes are connected in series. In order to make this pn diode a Zener diode, 1 × 10
Doping with an impurity of the first conductivity type of 18 cm -3 or more,
Conductive polysilicon is formed. A second conductivity type region having an impurity concentration of 1 × 10 18 cm −3 or more is formed in the first conductivity type polysilicon to form a Zener diode. Of course, this impurity concentration is 10 18 cm −3 to 10 19 c
At m -3 , avalanche and Zener yields are mixed and 1
It is estimated that Zener breakdown becomes dominant above 0 19 cm -3 .
【００２７】このように、ツェナーダイオードを直列接
続（逆直列または順直列）し、渦巻き状の薄膜層とする
ことで、第１電極と第２電極の間を直線で結ぶ線上で均
等な電位分布が得られ、電界集中を防止できる。図５は
ポリシリコンを用いたツェナーダイオードの電圧・電流
特性である。逆バイアスの領域では、ｐｎ接合の逆方向
電圧を増加させていくと、所定の電圧（ツェナー電圧：
ＶZ ）以上で、急激に電流が流れる、所謂、降伏現象が
現れる。前記のように、ツェナーダイオードにより形成
した、渦巻き状の薄膜層は、低電位側電極を基準にし
て、高電位側電極に電圧ＶS を印加すると、ＶS の大き
さで、ツェナーダイオードの逆阻止状態は非降伏状態と
降伏状態の２つの状態に分かれる。As described above, by connecting the zener diodes in series (in reverse series or forward series) to form a spiral thin film layer, a uniform potential distribution is formed on a straight line connecting the first electrode and the second electrode. And electric field concentration can be prevented. FIG. 5 shows voltage-current characteristics of a Zener diode using polysilicon. In the reverse bias region, when the reverse voltage of the pn junction is increased, a predetermined voltage (zener voltage:
Above V Z ), a so-called breakdown phenomenon appears, in which current flows rapidly. As described above, when a voltage V S is applied to the high-potential-side electrode with respect to the low-potential-side electrode, the spiral thin-film layer formed by the Zener diode has a magnitude of V S , which is the reverse of the Zener diode. The blocking state is divided into two states, a non-breakdown state and a breakdown state.
【００２８】個々のツェナーダイオードのツェナー電圧
をＶZ 、薄膜層の中のツェナーダイオードを形成するｐ
ｎ接合で、逆阻止状態にあるｐｎ接合の数をｍとする
と、 （１）ＶS ＜ｍ・ＶZ のとき（ツェナーダイオードは非
降伏状態） ｐｎ接合の逆方向の漏れ電流ＩS が渦巻き状の薄膜層に
流れる。高濃度の不純物をドープしたポリシリコンに形
成された個々のツェナーダイオードは、比較的漏れ電流
ＩS が大きく、均一な電圧・電流特性を有するために、
渦巻き状の薄膜層は、渦巻きに沿って均一な電位分布と
なる。尚、不純物濃度を高くすると、濃度制御が容易に
なり、面内の濃度のばらつきは小さくなり、抵抗値のば
らつきが小さくなる。 （２）ＶS ≧ｍ・ＶZ のとき（ツェナーダイオードは降
伏状態） ｐｎ接合の逆方向に過大な電流が流れ、その状態が長時
間続くと渦巻き状の薄膜層は発熱して破壊に至る。The zener voltage of each zener diode is V z , and p is the zener diode in the thin film layer.
Assuming that the number of pn junctions in an n-junction in the reverse blocking state is m, (1) When V S <m · V Z (Zener diode is in a non-breakdown state), the leakage current I S in the reverse direction of the pn junction is swirled. Flows into a thin film layer. Individual Zener diodes formed in polysilicon doped with a high concentration of impurities have relatively large leakage current I S and uniform voltage / current characteristics.
The spiral thin film layer has a uniform potential distribution along the spiral. Note that, when the impurity concentration is increased, the concentration control becomes easier, the variation in the in-plane concentration becomes smaller, and the variation in the resistance value becomes smaller. (2) When V S ≧ m · V Z (Zener diode is in a breakdown state) Excessive current flows in the reverse direction of the pn junction, and if the state continues for a long time, the spiral thin film layer generates heat and leads to destruction. .
【００２９】ツェナーダイオードの個数を増やして、半
導体装置の所望の耐圧より、渦巻き状の薄膜層に形成さ
れたツェナーダイオード全数を合わせたツェナー電圧を
高くなように設定すれば、前記の（１）項の非降伏状態
で使用できる。この非降伏状態でツェナーダイオードを
動作させることで、ツェナーダイオードを破壊させず
に、渦巻き状の薄膜層の電位分布を均一化できる。ま
た、渦巻き状の薄膜層を流れる漏れ電流はツェナーダイ
オードの逆阻止時の電圧・電流特性で決まり、この漏れ
電流は、ツェナーダイオードの数が変わらなければ、渦
巻き状の薄膜層の長さによる影響は少ない。つまり、薄
膜層の占める大きさによる影響は少ない。また、温度の
変化に対する、漏れ電流の変動も、従来の高抵抗の渦巻
き状の抵抗層の変動に比べて、大幅に小さく、安定した
電位分布が形成できる。If the number of Zener diodes is increased and the Zener voltage including the total number of Zener diodes formed in the spiral thin film layer is set to be higher than the desired breakdown voltage of the semiconductor device, the above-mentioned (1) It can be used in the non-yield state of the term. By operating the Zener diode in this non-breakdown state, the potential distribution of the spiral thin film layer can be made uniform without destroying the Zener diode. In addition, the leakage current flowing through the spiral thin film layer is determined by the voltage / current characteristics of the Zener diode during reverse blocking, and this leakage current is affected by the length of the spiral thin film layer if the number of Zener diodes does not change. Is less. That is, the influence of the size occupied by the thin film layer is small. Also, the fluctuation of the leakage current with respect to the change of the temperature is significantly smaller than that of the conventional high-resistance spiral-shaped resistance layer, and a stable potential distribution can be formed.
【００３０】図６は、渦巻き状の薄膜層に沿っての電界
分布で、同図（ａ）は電界分布の模式図で、図（ｂ）は
同図（ａ）の拡大図と渦巻き状の薄膜層の図で、同図
（ｃ）は電位分布を示す図である。同図（ａ）、（ｂ）
において、電界は渦巻き状の薄膜層に形成されたｐｎ接
合でＥMAX となり、空乏層が広がっていない箇所でＥ
MIN となる。また、ｐｎ接合が順バイアスされている箇
所でも小さな電界は存在するがそれは省略した。また、
ＥMIN は空乏層が広がらない領域での漏れ電極による電
圧降下で生ずる電界である。FIGS. 6A and 6B show the electric field distribution along the spiral thin film layer. FIG. 6A is a schematic view of the electric field distribution, and FIG. 6B is an enlarged view of FIG. FIG. 3C is a diagram showing a thin film layer, and FIG. Figures (a) and (b)
In, the electric field E MAX becomes at the pn junction formed in the spiral thin film layer, E at the point where the depletion layer does not spread
It becomes MIN . Although a small electric field is present even in a place where the pn junction is forward-biased, it is omitted. Also,
E MIN is an electric field generated by a voltage drop due to the leakage electrode in a region where the depletion layer does not spread.
【００３１】同図（ｃ）において、渦巻き状の薄膜層に
沿っての電位は、Ｖs からＧＮＤに向かった勾配が一定
となり、図７（ｂ）に示した理想的な電位分布となる。
拡大すると階段状に電位が降下しているが、ツェナーダ
イオードの数が多いため、極めて小さなステップとな
る。また、前記薄膜層を複数本形成すると、例えば、複
数本ある薄膜層の内１本が溶断しても、他の薄膜層で電
位分布の均一化を図ることができる。[0031] In FIG. (C), the potential along the spiral thin film layer, the slope is constant towards the GND from V s, an ideal potential distribution shown in FIG. 7 (b).
Although the potential drops stepwise when it is enlarged, the steps are extremely small due to the large number of zener diodes. When a plurality of thin film layers are formed, for example, even if one of the plurality of thin film layers is blown, the potential distribution can be made uniform in other thin film layers.
【００３２】[0032]
【発明の実施の形態】図１は、この発明の第１実施例の
半導体装置における耐圧構造部で、同図（ａ）は要部平
面図、同図（ｂ）は同図（ａ）のＡ−Ａ線で切断した要
部断面図である。この実施例では、外側の電極を基準
（ＧＮＤ）として、内側の島状に存在する電極に高電位
をかけるものとするが、これとは逆に、内側を基準にし
て、外側の電極に高電位をかける場合でも、渦巻き状の
薄膜層６の効果は同じである。1A and 1B show a breakdown voltage structure in a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of a main part, and FIG. 1B is a plan view of FIG. It is principal part sectional drawing cut | disconnected by the AA line. In this embodiment, the outer electrode is set as a reference (GND), and a high potential is applied to the inner island-shaped electrodes. Conversely, a high potential is applied to the outer electrode with the inner electrode as a reference. Even when a potential is applied, the effect of the spiral thin film layer 6 is the same.
【００３３】図１（ａ）において、プレーナ型の半導体
装置１は、その表面側表面の中心部に高電位側電極２
と、その高電位側電極２の外周側の低電位側電極３と、
高電位側電極２と低電位側電極３との間で高電位側電極
２の周囲を３重に周回して、高電位側電極２と低電位側
電極３とを電気的に接続する、第１導電形薄膜層４およ
び第２導電形薄膜層５の繰り返しからなる渦巻き状の薄
膜層６を有する。In FIG. 1A, a planar type semiconductor device 1 has a high potential side electrode 2
A low-potential-side electrode 3 on the outer peripheral side of the high-potential-side electrode 2;
A third round of the high potential side electrode 2 between the high potential side electrode 2 and the low potential side electrode 3 to electrically connect the high potential side electrode 2 and the low potential side electrode 3 It has a spiral thin film layer 6 composed of a repetition of a first conductivity type thin film layer 4 and a second conductivity type thin film layer 5.
【００３４】図１（ｂ）において、ｐ基板１０の表面層
にＮwell層９を形成し、Ｎwell層９の表面層にｎ形の高
電位領域８、ｐ形の低電位領域１２およびＰoffset領域
１４を形成する。また、ｐ基板１０の表面側には、絶縁
酸化膜１８を介して、第１導電形薄膜層４と第２導電形
薄膜層５の繰り返しからなる渦巻き状薄膜層６で形成さ
れる。この渦巻き状の薄膜層６のＡ−Ａ線にある箇所を
１５、１６、１７として示す。[0034] In FIG. 1 (b), p the N well layer 9 is formed on the surface layer of the substrate 10, the high potential region 8 of the n-type surface layer of the N well layer 9, p-type low potential region 12 and P An offset area 14 is formed. On the surface side of the p-substrate 10, a spiral thin film layer 6 formed by repeating the first conductivity type thin film layer 4 and the second conductivity type thin film layer 5 is formed via an insulating oxide film 18. The portions on the AA line of the spiral thin film layer 6 are shown as 15, 16, and 17.
【００３５】一方、ｐ基板１０の裏面側には、裏面側電
極１１を形成する。低電位側電極３はチップ終端部にあ
り、この終端部のダイシング面５６には歪み層が形成さ
れ、この歪み層で、電圧阻止能力がなくなるために、低
電位側電極３と裏面側電極１１は電気的に接続され、共
に電位的にＧＮＤとなる。勿論、このダイシング面５６
に加え、チップ終端部の露出面全体をｐ層とすること
で、低電位側電極３と裏面側電極１１をさらに強く電気
的に接続させることができる。On the other hand, on the back side of the p substrate 10, a back side electrode 11 is formed. The low-potential-side electrode 3 is located at the terminal end of the chip, and a strained layer is formed on the dicing surface 56 at the end of the chip. Are electrically connected, and both are electrically GND. Of course, this dicing surface 56
In addition, by making the entire exposed surface of the chip end portion a p-layer, the low potential side electrode 3 and the back side electrode 11 can be electrically connected more strongly.
【００３６】前記の渦巻き状の薄膜層６は、例えば、ノ
ンドープのポリシリコンに第１導電形および第２導電形
の不純物を導入して、第１導電形薄膜層４および第２導
電形薄膜層５を交互に形成して得ることができる。ま
た、別の例として、第１導電形ポリシリコンに第２導電
形不純物を選択的に離して導入して、第１導電形薄膜層
４および第２導電形薄膜層５を交互に形成して得ること
もできる。例えば、第１導電形薄膜層４をｎ層とし、第
２導電形薄膜層５をｐ層とした場合のｐｎダイオードの
逆直列状態を５１に示す。尚、図では白抜き部が第１導
電形薄膜層４で、ハッチング部が第２導電形薄膜層５と
して示したが、書き切れないので、矢印イの方向に一つ
置きに示されるハッチング部を省略した。The spiral thin film layer 6 is formed, for example, by introducing impurities of the first conductivity type and the second conductivity type into non-doped polysilicon to form the first conductivity type thin film layer 4 and the second conductivity type thin film layer. 5 can be obtained alternately. Further, as another example, a second conductivity type impurity is selectively introduced into the first conductivity type polysilicon at a distance, and the first conductivity type thin film layers 4 and the second conductivity type thin film layers 5 are alternately formed. You can also get. For example, 51 shows an anti-series state of a pn diode when the first conductivity type thin film layer 4 is an n layer and the second conductivity type thin film layer 5 is a p layer. In the drawing, the white portion is the first conductivity type thin film layer 4 and the hatched portion is the second conductivity type thin film layer 5, but since the writing is not complete, the hatching portions shown alternately in the direction of arrow a. Was omitted.
【００３７】この構造において、低電位側電極３を基準
にして、高電位側電極２に正電位Ｖ S を印加すると、渦
巻き状の薄膜層６の高電位側電極２と接続する端にも電
位Ｖ S が印加され、この渦巻き状の薄膜層には均一な電
位分布が形成される。図２は、チップ表面の電位分布の
様子を示めしたもので、同図（ａ）は半導体装置の要部
断面図、同図（ｂ）はチップ表面の電位分布である。電
位勾配が生ずる箇所はＰoffset層表面である。In this structure, the low potential side electrode 3 is used as a reference.
And the positive potential V is applied to the high potential side electrode 2. SVortex
The end connected to the high potential side electrode 2 of the wound thin film layer 6 is also charged.
Rank V SIs applied, and a uniform electric current is applied to the spiral thin film layer.
An order distribution is formed. FIG. 2 shows the potential distribution on the chip surface.
FIG. 1A shows the main part of a semiconductor device.
FIG. 4B is a cross-sectional view, showing the potential distribution on the chip surface. Electric
The point where the phase gradient occurs is PoffsetIt is a layer surface.
【００３８】同図（ａ）は図１（ｂ）の上部を描いた図
である。また同図（ｂ）は図１（ａ）のＡ−Ａ線上に沿
って、高電位側電極２から低電位側電極３に向かっての
電位分布を示した図である。渦巻き状の薄膜層６をＡ−
Ａ線で切断した断面で表すと１５、１６、１７で示され
る。この渦巻き状の薄膜層１５、１６、１７にかかる電
位をＶ15、Ｖ16、Ｖ17とする。高電位側電極２から低電
位側電極３に向かっての電位は、平均的な勾配が一定と
なる。そのため、Ｎwell層９、Ｐoffset層１４および図
示しないｐ基板層１０ａに形成される空乏層内の電界は
緩和され、半導体装置１を高耐圧化することができる。FIG. 1A is a diagram illustrating the upper part of FIG. 1B. FIG. 2B is a diagram showing a potential distribution from the high potential side electrode 2 to the low potential side electrode 3 along the line AA in FIG. The spiral thin film layer 6 is
When expressed in a cross section cut along the line A, they are indicated by 15, 16, and 17. The potential of this spiral thin film layer 15, 16, 17 and V 15, V 16, V 17 . The average gradient of the potential from the high potential side electrode 2 to the low potential side electrode 3 is constant. Therefore, the electric field in the depletion layer formed in N well layer 9, P offset layer 14, and p substrate layer 10a (not shown) is reduced, and semiconductor device 1 can have a high breakdown voltage.
【００３９】つぎに、渦巻き状の薄膜層６に沿って、印
加される電位について図１（ａ）を用いて説明する。半
導体装置の耐圧が、例えば、６００Ｖの場合、ツェナー
ダイオードを形成するｐｎ接合５５で、逆阻止状態にあ
るｐｎ接合５５の数をｍ＝４００個、接合部ダイオード
の降伏電圧であるツェナー電圧を全て等しく、ＶZ ＝４
Ｖとなるようツェナーダイオードの耐圧を設定する。こ
うすると、ツェナーダイオードの全電圧＝４Ｖ×４００
＝１６００Ｖとなり、半導体装置１の耐圧６００Ｖに対
して十分余裕があり、ツェナーダイオードが降伏するこ
とはなく、従って、発熱で破壊することもない。また、
一個のツェナーダイオードに印加される電圧は６００Ｖ
÷４００＝１．５Ｖと低く、高電位側電極２から低電位
側電極３に、渦巻き状の薄膜層６に沿って、この１．５
Ｖの電位ステップで電位は均一に低下し、均一な電位分
布が得られる。Next, the potential applied along the spiral thin film layer 6 will be described with reference to FIG. When the breakdown voltage of the semiconductor device is, for example, 600 V, the number of the pn junctions 55 in the reverse blocking state is m = 400 in the pn junction 55 forming the Zener diode, and the Zener voltage which is the breakdown voltage of the junction diode is all Equal, V Z = 4
The withstand voltage of the Zener diode is set to be V. In this case, the total voltage of the Zener diode = 4V × 400
= 1600V, which is sufficient for the withstand voltage 600V of the semiconductor device 1, and the Zener diode does not break down and therefore does not break down due to heat generation. Also,
The voltage applied to one Zener diode is 600V
÷ 400 = 1.5 V, which is 1.5 V along the spiral thin film layer 6 from the high potential side electrode 2 to the low potential side electrode 3.
At the V potential step, the potential decreases uniformly, and a uniform potential distribution is obtained.
【００４０】また、前記のＶZ を７Ｖに設定した場合
は、ｍが２３０個程度で、一個のツェナーダイオードに
印加される電圧が２．６Ｖ程度と低くなり、高電位側電
極２から低電位側電極３に、渦巻き状の薄膜層６に沿っ
て、この２．６Ｖの電位ステップで電位は均一に低下
し、均一な電位分布が得られることになる。ツェナーダ
イオードを形成するポリシリコンの濃度（第１導電形薄
膜層の濃度および第２導電形薄膜層の濃度）は高いため
に、ツェナーダイオードの電圧・電流特性のばらつきは
小さくなる。実測では、漏れ電流に対する各ツェナーダ
イオードが分担する電圧のばらつきは１０％以内で、渦
巻き状の薄膜層に沿う電位分布の均一性は、ポリシリコ
ンの濃度を高めることで向上する。Further, if you set the aforementioned V Z to 7V is, m with about 230 pieces, the voltage applied to one of the zener diode is as low as about 2.6V, a low potential from the high voltage electrode 2 In the side electrode 3, along the spiral thin film layer 6, the potential drops uniformly in this 2.6 V potential step, and a uniform potential distribution can be obtained. Since the concentration of the polysilicon forming the Zener diode (the concentration of the first conductivity type thin film layer and the concentration of the second conductivity type thin film layer) is high, the variation in the voltage / current characteristics of the Zener diode becomes small. In the actual measurement, the variation of the voltage shared by each Zener diode with respect to the leakage current is within 10%, and the uniformity of the potential distribution along the spiral thin film layer is improved by increasing the concentration of polysilicon.
【００４１】従って、ツェナーダイオードを降伏させる
ことなく、渦巻き状の薄膜層６に沿って安定した電位分
布を得ることができ、半導体装置の耐圧を向上できる。
また、図１では、渦巻き状の薄膜層６を内側の高電位側
電極２の周囲を３重に周回としたが、特に、チップサイ
ズや半導体装置１の耐圧で周回の回数は変わる。但し、
周回の回数が多い程、高電位側電極２と低電位側電極３
を直線で結ぶ線上（例えばＡ−Ａ線上）の電位分布の均
一性が向上するので好ましい。Accordingly, a stable potential distribution can be obtained along the spiral thin film layer 6 without causing breakdown of the Zener diode, and the withstand voltage of the semiconductor device can be improved.
In FIG. 1, the spiral thin film layer 6 is wound around the inner side of the high-potential-side electrode 3 three times. However, the number of times of winding changes in particular depending on the chip size and the breakdown voltage of the semiconductor device 1. However,
The higher the number of turns, the higher the potential 2 and the lower potential 3
This is preferable because the uniformity of the potential distribution on a line connecting the lines (for example, on the line AA) is improved.
【００４２】また、ツェナーダイオードの個数もここで
は４００個としたが、全体のツェナー電圧が半導体装置
１の耐圧以上になるように個数を設定すればよい。ま
た、渦巻き状の薄膜層６の形状もこの渦巻き状の薄膜層
６が取り巻く電極形状（例えば、高電位側電極２の形
状）に合わせてよく、円形でも多角形でもよい。さら
に、渦巻き状の薄膜層６の材質についは、この実施例で
はポリシリコンとしたが、単結晶シリコンやＧａＡｓお
よびＳｉＣなどの半導体材料を用いてもよい。また、始
点から終点に達する渦巻きの本数は、実施例では１本で
示したが、複数本、並設しても構わない。Although the number of Zener diodes is 400 here, the number may be set so that the overall Zener voltage is equal to or higher than the breakdown voltage of the semiconductor device 1. In addition, the shape of the spiral thin film layer 6 may conform to the shape of the electrode (for example, the shape of the high-potential-side electrode 2) surrounding the spiral thin film layer 6, and may be circular or polygonal. Furthermore, although the material of the spiral thin film layer 6 is polysilicon in this embodiment, single crystal silicon or a semiconductor material such as GaAs and SiC may be used. Although the number of spirals from the start point to the end point is one in the embodiment, a plurality of spirals may be arranged in parallel.
【００４３】前記した実施例は、ｐｎダイオードが逆直
列に多数接続された例である。つぎに、ｐｎダイオード
が順直列に接続され実施例を説明する。図３は、この発
明の第２実施例の半導体装置における耐圧構造部の要部
平面図である。この図は、渦巻き状の薄膜層６に形成さ
れるｐｎ接合５５を一つ置きに金属膜５３で短絡し、す
べてのツェナーダイオードであるｐｎダイオードが順直
列に形成されている点が図１（ａ）と異なる。この金属
膜５３の材質はアルミニウムなど、デバイスの電極を形
成するときに用いる材質でよい。また、形成されるｐｎ
ダイオードは、図中の５２に示すように逆阻止状態とな
るように、順方向のｐｎ接合上に金属膜５３を形成す
る。尚、矢印ロの方向で、金属膜５３がｐｎ接合５５が
一つ置きに配置されるが、省略した。The above embodiment is an example in which a large number of pn diodes are connected in anti-series. Next, an embodiment in which pn diodes are connected in series will be described. FIG. 3 is a plan view of a main part of a breakdown voltage structure in a semiconductor device according to a second embodiment of the present invention. This figure shows that every other pn junction 55 formed in the spiral thin film layer 6 is short-circuited by the metal film 53, and that all the pn diodes which are zener diodes are formed in series with FIG. Different from a). The material of the metal film 53 may be aluminum or another material used when forming electrodes of the device. Also, the pn to be formed
The metal film 53 is formed on the pn junction in the forward direction so that the diode is in a reverse blocking state as indicated by 52 in the drawing. In the direction of arrow B, the metal film 53 is disposed every other pn junction 55, but is omitted.
【００４４】前記した第１実施例では、横型のプレーナ
型の半導体装置の耐圧構造部を示したが、縦型の半導体
装置の耐圧構造の場合でも、チップの活性領域から、横
方向に空乏層が拡張していくタイプの半導体装置では、
前記したツェナーダイオードの繰り返しからなる渦巻き
状の薄膜層が適用できる。つぎに、縦型の半導体装置に
渦巻き状の薄膜層を適用した実施例について説明する。In the above-described first embodiment, the breakdown voltage structure of the horizontal planar type semiconductor device has been described. However, even in the case of the breakdown voltage structure of the vertical semiconductor device, the depletion layer extends in the lateral direction from the active region of the chip. In the type of semiconductor devices that are expanding,
A spiral thin film layer formed by repeating the above-described Zener diode can be applied. Next, an embodiment in which a spiral thin film layer is applied to a vertical semiconductor device will be described.
【００４５】図４は、この発明の第３実施例の半導体装
置における耐圧構造部の要部断面図である。ｎ- 層２３
の裏面側にｎ+ 層２２を形成し、表面側に低電位領域２
５となるｐウエル領域、この低電位領域を取り囲むよう
にガードリングとなるｐ領域２９、３０、３１をそれぞ
れ形成し、チップの終端部には、高電位領域２０となる
ｐ領域を形成する。低電位領域２５となるｐウエル領域
には図示しない活性領域（例えば、ＭＯＳＦＥＴでいう
とゲート部やソース部が占めている領域のこと）が形成
される。低電位領域２５上に低電位側電極２６、高電位
領域２０上に高電位側電極１９が形成され、裏面のｎ+
層上には裏面側電極２１が形成される。裏面側電極２１
と高電位側電極１９はダイシング面４５で電気的に接続
されている。FIG. 4 is a sectional view showing a main part of a breakdown voltage structure in a semiconductor device according to a third embodiment of the present invention. n - layer 23
N + layer 22 is formed on the back side of
A p-well region to be 5 and p-regions 29, 30, and 31 to be guard rings are formed so as to surround the low-potential region, and a p-region to be a high-potential region 20 is formed at the end of the chip. An active region (not shown) (for example, a region occupied by a gate portion and a source portion in a MOSFET) is formed in the p-well region serving as the low potential region 25. The low potential side electrode 26 on the low potential region 25, the high-potential-side electrode 19 is formed on the high potential region 20, the back surface of the n +
A back side electrode 21 is formed on the layer. Back side electrode 21
The high potential side electrode 19 is electrically connected to the dicing surface 45.
【００４６】また、ガードリングのｐ領域２９、３０、
３１は、ｐウエル領域２５をリング状に取り囲んでい
る。高電位側電極１９と低電位側電極２６とを電気的に
接続する渦巻き状の薄膜層２７が半導体基板上の絶縁酸
化膜２８を介して形成されている。ここで、裏面側電極
２１に電位ＶS をかけると、高電位側電極１９と低電位
側電極２６の間に、電位ＶS がかかり、ツェナーダイオ
ードの直列接続構造となっている渦巻き状の薄膜層２７
には、漏れ電流が流れて、電位分布が形成される。この
電位分布による電界が、半導体基板に形成される空乏層
２４を均一に広げ、電界集中を緩和し、半導体装置の耐
圧を向上させる。The guard ring p regions 29, 30,
Reference numeral 31 surrounds the p-well region 25 in a ring shape. A spiral thin film layer 27 for electrically connecting the high potential side electrode 19 and the low potential side electrode 26 is formed via an insulating oxide film 28 on a semiconductor substrate. Here, when applying a potential V S to the rear surface side electrode 21, between a high-potential-side electrode 19 the low-potential electrode 26, it takes the potential V S, spiral thin film which has a series-connection structure of a Zener diode Layer 27
, A leakage current flows to form a potential distribution. The electric field due to this potential distribution uniformly spreads the depletion layer 24 formed on the semiconductor substrate, reduces the electric field concentration, and improves the breakdown voltage of the semiconductor device.
【００４７】この発明の第４実施例の半導体装置で、図
１の渦巻き状の薄膜層を形成する第１導電形層および第
２導電形層の不純物濃度がそれぞれ１×１０18ｃｍ-3以
上にする。このように不純物濃度を高くすることで、第
１導電形薄膜層と第２導電形薄膜層で形成されるｐｎダ
イオードはツェナーダイオードとなる。これらの第１導
電形薄膜層と第２導電形薄膜層の不純物濃度を高くする
ことで、ツェナーダイオードの逆阻止時の電圧・電流特
性のばらつきを小さく抑制でき、渦巻き状の薄膜層に沿
って均一な電位勾配を形成できる。また、渦巻き状の薄
膜層にツェナーダイオード群を形成することで、抵抗性
の薄膜層と比べて、電位分布の温度依存性を小さくでき
る。In the semiconductor device according to the fourth embodiment of the present invention, the first conductive type layer and the second conductive type layer forming the spiral thin film layer of FIG. 1 each have an impurity concentration of 1 × 10 18 cm −3 or more. To By increasing the impurity concentration in this way, the pn diode formed by the first conductive type thin film layer and the second conductive type thin film layer becomes a Zener diode. By increasing the impurity concentration of the first conductivity type thin film layer and the second conductivity type thin film layer, the variation of the voltage / current characteristics at the time of reverse blocking of the Zener diode can be suppressed to be small, and along the spiral thin film layer. A uniform potential gradient can be formed. Further, by forming the Zener diode group on the spiral thin film layer, the temperature dependence of the potential distribution can be reduced as compared with the resistive thin film layer.
【００４８】この発明の第４実施例の半導体装置で、半
導体基板上に、絶縁酸化膜を介して渦巻き状の薄膜層を
形成する場合の絶縁酸化膜の膜厚を０．０１から１０μ
ｍとする。０．０１μｍより薄い場合は、製造条件のば
らつきなどで半導体基板と渦巻き状の薄膜層が接触する
場合が生ずる恐れが出てくる。一方、１０μｍを超える
と、絶縁酸化膜の形成に長時間かかかり、半導体基板上
に形成される絶縁酸化膜の厚さが厚くなりすぎて、渦巻
き状の薄膜層の電位を効果的に半導体基板の表面に伝え
にくくなる。そのため、デバイス構造としては好ましく
ない。また、製造コストも当然上昇する。In the semiconductor device according to the fourth embodiment of the present invention, when forming a spiral thin film layer on a semiconductor substrate via an insulating oxide film, the thickness of the insulating oxide film is set to 0.01 to 10 μm.
m. If the thickness is less than 0.01 μm, there is a possibility that the spiral wound thin film layer may come into contact with the semiconductor substrate due to variations in manufacturing conditions. On the other hand, if the thickness exceeds 10 μm, it takes a long time to form the insulating oxide film, the thickness of the insulating oxide film formed on the semiconductor substrate becomes too thick, and the potential of the spiral thin film layer is effectively reduced. It is difficult to convey to the surface. Therefore, it is not preferable as a device structure. In addition, the manufacturing cost naturally increases.
【００４９】前記のように、この発明の渦巻き状の薄膜
層は、ツェナーダイオードの繰り返し構造となってお
り、逆阻止状態にあるダイオードの個数ｍと個々のツェ
ナーダイオードのツェナー電圧ＶZ の積（ｍ×ＶZ ）が
半導体装置の耐圧より十分大きいように設計しておけ
ば、高電位側電極と低電位側電極間に耐圧以下の電圧を
印加したとき、渦巻き状の薄膜層には、ダイオードの逆
方向の漏れ電流ＩS が流れ、薄膜層に沿って均一な電位
分布が生じ、それに従って、第１導電形薄膜層もしくは
第２導電形薄膜層で、キャリアの移動が起こり、空乏層
が拡張する。これによって、電界集中が緩和され、耐圧
を向上できる。As described above, the spiral thin film layer of the present invention has a repeating structure of a Zener diode, and the product (m) of the number m of the diodes in the reverse blocking state and the Zener voltage V Z of each Zener diode. m × V Z ) is designed to be sufficiently higher than the withstand voltage of the semiconductor device. When a voltage lower than the withstand voltage is applied between the high-potential side electrode and the low-potential side electrode, the spiral thin film layer includes a diode. Leakage current I S flows in the opposite direction, and a uniform potential distribution occurs along the thin film layer. Accordingly, carriers move in the first conductivity type thin film layer or the second conductivity type thin film layer, and a depletion layer is formed. Expand. Thereby, the electric field concentration is reduced, and the withstand voltage can be improved.
【００５０】従来のフィールドプレートや渦巻き状の抵
抗層に比べ、この発明は、渦巻き状の薄膜層の第１導電
形もしくは第２導電形の不純物濃度、ツェナーダイオー
ドの個数、薄膜層の材質の最適化によって、薄膜層の大
きさ（幅、長さ）や温度の変化による漏れ電流ＩS の変
動を大幅に小さくでき、安定した耐圧を得ることができ
る。Compared with the conventional field plate and the spiral resistive layer, the present invention optimizes the impurity concentration of the first or second conductive type of the spiral thin film layer, the number of Zener diodes, and the material of the thin film layer. As a result, fluctuations in the leakage current I S due to changes in the size (width, length) and temperature of the thin film layer can be significantly reduced, and a stable breakdown voltage can be obtained.
【００５１】図１０は、この発明の第５実施例の半導体
装置における耐圧構造部の要部平面図である。薄膜層が
４本渦巻き状に形成されている。渦巻き状の薄膜層は第
１導電形薄膜層と第２導電形薄膜層から形成され、図１
（ａ）との違いは、渦巻き状の薄膜層が複数本（図１０
では、第１渦巻き状の薄膜層６ａ、第２渦巻き状の薄膜
層６ｂ、第３渦巻き状の薄膜層６ｃおよび第４渦巻き状
の薄膜層６ｄの４本）形成されている点である。薄膜層
を複数本とすることで、例えば、１本の薄膜層が切れて
も、他の健全な薄膜層によって電位分布の均一化が図ら
れて、素子耐圧に対する信頼性が向上する。FIG. 10 is a plan view of a main part of a breakdown voltage structure in a semiconductor device according to a fifth embodiment of the present invention. Four thin film layers are formed in a spiral shape. The spiral thin film layer is formed of a first conductivity type thin film layer and a second conductivity type thin film layer.
The difference from (a) is that a plurality of spiral thin film layers (FIG. 10)
Is that the first spiral-shaped thin film layer 6a, the second spiral-shaped thin film layer 6b, the third spiral-shaped thin film layer 6c, and the fourth spiral-shaped thin film layer 6d are formed. By using a plurality of thin film layers, for example, even if one thin film layer breaks, the potential distribution is made uniform by another healthy thin film layer, and the reliability with respect to the element withstand voltage is improved.
【００５２】尚、第５実施例の半導体装置の要部断面図
およびチップ表面の電位分布の様子は、図２（ａ）およ
び（ｂ）と同じであるので説明を省略する。図１１は、
この発明の第６実施例の半導体装置における要部断面図
である。これは、第１実施例で示した耐圧構造を高耐圧
横形ＮＭＯＳ（ｎチャネルＭＯＳＦＥＴ）に適用した例
である。The sectional view of the main part of the semiconductor device of the fifth embodiment and the state of the potential distribution on the chip surface are the same as those shown in FIGS. FIG.
FIG. 16 is a sectional view of a main part of a semiconductor device according to a sixth embodiment of the present invention. This is an example in which the breakdown voltage structure shown in the first embodiment is applied to a high breakdown voltage lateral NMOS (n-channel MOSFET).
【００５３】ｐ基板５７のＮwell領域５８を形成し、Ｎ
well領域５８の表面層に選択的にｐ - 領域６０、Ｐ
offset領域６７を形成し、また、Ｐwell領域６１、６４
を形成する。つぎに、絶縁酸化膜６９、７０であるＬＯ
ＣＯＳ（Ｌｏｃａｌ Ｏｘｉｄａｔｉｏｎ ｏｆ Ｓｉ
ｌｉｃｏｎ）を形成する。そのつぎに、図示しないゲー
ト酸化膜を介してポリシリコンでゲート電極７２を形成
し、絶縁酸化膜７０上にポリシリコン膜７５、８４およ
び渦巻き状の薄膜層を形成する。この渦巻き状の薄膜層
８３は第１実施例で説明したものと同等である。当然、
前記したように、この渦巻き状の薄膜層８３は多数のｐ
ｎダイオード（ツェナーダイオードなど）で構成されて
いる。N of p substrate 57wellForming a region 58, N
wellThe surface layer of region 58 is selectively p -Region 60, P
offsetForming a region 67;wellRegions 61 and 64
To form Next, the insulating oxide films 69 and 70
COS (Local Oxidation of Si)
licon). Next, a game (not shown)
The gate electrode 72 is formed with polysilicon through the oxide film
Then, polysilicon films 75, 84 and
Then, a spiral thin film layer is formed. This spiral thin film layer
Reference numeral 83 is the same as that described in the first embodiment. Of course,
As described above, the spiral thin film layer 83 has a large number of p.
composed of n diodes (such as zener diodes)
I have.
【００５４】つぎに、ソース領域となるｎ+ 領域６３、
６５、ドレイン領域となるｎ+ 領域６８を形成し、この
とき、渦巻き状の薄膜層８３の図示しないｎ+ 領域も形
成し、またフィールドプレートとなるポリシリコン膜７
５、８４をｎ形の低抵抗層とする。つぎに、コンタクト
をとるために、ｐ+ 領域５９、６２、６６を形成し、こ
のとき、渦巻き状の薄膜層８３の図示しないｐ+ 領域も
形成する。Next, an n + region 63 serving as a source region,
65, an n + region 68 serving as a drain region is formed. At this time, an n + region (not shown) of the spiral thin film layer 83 is also formed, and the polysilicon film 7 serving as a field plate is formed.
5, 84 are n-type low resistance layers. Next, in order to make contact, p + regions 59, 62, and 66 are formed. At this time, p + regions (not shown) of the spiral thin film layer 83 are also formed.
【００５５】つぎに、図示しないＰＳＧ（リン・ガラ
ス）などの絶縁膜を表面に被覆し、コンタクト孔を形成
した後、ソース電極７１、７３およびドレイン電極７４
を形成し、裏面に裏面側電極８５を形成する。この高耐
圧横型ＮＭＯＳは、オン状態のとき、主電流である電子
流が活性領域２０１を、ソース側（ｎ+ 領域６３、６
５）からドレイン側（ｎ+ 領域６８）に流れる構造であ
る。渦巻き状の薄膜層８３が、主電流が流れる活性領域
２０１の上に形成されていることで、阻止状態でのドレ
イン側からソース側への電位分布を均一化できて、素子
耐圧の信頼性を向上させることができる。さらに、ソー
ス・ドレイン間の距離が低減できて、オン抵抗の低減を
図ることができると共に、素子占有面積を小さくできる
利点も生じる。Next, after covering the surface with an insulating film such as PSG (phosphorus glass) (not shown) and forming contact holes, the source electrodes 71 and 73 and the drain electrode 74 are formed.
Is formed, and the back surface side electrode 85 is formed on the back surface. In the high-breakdown-voltage lateral NMOS, when in the ON state, the electron current, which is the main current, flows through the active region 201 to the source side (n + regions 63, 6).
This is a structure that flows from 5) to the drain side (n + region 68). Since the spiral thin film layer 83 is formed on the active region 201 through which the main current flows, the potential distribution from the drain side to the source side in the blocking state can be made uniform, and the reliability of the element withstand voltage can be improved. Can be improved. Further, the distance between the source and the drain can be reduced, the on-resistance can be reduced, and the element occupied area can be reduced.
【００５６】図１２は、この発明の第７実施例の半導体
装置における要部断面図である。これは、第１実施例で
示した耐圧構造を、高耐圧横型ＰＭＯＳ（ｐチャネルＭ
ＯＳＦＥＴ）に適用した例である。ここでは、構造の詳
細な説明は省略するが、渦巻き状の薄膜層１０４は、図
１１と同様に、活性領域２０２の上に形成されている。
この場合も第６実施例で説明した効果と同様の効果が期
待できる。FIG. 12 is a sectional view showing a main part of a semiconductor device according to a seventh embodiment of the present invention. This is because the breakdown voltage structure shown in the first embodiment is changed to a high breakdown voltage lateral PMOS (p-channel M
OSFET). Although a detailed description of the structure is omitted here, the spiral thin film layer 104 is formed on the active region 202 as in FIG.
In this case, the same effect as that described in the sixth embodiment can be expected.
【００５７】[0057]
【発明の効果】この発明によれば、島状領域の周囲を外
周部に向かって周回し、高電位領域と低電位領域を電気
的に接続する渦巻き状の薄膜層を、ツェナーダイオード
の繰り返しにより構成することで、つぎのような効果が
ある。耐圧構造部の耐圧は、ツェナーダイオードの数で
決まり、薄膜層の幅に対する依存性は極めて小さく、そ
のため、同一耐圧ではチップサイズに渦巻き状の幅を一
定にできる。このことによって、同一耐圧の素子系列を
製造する場合、製造コストが、従来の抵抗薄膜層（フィ
ールドプレートや渦巻き状の抵抗薄膜層）に比べて大幅
に低減できる。According to the present invention, the spiral thin film layer which goes around the island region toward the outer periphery and electrically connects the high potential region and the low potential region is formed by repeating the zener diode. The configuration has the following effects. The breakdown voltage of the breakdown voltage structure is determined by the number of Zener diodes, and has a very small dependence on the width of the thin film layer. Therefore, at the same breakdown voltage, the spiral width can be made constant in the chip size. As a result, when manufacturing an element series having the same withstand voltage, the manufacturing cost can be greatly reduced as compared with a conventional resistance thin film layer (a field plate or a spiral resistance thin film layer).
【００５８】また、ツェナーダイオードの逆耐圧特性を
利用しているので、温度依存性が小さいく、そのため、
耐圧を安定して得ることができる。また渦巻き状の薄膜
層を形成するポリシリコンの不純物濃度を１×１０18ｃ
ｍ -3以上と高濃度とすることで、個々のツェナーダイオ
ードの電圧・電流特性を揃えることができる。そうする
ことで、高電位領域から低電位領域への電位勾配を均一
化し、高い耐圧を得ることができる。The reverse withstand voltage characteristic of the Zener diode is
The temperature dependence is small because it is used.
Withstand voltage can be obtained stably. Spiral thin film
The impurity concentration of the polysilicon forming the layer is 1 × 1018c
m -3With the above high concentration, individual zener diodes
The voltage and current characteristics of the circuit can be made uniform. Do so
Uniform potential gradient from high-potential region to low-potential region
And a high withstand voltage can be obtained.
【００５９】また、薄膜層を複数本とすることで、素子
耐圧に対する信頼性が向上する。By using a plurality of thin film layers, the reliability with respect to the element withstand voltage is improved.
【図１】この発明の第１実施例の半導体装置における耐
圧構造部で、（ａ）は要部平面図、（ｂ）は同図（ａ）
のＡ−Ａ線で切断した要部断面図FIGS. 1A and 1B show a breakdown voltage structure of a semiconductor device according to a first embodiment of the present invention, wherein FIG.
Sectional view taken along line AA of FIG.
【図２】チップ表面の電位分布の様子を示めしたもの
で、（ａ）は半導体装置の要部断面図、（ｂ）はチップ
表面の電位分布図FIGS. 2A and 2B show a state of a potential distribution on a chip surface, wherein FIG. 2A is a cross-sectional view of a main part of a semiconductor device, and FIG.
【図３】この発明の第２実施例の半導体装置における耐
圧構造部の要部平面図FIG. 3 is a plan view of a main part of a breakdown voltage structure in a semiconductor device according to a second embodiment of the present invention;
【図４】この発明の第３実施例の半導体装置における耐
圧構造部の要部断面図FIG. 4 is a sectional view of a main part of a breakdown voltage structure in a semiconductor device according to a third embodiment of the present invention;
【図５】ポリシリコンを用いたツェナーダイオードの電
圧・電流特性を示す図FIG. 5 is a diagram showing voltage-current characteristics of a Zener diode using polysilicon.
【図６】渦巻き状の薄膜層に沿っての電界分布で、
（ａ）は電界分布の模式図で、（ｂ）は（ａ）の拡大図
と渦巻き状の薄膜層の図で、（ｃ）は電位分布を示す図FIG. 6 shows an electric field distribution along a spiral thin film layer,
(A) is a schematic diagram of an electric field distribution, (b) is an enlarged view of (a) and a diagram of a spiral thin film layer, and (c) is a diagram showing a potential distribution.
【図７】従来の耐圧構造部である、Ｄｏｕｂｌｅ ＲＥ
ＳＵＲＦ構造と抵抗性フィールドプレート構造を組み合
わせた構造で、（ａ）は要部断面図、（ｂ）は電位分布
図FIG. 7 shows a conventional withstand voltage structure, Double RE.
A structure combining a SURF structure and a resistive field plate structure. (A) is a sectional view of a main part, and (b) is a potential distribution diagram.
【図８】半導体内部の空乏層の拡がりを示した図FIG. 8 is a diagram showing the expansion of a depletion layer inside a semiconductor;
【図９】従来の耐圧構造部で、渦巻き状の薄膜抵抗層４
５の要部平面図FIG. 9 shows a conventional thin-film resistance layer 4 having a spiral structure and a spiral structure.
5 main part plan view
【図１０】この発明の第５実施例の半導体装置における
耐圧構造部の要部平面図FIG. 10 is a plan view of a main part of a breakdown voltage structure in a semiconductor device according to a fifth embodiment of the present invention;
【図１１】この発明の第６実施例の半導体装置における
要部断面図FIG. 11 is a sectional view showing a main part of a semiconductor device according to a sixth embodiment of the present invention;
【図１２】この発明の第７実施例の半導体装置における
要部断面図FIG. 12 is a sectional view showing a main part of a semiconductor device according to a seventh embodiment of the present invention;
１ 半導体装置 ２ 高電位側電極 ３ 低電位側電極 ４ 第１導電形薄膜層 ５ 第２導電形薄膜層 ６ 渦巻き状の薄膜層 ６ａ〜６ｄ 第１〜第４渦巻き状の薄膜層 ８ 高電位領域 ９ Ｎwell領域 １０ ｐ基板 １０ａ ｐ基板層 １１ 裏面側電極 １２ 低電位領域 １４ Ｐoffset領域 １５、１６、１７ 渦巻き状の薄膜層 １８ 絶縁酸化膜 １９ 高電位側電極 ２０ 高電位領域 ２１ 裏面側電極 ２２ ｎ+ 層 ２３ ｎ- 層 ２４ 空乏層 ２５ 低電位領域 ２６ 低電位側電極 ２７ 渦巻き状の薄膜層 ２８ 絶縁酸化膜 ２９、３０、３１ ｐ領域 ５３ 金属膜 ５５ ｐｎ接合 ５６ ダイシング面DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 High potential side electrode 3 Low potential side electrode 4 1st conductivity type thin film layer 5 2nd conductivity type thin film layer 6 Spiral thin film layer 6a-6d 1st-4th spiral thin film layer 8 High potential area 9 N well region 10 p substrate 10 a p substrate layer 11 backside electrode 12 low potential region 14 P offset region 15, 16, 17 spiral thin film layer 18 insulating oxide film 19 high potential side electrode 20 high potential region 21 backside electrode Reference Signs List 22 n + layer 23 n − layer 24 depletion layer 25 low potential region 26 low potential side electrode 27 spiral thin film layer 28 insulating oxide film 29, 30, 31 p region 53 metal film 55 pn junction 56 dicing surface
【手続補正書】[Procedure amendment]
【提出日】平成１２年１月３１日（２０００．１．３
１）[Submission date] January 31, 2000 (200.1.3
1)
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Correction target item name] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【特許請求の範囲】[Claims]
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００６[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【０００６】１つのｐｎ接合は、Ｎwell領域３４とＰ
offset領域３９、低電位領域３７のｐｎ接合であり、も
う一つのｐｎ接合は、Ｎwell領域３４とｐ基板層３５ａ
のｐｎ接合である。一般的に、絶縁酸化膜４１と半導体
界面の固定電荷の影響で、半導体表面の空乏層内部には
電界の集中が起き易く、これがデバイスの破壊につなが
る。[0006] One pn junction is composed of an N well region 34 and a P well.
The offset region 39 is a pn junction of the low potential region 37, and the other pn junction is composed of the N well region 34 and the p substrate layer 35a.
Pn junction. Generally, an electric field tends to concentrate inside the depletion layer on the semiconductor surface due to the effect of fixed charges at the interface between the insulating oxide film 41 and the semiconductor, which leads to destruction of the device.
【手続補正３】[Procedure amendment 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２３[Correction target item name] 0023
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２３】前記半導体基板が第１導電形であって、該
半導体基板の表面層に第２導電形の第１領域と第２領域
が離してそれぞれ形成され、前記第１領域と前記第２領
域の間の前記半導体基板の表面層に、前記第１領域およ
び第２領域から離して、第２導電形の第３領域が、前記
第１領域を取り囲むようにリング状に形成され、前記第
１領域と前記第１電極とが接続し、前記第２領域と前記
第２電極とが接続する構成としてもよい。前記半導体基
板の表面層に第１導電形の第１領域が形成され、該第１
領域の表面層に第１導電形の第２領域と第２導電形の第
３領域が離して形成され、前記第２領域と前記第３領域
の間の前記第１領域の表面層に、前記第２領域から離
し、且つ、前記第３領域に接するように第２導電形の第
４領域が形成され、前記第２領域と前記第１電極とが接
続し、前記第３領域と前記第２電極とが接続する構成と
してもよい。前記半導体基板の表面層に第１導電形の第
１領域が形成され、該第１領域の表面層に第２導電形の
第２領域と第３領域が離して形成され、前記第２領域と
前記第３領域の間の前記第１領域の表面層に、前記第２
領域から離し、且つ、前記第３領域に接するように第２
導電形の第４領域が形成され、前記第１電極は前記第２
領域の表面上または前記第２領域と前記第３領域の間の
表面の上部に形成され、前記第２電極は前記第３領域と
接続される構成としてもよい。 The semiconductor substrate is of a first conductivity type, and a first region and a second region of a second conductivity type are separately formed on a surface layer of the semiconductor substrate, and the first region and the second region are formed. A third region of a second conductivity type is formed in a ring shape on the surface layer of the semiconductor substrate between the first region and the second region so as to surround the first region. A configuration may be such that a region is connected to the first electrode, and the second region is connected to the second electrode. The semiconductor substrate
A first region of a first conductivity type is formed in a surface layer of the plate;
The second region of the first conductivity type and the second region of the second conductivity type are formed on the surface layer of the region.
Three regions are formed apart from each other, the second region and the third region
Between the second region and the surface layer of the first region.
And the second conductivity type is in contact with the third region.
Four regions are formed, and the second region and the first electrode are in contact with each other.
Connecting the third region to the second electrode;
May be. The first conductivity type first layer is formed on the surface layer of the semiconductor substrate.
One region is formed, and a second conductive type is formed on the surface layer of the first region.
A second region and a third region are formed apart from each other, and the second region and the third region are separated from each other.
The second layer is provided on the surface layer of the first region between the third regions.
The second region is separated from the region and is in contact with the third region.
A fourth region of conductivity type is formed, and the first electrode is connected to the second region.
On the surface of the region or between the second region and the third region
The second electrode is formed on an upper surface, and the second electrode is in contact with the third region.
It may be configured to be connected.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２８[Correction target item name] 0028
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２８】個々のツェナーダイオードのツェナー電圧
をＶZ 、薄膜層の中のツェナーダイオードを形成するｐ
ｎ接合で、逆阻止状態にあるｐｎ接合の数をｍとする
と、 （１）ＶS ＜ｍ・ＶZ のとき（ツェナーダイオードは非
降伏状態） ｐｎ接合の逆方向の漏れ電流ＩS が渦巻き状の薄膜層に
流れる。高濃度の不純物をドープしたポリシリコンに形
成された個々のツェナーダイオードは、均一な電圧・電
流特性を有するために、渦巻き状の薄膜層は、渦巻きに
沿って均一な電位分布となる。尚、不純物濃度を高くす
ると、濃度制御が容易になり、面内の濃度のばらつきは
小さくなり、抵抗値のばらつきが小さくなる。 （２）ＶS ≧ｍ・ＶZ のとき（ツェナーダイオードは降
伏状態） ｐｎ接合の逆方向に過大な電流が流れ、その状態が長時
間続くと渦巻き状の薄膜層は発熱して破壊に至る。The zener voltage of each zener diode is V z , and p is the zener diode in the thin film layer.
In n junction, if the number of pn junction in the reverse blocking state and m, (1) VS <When m · V Z (zener diode non breakdown condition) reverse leakage I S of the pn junction is spirally Flows into the thin film layer. Since each zener diode formed on polysilicon doped with a high concentration of impurities has uniform voltage / current characteristics, the spiral thin film layer has a uniform potential distribution along the spiral. Note that, when the impurity concentration is increased, the concentration control becomes easier, the variation in the in-plane concentration becomes smaller, and the variation in the resistance value becomes smaller. (2) when the VS ≧ m · V Z (Zener diode breakdown conditions) excessive current flows in the opposite direction of the pn junction, spiral thin film layer when the state continues for a long time leads to destruction by heat.
【手続補正５】[Procedure amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２９[Correction target item name] 0029
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２９】ツェナーダイオードの個数を増やして、半
導体装置の所望の耐圧より、渦巻き状の薄膜層に形成さ
れたツェナーダイオード全数を合わせたツェナー電圧を
高くなるように設定すれば、前記の（１）項の非降伏状
態で使用できる。この非降伏状態でツェナーダイオード
を動作させることで、ツェナーダイオードを破壊させず
に、渦巻き状の薄膜層の電位分布を均一化できる。ま
た、渦巻き状の薄膜層を流れる漏れ電流はツェナーダイ
オードの逆阻止時の電圧・電流特性で決まり、この漏れ
電流は、ツェナーダイオードの数が変わらなければ、渦
巻き状の薄膜層の長さによる影響は少ない。つまり、薄
膜層の占める大きさによる影響は少ない。また、温度の
変化に対する、漏れ電流の変動も、従来の高抵抗の渦巻
き状の抵抗層の変動に比べて、大幅に小さく、安定した
電位分布が形成できる。If the number of Zener diodes is increased and the Zener voltage, which is the total number of Zener diodes formed in the spiral thin film layer, is set to be higher than the desired breakdown voltage of the semiconductor device, (1) It can be used in the non-yield state of the term. By operating the Zener diode in this non-breakdown state, the potential distribution of the spiral thin film layer can be made uniform without destroying the Zener diode. In addition, the leakage current flowing through the spiral thin film layer is determined by the voltage / current characteristics of the Zener diode during reverse blocking, and this leakage current is affected by the length of the spiral thin film layer if the number of Zener diodes does not change. Is less. That is, the influence of the size occupied by the thin film layer is small. Also, the fluctuation of the leakage current with respect to the change of the temperature is significantly smaller than that of the conventional high-resistance spiral-shaped resistance layer, and a stable potential distribution can be formed.
【手続補正６】[Procedure amendment 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５３[Correction target item name] 0053
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００５３】ｐ基板５７のＮwell領域５８を形成し、Ｎ
well領域５８の表面層に選択的にｐ - 領域６０、Ｐ
offset領域６７を形成し、また、Ｐwell領域６１、６４
を形成する。つぎに、絶縁酸化膜６９、７０であるＬＯ
ＣＯＳ（Ｌｏｃａｌ Ｏｘｉｄａｔｉｏｎ ｏｆ Ｓｉ
ｌｉｃｏｎ）を形成する。そのつぎに、図示しないゲー
ト酸化膜を介してポリシリコンでゲート電極７２を形成
し、絶縁酸化膜７０上にポリシリコン膜７５、８４およ
び渦巻き状の薄膜層８３を形成する。この渦巻き状の薄
膜層８３は第１実施例で説明したものと同等である。当
然、前記したように、この渦巻き状の薄膜層８３は多数
のｐｎダイオード（ツェナーダイオードなど）で構成さ
れている。N of p substrate 57wellForming a region 58, N
wellThe surface layer of region 58 is selectively p - Region 60, P
offsetForming a region 67;wellRegions 61 and 64
To form Next, the insulating oxide films 69 and 70
COS (Local Oxidation of Si)
licon). Next, a game (not shown)
The gate electrode 72 is formed with polysilicon through the oxide film
Then, polysilicon films 75, 84 and
And spiral film layer83To form This spiral thin
The film layer 83 is the same as that described in the first embodiment. This
However, as described above, the spiral thin film layer 83 has a large number.
Pn diode (such as Zener diode)
Have been.
【手続補正７】[Procedure amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５７[Correction target item name] 0057
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００５７】[0057]
【発明の効果】この発明によれば、島状領域の周囲を外
周部に向かって周回し、高電位領域と低電位領域を電気
的に接続する渦巻き状の薄膜層を、ツェナーダイオード
の繰り返しにより構成することで、つぎのような効果が
ある。耐圧構造部の耐圧は、ツェナーダイオードの数で
決まり、薄膜層の幅に対する依存性は極めて小さく、そ
のため、同一耐圧においては、電流容量によってチップ
サイズが変わっても渦巻き状の幅を一定にできる。この
ことによって、同一耐圧の素子系列を製造する場合、製
造コストが、従来の抵抗薄膜層（フィールドプレートや
渦巻き状の抵抗薄膜層）に比べて大幅に低減できる。According to the present invention, the spiral thin film layer which goes around the island region toward the outer periphery and electrically connects the high potential region and the low potential region is formed by repeating the zener diode. The configuration has the following effects. Breakdown voltage of the breakdown voltage structure is determined by the number of zener diodes, dependence on the width of the thin film layer is extremely small, therefore, in the same breakdown voltage, the chip by the current capacity
The spiral width can be kept constant even if the size changes . As a result, when manufacturing an element series having the same withstand voltage, the manufacturing cost can be greatly reduced as compared with a conventional resistance thin film layer (a field plate or a spiral resistance thin film layer).
【手続補正８】[Procedure amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５８[Correction target item name] 0058
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００５８】また、ツェナーダイオードの逆耐圧特性を
利用しているので、温度依存性が小さく、そのため、耐
圧を安定して得ることができる。また渦巻き状の薄膜層
を形成するポリシリコンの不純物濃度を１×１０18ｃｍ
-3以上と高濃度とすることで、個々のツェナーダイオー
ドの電圧・電流特性を揃えることができる。そうするこ
とで、高電位領域から低電位領域への電位勾配を均一化
し、高い耐圧を得ることができる。Further, since the reverse withstand voltage characteristic of the Zener diode is used, the temperature dependency is small , so that the withstand voltage can be stably obtained. The impurity concentration of the polysilicon forming the spiral thin film layer is 1 × 10 18 cm.
By setting the concentration as high as -3 or more, the voltage and current characteristics of the individual zener diodes can be made uniform. By doing so, the potential gradient from the high potential region to the low potential region can be made uniform, and a high breakdown voltage can be obtained.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 齋藤 順 神奈川県川崎市川崎区田辺新田１番１号 富士電機株式会社内 Ｆターム(参考） 5F048 AA05 AA07 AC06 AC10 BA01 BB05 BC00 BC03 BC07 BC12 BD00 BE03 BE05 BF16 BG12 BH05 BH07 CC06 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Jun Saito 1-1-1, Tanabe-Shinda, Kawasaki-ku, Kawasaki-shi, Kanagawa F-term (reference) 5F048 AA05 AA07 AC06 AC10 BA01 BB05 BC00 BC03 BC07 BC12 BD00 BE03 BE05 BF16 BG12 BH05 BH07 CC06
Claims (13)
いに離して形成された第１電極と第２電極とを有する半
導体装置において、両端がそれぞれ第１電極、第２電極
に接続され、且つ、第１電極を取り囲む渦巻き状の薄膜
層が、前記絶縁膜上に形成され、該渦巻き状の薄膜層の
長手方向に沿って、直列に複数個のｐｎダイオードが形
成されることを特徴とする半導体装置。1. A semiconductor device having a first electrode and a second electrode formed apart from each other on an insulating film formed on a semiconductor substrate, both ends of which are connected to the first electrode and the second electrode, respectively. A spiral thin film layer surrounding the first electrode is formed on the insulating film, and a plurality of pn diodes are formed in series along the longitudinal direction of the spiral thin film layer. Semiconductor device.
半導体基板が、主電流が流れる活性領域となっていて、
その半導体基板上に前記絶縁膜を介して前記渦巻き状の
薄膜層が形成されていることを特徴とする請求項１に記
載の半導体装置。2. The semiconductor substrate between the first electrode and the second electrode is an active region through which a main current flows,
2. The semiconductor device according to claim 1, wherein the spiral thin film layer is formed on the semiconductor substrate via the insulating film.
該ポリシリコンに第１導電形領域と第２導電形領域が交
互に複数個形成され、前記第１導電形領域と前記第２導
電形領域とでｐｎダイオードが形成されることを特徴と
する請求項１に記載の半導体装置。3. The thin film layer is formed of polysilicon,
A plurality of first conductivity type regions and a plurality of second conductivity type regions are alternately formed in said polysilicon, and a pn diode is formed by said first conductivity type region and said second conductivity type region. Item 2. The semiconductor device according to item 1.
形成され、該第１導電形ポリシリコンに選択的に第２導
電形領域が、離して複数個形成され、前記第１導電形ポ
リシリコンで形成された第１導電形領域と前記第２導電
形領域が交互に複数個形成され、前記第１導電形領域と
前記第２導電形領域とでｐｎダイオードが形成されるこ
とを特徴とする請求項１または２に記載の半導体装置。4. The first conductivity type polysilicon, wherein the thin film layer is formed of a first conductivity type polysilicon, and a plurality of second conductivity type regions are selectively formed in the first conductivity type polysilicon at a distance from each other. A plurality of first conductivity type regions and the second conductivity type regions formed of polysilicon are alternately formed, and a pn diode is formed by the first conductivity type regions and the second conductivity type regions. 3. The semiconductor device according to claim 1, wherein:
直列に前記薄膜層に形成されることを特徴とする請求項
１または２に記載の半導体装置。5. The semiconductor device according to claim 1, wherein said pn diode is formed in said thin film layer in a forward series or an inverse series.
であることを特徴とする請求項１ないし５のいずれかに
記載の半導体装置。6. The semiconductor device according to claim 1, wherein said pn diode is a Zener diode.
領域の不純物濃度が１×１０18ｃｍ-3以上であることを
特徴とする請求項３に記載の半導体装置。7. The semiconductor device according to claim 3, wherein said first conductivity type region and said second conductivity type region have an impurity concentration of 1 × 10 18 cm −3 or more.
物もしくはｎ形不純物を１×１０18ｃｍ-3以上ドーピン
グして形成されることを特徴とする請求項４に記載の半
導体装置。8. The semiconductor device according to claim 4, wherein said first conductivity type polysilicon is formed by doping a p-type impurity or an n-type impurity by 1 × 10 18 cm −3 or more.
ｍ以下とすることを特徴とする請求項１または２に記載
の半導体装置。9. The insulating film having a thickness of 0.01 or more and 10 μm or more.
3. The semiconductor device according to claim 1, wherein m is equal to or less than m. 4.
該半導体基板の表面層に第１導電形の第１領域と第２導
電形の第２領域が離して形成され、前記第１領域と前記
第２領域の間の前記半導体基板の表面層に、前記第１領
域から離し、且つ、前記第２領域に接するように第２導
電形の第３領域が形成され、前記第１領域と前記第１電
極とが接続し、前記第２領域と前記第２電極とが接続す
ることを特徴とする請求項１に記載の半導体装置。10. The semiconductor substrate of the first conductivity type,
A first region of a first conductivity type and a second region of a second conductivity type are formed separately on a surface layer of the semiconductor substrate, and a surface layer of the semiconductor substrate between the first region and the second region includes: A third region of the second conductivity type is formed so as to be separated from the first region and in contact with the second region, the first region is connected to the first electrode, and the second region is connected to the second region. The semiconductor device according to claim 1, wherein the two electrodes are connected.
該半導体基板の表面層に第２導電形の第１領域と第２領
域が離してそれぞれ形成され、前記第１領域と前記第２
領域の間の前記半導体基板の表面層に、前記第１領域お
よび第２領域から離して、第２導電形の第３領域が、前
記第１領域を取り囲むようにリング状に形成され、前記
第１領域と前記第１電極とが接続し、前記第２領域と前
記第２電極とが接続することを特徴とする請求項１に記
載の半導体装置。11. The semiconductor substrate of the first conductivity type,
A first region and a second region of a second conductivity type are separately formed on a surface layer of the semiconductor substrate, and the first region and the second region are formed separately.
A third region of a second conductivity type is formed in a ring shape on the surface layer of the semiconductor substrate between regions, away from the first region and the second region, so as to surround the first region. 2. The semiconductor device according to claim 1, wherein one region is connected to the first electrode, and the second region is connected to the second electrode.
徴とする請求項１または２に記載の半導体装置。12. The semiconductor device according to claim 1, wherein a plurality of said thin film layers are formed.
ダイオードの降伏電圧をＶZ 、前記渦巻き状の薄膜層の
中のｐｎダイオードを形成するｐｎ接合で、逆阻止状態
にあるｐｎ接合の数をｍとすると、 ＶB ＜ＶZ ×ｍ を満足することを特徴とする請求項１または２に記載の
半導体装置。13. The semiconductor device according to claim 1, wherein the breakdown voltage is V B ,
Assuming that the breakdown voltage of the diode is V Z , and the number of pn junctions forming a pn diode in the spiral thin film layer in the reverse blocking state is m, V B <V Z × m is satisfied. The semiconductor device according to claim 1, wherein:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30851699A JP4960540B2 (en) | 1998-11-05 | 1999-10-29 | Semiconductor device |
| US09/494,995 US6603185B1 (en) | 1999-02-01 | 2000-01-31 | Voltage withstanding structure for a semiconductor device |
| EP00101883A EP1032046A1 (en) | 1999-02-01 | 2000-01-31 | Semiconductor device having a thin film field-shaping structure |
| US10/460,135 US6828645B2 (en) | 1999-02-01 | 2003-06-12 | Voltage withstanding structure for a semiconductor device |
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31383998 | 1998-11-05 | ||
| JP1998313839 | 1998-11-05 | ||
| JP11-23852 | 1999-02-01 | ||
| JP1999023852 | 1999-02-01 | ||
| JP2385299 | 1999-02-01 | ||
| JP10-313839 | 1999-02-01 | ||
| JP30851699A JP4960540B2 (en) | 1998-11-05 | 1999-10-29 | Semiconductor device |
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| JP2010141905A Division JP5267510B2 (en) | 1998-11-05 | 2010-06-22 | Semiconductor device |
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Family
ID=27284409
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| JP30851699A Expired - Fee Related JP4960540B2 (en) | 1998-11-05 | 1999-10-29 | Semiconductor device |
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