JP2000295533A - Solid-state imaging device, driving method thereof, and signal processing method of solid-state imaging device - Google Patents

Abstract

(57) [Problem] In a conventional method of correcting based on a black level signal of a pixel, offset variation for each line amplifier can be corrected, but gain variation cannot be corrected. A line amplifier (19) is provided for each vertical signal line (15).
In a CMOS type imaging device having
Of the pixel 11 by changing the operating point of the line amplifier 19 in two steps by switching the DC bias of the line amplifier 19 into two levels (high level and low level) by the DC bias generation circuit 23 within the vertical blanking period V-BLK. Without operating, a black level signal and a white level signal are generated, and the black level signal and the white level signal are processed by a signal processing system in a subsequent stage.
It is used as a correction signal for correcting the characteristic variation of the line amplifier 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensing device, a method of driving the same, and a signal processing method of the solid-state image sensing device. More particularly, the present invention relates to a solid-state image sensing device having a line amplifier for each vertical signal line, and a method of driving the same. The present invention relates to a signal processing method for removing a vertical streak-like noise component of a solid-state imaging device.

[0002]

2. Description of the Related Art Conventionally, as a solid-state imaging device of this type, as shown in FIG. 9, a vertical scanning circuit 102 applies a vertical selection line 103 to a pixel portion in which unit pixels 101 are two-dimensionally arranged in a matrix. , The pixel signals of the unit pixels 101 are stored in the line amplifier 105 connected to each of the vertical signal lines 104 on a row-by-row basis, and the horizontal scanning circuit 16 performs column selection to perform horizontal selection. There is known a CMOS type image sensor having a configuration in which output is performed via a signal line 107 and a sense amplifier 108 (for example,
U.S. Pat. No. 5,345,266).

As described above, in a CMOS type image sensor having a line amplifier 108 for each vertical signal line 104, variations in the characteristics of the circuit elements constituting each line amplifier 108 are inevitable. This becomes a factor of characteristic variation for each line amplifier 108. The characteristic variation of each line amplifier 108 includes variation in Vth (threshold voltage) of a transistor (hereinafter, Vth).
Offset variation due to variation)
And there is gain variation.

[0004] These characteristic variations appear as vertical streak-like noise, which adversely affects image quality. Conventionally, in order to remove this vertical streak-shaped noise component, a black level signal is output from each pixel in a state where incident light incident on the imaging surface of the imaging element is blocked (shutter is closed).
This is stored in a frame memory in a signal processing system at the subsequent stage, and correction is performed by calculating for each pixel with an image signal output from an image sensor.

[0005]

However, as described above, in the conventional method of correcting based on the black level signal of the pixel, offset variations due to Vth variations and the like can be corrected, but the line can be corrected only from the black level signal. Since information on the gain of the amplifier 108 cannot be obtained, it is not possible to correct the variation in gain of each vertical signal line 104 for each line amplifier 108, and therefore it is not possible to completely remove vertical streak-like noise components. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of correcting not only offset variation for each line amplifier but also gain variation, and a driving method thereof. A method and a signal processing method for a solid-state imaging device are provided.

[0007]

In order to achieve the above object, according to the present invention, a pixel section in which unit pixels are two-dimensionally arranged in a matrix and a pixel section in a row direction of the pixel section are arranged. In a solid-state imaging device including a plurality of line amplifiers connected to each of the connected signal lines, an operating point of each of the plurality of line amplifiers is changed.

By changing the operating point of each of the plurality of line amplifiers, for example, two correction signals of a black level signal and a white level signal can be generated. These two correction signals are derived as output signals of the solid-state imaging device. Then, in the signal processing system, the two correction signals are calculated with the imaging signal of the solid-state imaging device. As a result, noise components included in the imaging signal of the solid-state imaging device, particularly noise components caused by variations in the gain of the line amplifier are removed.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a CMOS image sensor according to an embodiment of the present invention.

In FIG. 1, a region surrounded by a broken line represents a unit pixel 11. The unit pixel 11 includes a photodiode (PD) 12 which is a photoelectric conversion element and a selection MOS which is a vertical selection switch for selecting pixels in row units.
A transistor 13 and a readout MO which is a readout switch for reading out signal charges from the photodiode 12
And an S transistor 14. These unit pixels 1
1 are two-dimensionally arranged in a matrix to constitute a pixel portion.

In this unit pixel 11, a photodiode 12 photoelectrically converts incident light and accumulates signal charges obtained by the photoelectric conversion. That is, the photodiode 12 has both functions of photoelectric conversion and charge accumulation. A cathode electrode of the photodiode 12 and a vertical signal line 15 arranged for each pixel column in a row direction (vertical direction).
Between them, the selection MOS transistor 13 and the read MOS transistor 14 are connected in series.
The gate electrode of the selection MOS transistor 13 is connected to the vertical selection line 16 and the read MOS transistor 14
Are connected to the read pulse line 17, respectively.

Between an end of the vertical signal line 15 and the horizontal signal line 18, a line amplifier 19 for converting signal charges read out to the vertical signal line 15 into a signal voltage, and an output voltage of the line amplifier 19 Are selectively connected in series to the horizontal signal line 18.

As the line amplifier 19, for example, FIG.
As shown in FIG. 2A, a configuration having two stages of a differential amplifier 191 and a common source amplifier 192 and a configuration having a source follower circuit as shown in FIG. 2B are used. The line amplifier 19 includes a capacitor 2
1 and a reset MOS for resetting the vertical signal line 15
Transistors 22 are connected in parallel. The line amplifier 19 may have a circuit configuration for converting a signal charge into a signal current.

The DC bias of the line amplifier 19 (hereinafter referred to as
DC bias) is generated by the DC bias generation circuit 23. The DC bias generation circuit 23 generates, for example, a binary (high level / low level) DC bias and selectively supplies the high level / low level DC bias to the line amplifier 19, thereby It functions as operating point adjusting means for changing the operating point of the line amplifier 19 in two stages.

FIG. 3 shows an example of the circuit configuration of the DC bias generation circuit 23. DC bias generation circuit 2 according to this example
Reference numeral 3 denotes a Pch MOS transistor Q1 having a source electrode connected to a power supply and a gate electrode grounded;
The drain electrode of the OS transistor Q1 and the ground (GN
D) NchMO of diode connection configuration connected during
S transistor Q2 and PchMOS transistor Q1
PchMOS transistor Q connected in parallel to
3 is a MOS resistance type direct current source circuit.

In the DC bias generation circuit 23 having such a configuration, a bias switching pulse for switching the DC bias is applied to the gate electrode of the PchMOS transistor Q3, and the PchMOS transistors Q1, Q3 and Nc
The potential of each drain common connection point A of the hMOS transistor Q2 is extracted as a DC bias. The bias switching pulse is generated in the vertical blanking period V-BLK of the video signal format, as shown in the timing chart of FIG.

Here, when the bias switching pulse is at a high level, the MOS transistor Q3 is in an off state, so that a low level is applied to the drain common connection point A by the voltage division by the channel resistances of the MOS transistors Q1 and Q2. When the potential is obtained as a DC bias and the bias switching pulse is at a low level, MOS transistor Q3 is turned on, and MOS transistors Q1, Q3
Are connected in parallel, a high-level potential of substantially the power supply voltage is obtained as a DC bias.

Referring again to FIG. 1, a vertical scanning circuit 24 for row selection and a horizontal scanning circuit 25 for column selection are provided. These scanning circuits 24 and 25 are constituted by, for example, shift registers. The vertical scanning pulse φVm output from the vertical scanning circuit 24 is applied to the vertical selection line 16, the read pulse φCn output from the horizontal scanning circuit 25 is applied to the read pulse line 17, and the horizontal scanning pulse φHn is used for horizontal selection. MOS transistor 2
The reset pulse φRn is applied to the gate electrode of the reset MOS transistor 22.

At the output end of the horizontal signal line 18, for example, a correlated double sampling circuit (hereinafter, referred to as a CDS (Correlated Double Sampling) circuit) 27 is provided as a difference circuit via a horizontal output amplifier 26. This CD
The S circuit 27 is connected to the horizontal signal line 18 from each of the unit pixels 11.
This is provided to obtain a difference between a reset level and a signal level which are sequentially supplied via the.

In the CMOS type imaging device having the above structure,
The pixel portion in which the unit pixels 11 are arranged in a matrix is shown in FIG.
As shown in the figure, with respect to the entire area (pixel area), a specific area is an opening area which takes in light from the outside and actually contributes to imaging, and the other area is covered with a light shielding film. It is a light shielding area (optical black; OPB) that does not capture light. Since no light enters the light-shielded area from the outside, the pixels in the area output a black level signal. This black level signal is used as a reference level of an image signal output from the image sensor.

As shown in the timing chart of FIG. 4, the bias switching pulse applied to the DC bias generation circuit 23 has a low level only during a certain period in the vertical blanking period V-BLK, and otherwise has a high level. Becomes At the time of reading out the imaging signal, the bias switching pulse is at a high level. At this time, the DC shown in FIG.
In the bias generation circuit 23, the PchMOS transistor Q3 is turned off.

Here, the PchMOS transistor Q1 is always on because the source electrode is connected to the power supply and the gate electrode is connected to the ground. Thus, the potential obtained at the common drain connection point A, that is, the output DC bias potential is determined according to the channel resistances of the PchMOS transistor Q1 and the NchMOS transistor Q2.

This DC bias value is, for example, shown in FIG.
When input as the DC bias 1 of the line amplifier having the circuit configuration shown in FIG. 6, the input / output characteristics of the line amplifier become as shown in FIG. That is, a signal of (black level to saturation level) is output according to the signal charge generated in each pixel 11.

On the other hand, during the vertical blanking period V-BLK that does not appear on the actual screen, the line amplifier 19 and the horizontal scanning circuit 25 output a pseudo black level signal and a white level signal near the saturation level. I do.

First, when the black level signal is output, the vertical blanking period V
At −BLK, a high-level bias switching pulse is applied to the DC bias generation circuit 23. Thereby, Pch
Since the MOS transistor Q3 is turned off and a pixel signal in the light-shielded area is output in the vertical blanking period V-BLK, a black level signal is output. At this time, the input / output characteristics of the line amplifier 19 are as shown in FIG.
The black level signal is output when the reset level of the line amplifier 19 is input.

In outputting the white level signal, a certain period in the vertical blanking period V-BLK
A low level bias switching pulse is applied to the DC bias generation circuit 23. Thereby, PchMOS transistor Q3 is turned on. Then, since the channel resistances of the PchMOS transistor Q1 and the PchMOS transistor Q3 become parallel, the potential of the drain common connection point A, that is, the DC bias shifts toward the power supply voltage. At this time, the input / output characteristics of the line amplifier 19 are as shown in FIG. 7, and a white level signal is output when the reset level of the line amplifier 19 is input.

As described above, in the CMOS image sensor having the line amplifier 19 for each vertical signal line 15, the DC bias of the line amplifier 19 is controlled by the DC bias generation circuit 23 within the vertical blanking period V-BLK.
By changing the operating point of the line amplifier 19 in two stages by switching between values (high level and low level), the pixel 1
1 can be generated without generating the black signal level and the white signal level. The black signal level and white signal level generated in this manner are used as correction signals for correcting characteristic variations of the line amplifier 19 in a signal processing system at a later stage, as described later.

In this embodiment, the line amplifier 19
Is switched by two values, and the operating point of the line amplifier 19 is changed in two steps to generate a black level signal and a white level signal. However, the switching of the operating point of the line amplifier 19 is limited to two steps. Instead, the operating point of the line amplifier 19 is continuously changed by continuously changing the DC bias of the line amplifier 19 to continuously generate a level signal in addition to the black level signal and the white level signal. It is also possible.

According to this, since more information on the gain of the line amplifier 19 can be obtained, the variation in the gain of the line amplifier 19 can be more reliably corrected. , The vertical streak-like noise component caused by the variation in the gain of the line amplifier 19 included in the line amplifier 19 can be reliably removed.

Next, the configuration and operation of a signal processing system having a function of correcting the characteristic variation of the line amplifier 19 will be described. FIG. 8 is a block diagram illustrating an example of a configuration of a signal processing system of a CMOS image sensor.

In FIG. 8, a CMOS image sensor having the above-described configuration is used as the image sensor 31. As a result, the image sensor 31 outputs a black level signal and a white level signal as correction signals in the vertical blanking period V-BLK in addition to the normal imaging signal. Image sensor 3
The output signal of 1 is digitized by an A / D converter 32 and then supplied to an arithmetic circuit 33 and a line memory 34. The line memory 34 has a vertical blanking period V-
A signal of a pixel in the light-shielded area input in the BLK,
That is, a black level signal is stored for one line.

The black level signal stored in the line memory 34 is supplied to an arithmetic circuit 33. In the arithmetic circuit 33, the CMOS type image sensor 31 converts the A / D converter 32
Is calculated with the imaging signal supplied via the.
Thus, the offset variation (unevenness) of the line amplifier 19 is corrected. That is, the arithmetic circuit 33 removes, from among the characteristic variations of the line amplifier 19, a vertical streak-like noise component due to the offset variation from the image pickup signal.

Next, the image pickup signal from which the vertical streak-like noise component caused by the offset variation has been removed is calculated by the arithmetic circuit 35.
, And becomes one input of the difference circuit 36, and is further delayed by a predetermined time by the delay circuit 37 to become the other input of the difference circuit 36. The delay circuit 37 shown in FIG.
In the timing chart of FIG. 7, the black level signal and the white level signal input during the vertical blanking period V-BLK are synchronized.

The differential circuit 36 obtains the level difference between the black level signal and the white level signal synchronized by the delay circuit 37. This level difference is stored in the line memory 38 for one line. The level difference stored in the line memory 38 is supplied to an arithmetic circuit 35, and the arithmetic circuit 35 performs an arithmetic operation with the imaging signal supplied from the arithmetic circuit 33. Thus, the gain variation of the line amplifier 19 is corrected. That is, the arithmetic circuit 35 removes a vertical streak-like noise component due to the variation in the gain from the variation in the characteristics of the line amplifier 19 from the imaging signal.

As described above, the line amplifier is provided for each of the vertical signal lines, and the DC bias of the line amplifier is changed to change the operating point of the line amplifier so that at least two correction signals of the black level signal and the white level signal can be obtained. In the signal processing system of the image sensor 31 having the configuration for generating, the characteristic variation of the line amplifier is corrected based on the two correction signals, so that not only the offset variation but also the gain variation can be corrected. This makes it possible to reliably remove the vertical streak-like noise component contained in the image signal of the image sensor 31, thereby contributing to an improvement in image quality.

[0036]

As described above, according to the present invention,
In a solid-state imaging device having a line amplifier for each vertical signal line, by changing each operating point of these line amplifiers, for example, two correction signals of a black level signal and a white level signal can be generated. By performing correction processing using two correction signals, it is possible to correct not only offset variations for each line amplifier but also gain variations, so that vertical streak-like noise components included in the imaging signal of the solid-state imaging device are reliably removed. Will be able to do that.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a CMOS image sensor according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing circuit examples (A) and (B) of a line amplifier.

FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of a DC bias generation circuit.

FIG. 4 is a timing chart showing a timing relationship between an output signal of an image sensor and a bias switching pulse.

FIG. 5 is a diagram showing a relationship between an opening area and a light shielding area in a pixel area.

FIG. 6 is an input / output characteristic diagram of a line amplifier when an imaging signal is output.

FIG. 7 is an input / output characteristic diagram of a line amplifier when a black / white level signal is output.

FIG. 8 is a block diagram illustrating an example of a circuit configuration of a signal processing system.

FIG. 9 is a schematic configuration diagram illustrating a basic configuration of a CMOS image sensor.

[Explanation of symbols]

11 unit pixel, 12 photodiode, 15 vertical signal line, 18 horizontal signal line, 19 line amplifier, 23
... DC bias generation circuit, 27 ... Correlated double sampling (CDS) circuit, 31 ... Imaging element, 33,35 ... Operation circuit, 34,38 ... Line memory, 36 ... Difference circuit

Claims (8)

[Claims] A pixel unit in which unit pixels are two-dimensionally arranged in a matrix; a plurality of line amplifiers connected to each of signal lines arranged for each pixel column in a row direction of the pixel unit; A solid-state imaging device comprising: operating point adjusting means for changing an operating point of each of the plurality of line amplifiers. 2. The solid-state imaging device according to claim 1, wherein said operating point adjusting means changes a DC bias of each of said plurality of line amplifiers. 3. The operating point adjusting means sets a DC bias of each of the plurality of line amplifiers to at least two of a bias corresponding to a black level and a bias corresponding to a white level.
3. The solid-state imaging device according to claim 2, wherein switching is performed between two DC biases. 4. The solid-state imaging device according to claim 1, wherein said operating point adjusting means changes an operating point within a vertical blanking period. 5. A pixel section in which unit pixels are two-dimensionally arranged in a matrix, and a plurality of line amplifiers connected to each of signal lines arranged for each pixel column in a row direction of the pixel section. A driving method of the solid-state imaging device, wherein an operating point of each of the plurality of line amplifiers is changed. 6. The method according to claim 5, wherein an operating point is changed by changing a DC bias of each of the plurality of line amplifiers. 7. A pixel unit in which unit pixels are two-dimensionally arranged in a matrix, and a plurality of line amplifiers connected to each of signal lines arranged for each pixel column in a row direction of the pixel unit. A signal processing method for a solid-state imaging device, wherein a correction signal is generated by changing an operating point of each of the plurality of line amplifiers, and the correction signal is included in an imaging signal of the solid-state imaging device based on the correction signal. A signal processing method for a solid-state imaging device, wherein a noise component is removed. 8. A method for generating at least two correction signals of a black level signal and a white level signal by changing a DC bias of each of the plurality of line amplifiers, and imaging the solid-state imaging device based on the two correction signals. 8. The signal processing method for a solid-state imaging device according to claim 7, wherein a noise component included in the signal is removed.