JP2000305801A - Data transfer performance calculation method - Google Patents

Abstract

(57) [Problem] To easily and accurately calculate the data transfer performance of a system for transferring data between a plurality of functional modules via a system bus. SOLUTION: A random pattern generator 12 randomly extracts parameters such as a data transfer destination, a transfer direction, and the number of bursts to generate test patterns 11a and 11b, and a bus operation model 10a based on the patterns 11a and 11b. , 10b transfer data via the system bus 1. The bus monitor 13 collects the data transfer information and outputs the data transfer log 14 [transfer start time, transfer number (W
ord number), transfer cycle (clk), etc.], and the bus transfer performance calculation tool 15 calculates the data transfer amount from the log 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for calculating data transfer performance in a system including a system bus and functional modules connected to the system bus.

[0002]

2. Description of the Related Art FIG. 13 shows a conventional input / output performance measuring circuit disclosed in Japanese Patent Application Laid-Open No. 5-40706, in which a system bus 1 and a function module (H / W) connected to the system bus 1 have an original function. In addition to the bus control circuit 2 and the transfer control circuit 3 for controlling the operation of the system bus 1, which is a function, an adder 4, a transfer byte number register 5, counters 6a and 6b, and a transfer for measuring data transfer performance of the bus. An H / W such as a byte number storage memory 7 and a diagnostic control circuit 8 is provided.

In the conventional input / output performance measuring circuit having the above-described configuration, the unit time is measured by the counters 6a and 6b, and the adder 4 performs data transmission between the system bus 1 and the bus control circuit 2 within the unit time. Multiply the number of transfer bytes for the transfer.
As described above, the performance of data transfer performed by the input / output device is measured.

[0004]

Since the conventional system bus transfer performance calculation method is configured as described above, the H / W is used to measure the data transfer performance of the system bus 1.
It cannot be measured without the entity itself. In addition, H for measuring in a functional module connected to the system bus 1
/ W must be embedded. Furthermore, in order to accurately measure and calculate the data transfer performance, the data transfer operation on the system bus 1 must be close to that of the actual system. In addition, an application S / W that operates on the system must be prepared, and can be executed only in the final stage of the development of the system. Therefore, there is a problem that reworking when the system performance is insufficient becomes large. was there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the data transfer performance of the system bus is measured in a logic simulation environment, so that an H / W entity is prototyped and developed. It is an object of the present invention to provide a data transfer performance calculation method for easily and as accurately as possible calculating the performance of a system bus at an early stage of development before the development. This calculation method is also intended to be used for calculating the performance of H / W other than the simulation environment.

[0006]

(1) A system bus transfer performance calculation method according to the present invention calculates a data transfer performance of a system for transferring data between a plurality of functional modules connected via a system bus. In the data transfer performance calculation method, the function module randomly extracts parameters such as a data transfer destination, a transfer direction, and the number of bursts to generate a test pattern, and generates a test pattern based on the generated test pattern. A module having a bus operation model for executing data transfer, a bus monitor for recording a data transfer state on the system bus, and a data transfer capacity such as a data transfer amount calculated based on the record of the bus monitor. It is provided with a transfer capability calculation means.

(2) In a data transfer performance calculation method for calculating a data transfer performance of a system for transferring data between a plurality of function modules connected via a system bus, the function module includes a data transfer destination and a data transfer destination. A parameter file in which extraction probabilities for each parameter such as the transfer direction and the number of bursts are set, and a pattern generating means for randomly extracting each parameter of the parameter file according to the extraction probability to generate a test pattern; A module having a bus operation model for executing data transfer based on a test pattern, a bus monitor for recording a data transfer state on the system bus, and data such as a data transfer amount based on the record of the bus monitor. Transfer capacity calculating means for calculating the transfer capacity.

(3) In a data transfer performance calculation method for calculating a data transfer performance of a system for transferring data between a plurality of function modules connected via a system bus, the function module includes: A plurality of sets of test patterns in which parameters such as the transfer direction and the number of bursts are combined are set in advance, and a pattern generating means for randomly extracting these test patterns, and a bus for executing data transfer based on the extracted test patterns A module having an operation model, a bus monitor for recording a data transfer state on the system bus, and a transfer capability calculating means for calculating a data transfer capability such as a data transfer amount based on the recording of the bus monitor. It is a thing.

(4) Further, in any one of the above (1) to (3), an address for each functional module is set, and a transfer address is assigned to each functional module so that a data request source can be determined. Or means for transferring the address of the data requester together with the data, and transferring the data as data corresponding to the address at the time of data transfer, so that the bus monitor records the data transfer state corresponding to the address, The transfer capacity calculating means calculates the data transfer capacity such as the data transfer amount for each functional module based on the record of the bus monitor.

(5) In (4), the transfer capability calculating means feeds back the calculated data transfer capability of each functional module to the corresponding functional module, and the pattern generating means of the functional module feeds back. The data transfer capability is adjusted so that the data transfer capability approaches the data transfer capability set in the parameter file.

(6) In any one of the above items (1) to (5), the bus monitor detects a request signal requesting data transfer, and at the time of generation of the request signal and execution of the data transfer. The transfer time calculating means calculates the wait time or calculates the throughput from the two time points.

(7) In any one of the above (1) to (6), the bus monitor detects a retry signal (re-data transfer request) generated when the functional module cannot transfer data. In addition, the retry signal is recorded as zero data transfer amount, and when data transfer based on the retry signal is executed, the data transfer amount at the time of execution is recorded.

(8) Any one of (1) to (7)
In the paragraph, in the case where the system bus and other buses are hierarchically connected via a bus bridge that controls data transfer between these buses, and an arbitrary number of functional modules are connected to each of the buses, The bus monitor records the data transfer state of each bus, and the transfer capability calculating means calculates the data transfer capability of each bus.

(9) In the above (4) or (5), the system bus and other buses are hierarchically connected via a bus bridge which controls data transfer between these buses.
In a configuration in which an arbitrary number of function modules are connected to each of the buses, when setting addresses for the respective function modules, addresses are set so as not to be duplicated between layers, and the function modules are At the time of data transfer, the data corresponding to the address is transferred, the bus monitor records the data transfer state corresponding to the address for each bus, and the transfer capability calculating means records the same address for each bus of the bus monitor. When there is a data transfer record described above, it is recognized that the data transfer is between layers, and the data transfer time between layers can be calculated.

(10) Further, in any one of (1) to (9), one pattern generating means is used in place of the pattern generating means of a plurality of arbitrary functional modules. .

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a simulation configuration diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a system bus, and 10a and 10b denote bus operation models. A plurality of bus operation models are connected to the system bus 1 in a simulation environment defined in the present embodiment. Do.

In this embodiment, the bus operation models 10a and 10b will be described as models having the same function.
The model does not need to be the same as long as the operation can be simulated by some instructions. The protocol of the system bus 1 will be described on the premise of a standard bus having an address / data multiplex type and a burst transfer function, but the protocol and the like are not particularly defined.

Reference numerals 11a and 11b denote bus operation models 10
a and 10b are test patterns for determining the bus operation, in which a data transfer destination address during a bus master operation,
Information such as the data transfer direction, the number of bursts (the number of data that can be transmitted in one bus transfer), the transfer interval (idle period), and the response time at the time of a bus slave are included. Numeral 12 denotes a random pattern generator, which randomly determines each piece of the information for determining the bus operation by using a random function and generates test patterns 11a and 11b.

Reference numeral 13 denotes a bus monitor connected to the system bus 1, which receives an address / data signal, a control signal, and the like of the system bus 1, recognizes an operation state of the bus, and includes bus operation information. Data transfer log 1
4 is generated. Reference numeral 15 denotes a bus transfer performance calculation tool,
This is a tool for determining the performance of the system bus 1 from the information in the data transfer log 14.

Next, the operation will be described with reference to FIG. First, an arbitrary system bus 1 according to the determined specification and a functional module connected thereto are configured.
In order to simulate a specific system, a simulation environment for connecting the bus operation models 10a and 10b to the system bus 1 is constructed. In addition to the bus operation models 10a and 10b, a bus monitor 13 is connected to the system bus 1 under the simulation environment.

In this embodiment, the bus operation model 10
The following procedure is performed to operate a and 10b on the simulation. (1) First, the random pattern generator 12 generates information necessary for the operation of each of the bus operation models 10a and 10b, such as a data transfer destination address, a data transfer direction, the number of bursts, and a transfer interval during a bus master operation. ,
The response time at the time of the bus slave is determined.

(2) To illustrate this determination, the random pattern generator 12 has the following parameters, and each of the parameters (a), (b), (c),.
Select randomly for each. (A) Data transfer direction Read as random functions 0 to 9 Write 0 to 4 Write 5 to 9 (b) Number of bursts (at 1 to 4) Random functions as 0 to 99 10 to 24 2 25 to 49 3 50 to 74 4 75 to 99 (c) Data transfer destination As random function 0 to 99 Model A 0 to 33 Model B 34 to 66 Model C 67 to 99 (d) Number of response weights (0 to 3) As random function 0 to 99 0 to 24 1 25 to 49 2 50 to 74 3 75 to 99

(3) The content of the determined parameter differs depending on external factors and the content and operation of the S / W operating on the system. Further, the number of race conditions between the function modules on the system bus 1 cannot be easily grasped. That is, it can be said that it is impossible to accurately set the parameters in the early stage of development of a large system such as a computer system. In the present invention, in order to solve the problem,
A random function is used to determine the parameters. In other words, the main purpose is to calculate the performance of the system bus 1 easily and as accurately as possible by performing a simulation operation for a relatively long time using the parameters determined at random.

(4) Next, the random pattern generator 12 generates test patterns 11a and 11b for applying to each of the bus operation models 10a and 10b according to a predetermined format. (5) The bus operation models 10a and 10b perform a bus transfer operation (master operation and slave operation) according to the instructions of the test patterns 11a and 11b on a simulation. At this time, if a conflict occurs in data transfer between the bus operation models 10a and 10b, arbitration and operation are performed according to the specifications of the system bus 1. by this,
A random data transfer operation (including a race condition) by the bus operation models 10a and 10b can be realized on a simulation.

(6) On the other hand, the bus monitor 13 connected to the system bus 1 in the simulation recognizes the data state on the bus by taking in the address / data signal and control signal of the system bus 1 and recognizes the information. Is output in the form shown in FIG. 2, for example.
In this example, as information of the data transfer log 14, the transfer start time 16 (absolute time in simulation), the number of transfer data 17 (the number of data bytes transferred on the bus), the number of cycles 18 required for transfer (data transfer (The number of clocks from the start to the completion) is logged for each data transfer.

The simulator performs the simulation operation for a predetermined operation simulation time (execution clock). It is preferable to make the operation simulation time as long as possible in order to eliminate the bias of the random function and to improve the coverage of the race condition. (7) The bus transfer performance calculation tool 15 determines the information of the data transfer log 14 for the operation simulation time.
Accumulate the number of transfer data. The value obtained by dividing the total value by the simulation time can obtain the number of transfer data per unit time, that is, the data transfer performance on the system bus 1.

In the above embodiment, the number of data to be transferred per unit time is determined after a series of simulations is completed.
By utilizing the number 6, it is possible to calculate the number of transfer data per unit time at the same time as the simulation is executed. Thereby, the operation simulation time can be set freely. The number of cycles required for transfer is 1
It is also possible to determine the number of cycles required for transfer per unit data number, that is, the throughput value, from the accumulated value of 8 and the accumulated value of the transfer data number 17.

According to the first embodiment of the present invention, test patterns 11a and 11b describing operation instruction contents of bus operation models 10a and 10b in a simulation environment.
By using a random function, and a bus transfer performance calculation tool 15 for calculating the bus transfer performance from the output result of the bus monitor 13, and performing a simulation operation using randomly determined parameters. The performance of the system bus 1 can be calculated easily and as accurately as possible without being involved in the content and operation of the S / W operating on the system, and without comprehending the bus contention between the functional modules. This makes it possible to estimate the performance of a large system such as a computer system at an early stage of development. That is, it is possible to judge whether the system performance is right or wrong, and to implement the performance improvement measure and the effect determination without using the actual machine, and it is possible to greatly reduce the development period and the development cost.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a simulation configuration diagram showing Embodiment 2 of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, reference numeral 20 denotes a hierarchical bus having a hierarchical structure with the system bus 1. The hierarchical bus 20 may be a bus having the same specification as the system bus 1 or a bus having a different specification. Also,
These buses may have a master-slave relationship or an equal relationship.

The system bus 1 and the hierarchical bus 20
It has a different address space that is determined in advance, and determines whether or not data is to be transferred to and from the own bus based on the transfer address. Reference numeral 21 denotes a bus bridge, which is a functional module that functionally connects the system bus 1 and the hierarchical bus 20 and enables data transfer between buses according to a control protocol of each bus. In this simulation environment, the bus bridge 21 has an H / H that faithfully simulates the actual operation in order to improve the performance accuracy at the time of transfer between buses.
An equivalent function model such as a W model or operation description data of a development LSI is used.

Reference numeral 22 denotes a hierarchical bus connection bus operation model connected to the hierarchical bus 20. If the specification of the hierarchical bus 20 is equal to that of the system bus 1, the bus operation model 10
There is no problem even if they are the same as a and 10b. The operation of the hierarchical bus connection bus operation model 22 is instructed by a test pattern 23 generated by a random pattern generator 24, similarly to the bus operation models 10a and 10b of the system bus 1 connection. Reference numeral 25 denotes a hierarchical bus connection bus monitor,
It monitors the data transfer operation of the hierarchical bus 20 and outputs a data transfer log 26. Hierarchical bus transfer performance calculation tool 27
Determines the performance of the hierarchical bus 20.

Next, the operation will be described. (1) The hierarchical bus connection bus operation model 22, the hierarchical bus connection bus monitor 25, and the hierarchical bus transfer performance calculation tool 27 connected to the hierarchical bus 20 have the same function as the corresponding part of the system bus 1 connection. (2) The random pattern generator 12 that determines the operation of the system bus 1 adds the hierarchical bus connection bus operation model 22 for the connection of the hierarchical bus 20 as a transfer destination candidate.

(3) Similarly, the random pattern generator 24 that determines the operation of the hierarchical bus 20 adds the bus operation models 10a and 10b of the system bus 1 connection as transfer destination candidates. As a result, data transfer between layers between the system bus 1 and the layer bus 20 is executed in a random manner on the simulation. (4) Other operations are the same as the operations described in the first embodiment. The bus transfer performance calculation tool 15 calculates the data transfer performance of the system bus 1 under the above-described conditions. , The data transfer performance of the hierarchical bus 20 under the above conditions is measured.

In this embodiment, the random pattern generator 24 and the hierarchical bus transfer performance calculation tool 27 on the hierarchical bus 20 side are different. However, when the bus specifications are the same, the system bus 1 side It may be realized by the same function tool. Further, although the random pattern generators 12 and 24 are configured separately, a configuration may be used in which both buses have the same specifications.

The system bus 1 bus operation model 10
The data transfer destinations a and 10b are transmitted to the space of the hierarchical bus 20 and the hierarchical bus connection bus operation model 2 of the hierarchical bus 20 connection.
By fixing the two data transfer destinations in the space of the system bus 1, the operation performance of the bus bridge 21 can be obtained. As a result, for example, when a bus bridge LSI of the system is developed, the data transfer performance of the LSI can be grasped and tuned (adjustment of the number of buffers / FIFOs, operation method study) during design and development, and the performance cannot be achieved. Redevelopment due to such factors can be prevented. In addition,
Although FIG. 3 illustrates a two-layer bus, it may be applied to a bus configuration of three or more layers.

According to the second embodiment of the present invention, an equivalent function model or design data of an LSI developed by itself is applied to the bus bridge 21 connecting the buses, and at the same time, the bus operation model 22 and the Since the bus monitor 25 and the bus transfer performance calculation tool 27 are provided, the system bus 1 and the hierarchical bus 20 can be randomly generated.
Between the layers can be executed on the simulation, the data transfer performance of the system bus 1 and the data transfer performance of the hierarchical bus 20 can be measured, and the performance can be measured in a system hierarchized by a bus bridge or the like. Further, in the case of developing a system bus bridge LSI, the data transfer performance of the LSI can be grasped and tuned (buffer / FIFO number adjustment, operation method study) during design development, and redevelopment due to performance failure, etc. Can be prevented.

Embodiment 3 Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a simulation configuration diagram showing another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 4, 31
a and 32b are parameter files, and this information is input to each of the random pattern generators 12a and 12b. In the figure, the random pattern generator 1
Although 2a and 12b are configured separately, a configuration that is shared may be used.

Next, the operation will be described. First, when considering the configuration of a computer system or the like, the function modules connected to the system bus 1 are often not limited to the same type, and each function module has its own characteristics. For example, graphic LSIs mainly perform data reception and transfer. In addition, for a communication LSI such as Ethernet and SCSI, the data transfer amount is determined by the performance of the communication IO. Further, there are many cases where the access response time to each functional module is individually biased.

As described above, performance can be easily and accurately calculated by randomly generating operation parameters using a random function. However, it is necessary to weight the characteristics of the bus operation form of each functional module in the form of occurrence probability. Thereby, the calculation accuracy is further improved. This embodiment realizes this.

(1) Parameter files 31a, 31b
Are items that determine the operation of the bus operation models 10a and 10b, for example, the amount of data transferred during bus master operation (the frequency of occurrence of transfer: the data transfer capability of the bus is a certain value depending on the bus performance. Increasing the frequency of transfer increases the amount of data transfer), data transfer direction (read / write), number of bursts for each data transfer, data transfer destination (transfer address: target), and access response time during bus slave operation Such information that defines the occurrence probability is stored in a format as shown in FIG. 4, for example.
Note that the target refers to the data transfer request recipient regardless of the data transfer direction. Before executing the simulation, the system designer sets each bus operation model 10
The bus operation characteristics of the functional modules simulated by a and 10b are grasped, and the characteristics are set in the corresponding parameter files 31a and 31b in the form of occurrence probability for each item.

The parameter file (B) shown here
Model A, B, C as "data transfer destination"
However, this corresponds to the bus operation models 10a, 10b, 10
c (10c is not shown). Accordingly, since the model B is its own bus operation model 10b, the transfer probability is set to 0%.

(2) Random pattern generator 12
a, 12b are the corresponding bus operation models 10a, 10b
The test patterns 11a and 11b are generated. At this time, the random pattern generators 12a and 12b use a random function to determine various data transfer parameters in the same manner as in the above-described embodiment, but use the parameter files 31a and 31b to determine the statistical occurrence probability.
A generating means is used to make the occurrence probability set to b.

(3) An example of a method for determining the number of bursts will be described. First, the random pattern generator 12
In a and 12b, the random value to be randomly selected is set to 0-9. Since the random value is a value using a random function, the occurrence probabilities of 0 to 9 are statistically equal. Next, check the parameter settings. For example, in the example of FIG. 4, the burst number setting in the parameter files 31a and 31b is such that the probability of occurrence of the burst number 1 is 30%, the burst number 2 is
4, the probability of occurrence is 30%, and the probability of occurrence of burst numbers 5 to 8 is 40%. Therefore, when the random value is 0 to 2, the number of bursts is 1, and when the random value is 3 to 5, the number of bursts is 2 to 4.
In the case of 5 to 9, the lottery is re-lottered among the burst numbers 5 to 8.

(4) Another specific example of the re-lottery is shown below for the number of response weights. Lottery of the group described in the parameter definition file Number of response weights Number of occurrence probability values Random value 0 20% 0-19 1-340% 20-594 4-630% 60-89 7-9 10% 90-99 Number of response weights If = 1 to 3 is selected, the lottery will be selected again. Number of response weights Random value 10 to 33 2 34 to 66 3 67 to 99

According to the above method, the individual parameters selected by the random pattern generators 12a and 12b are random, but the statistical occurrence probability is based on the occurrence probability set in the parameter files 31a and 31b. (5) By executing a simulation using the generated test patterns 11a and 11b and performing the calculation described in the first embodiment, an arbitrary data transfer operation on the system bus 1 is limited to some extent. Performance calculation in a system including functional modules can be calculated more accurately.

According to the third embodiment of the present invention, various data transfer parameters are determined by the parameter file 31.
Since the occurrence probabilities set in a and 31b are statistically matched, it is possible to make the bus transfer operation characteristics of the individual function modules more faithful to those of the actual system, and an unspecified number of function modules can be used. Even in a system connected by a bus, it is possible to increase the performance calculation accuracy.

Embodiment 4 Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a simulation configuration diagram showing another embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals. In FIG. 5, 41a,
Reference numeral 41b denotes bus operation model identification data, and the test patterns 11a and 11b generated by the random pattern generators 12a and 12b
A set value for determining whether or not the bus operation models 10a and 10b correspond to each other, and the relationship between the set values and the corresponding bus operation models 10a and 10b is predetermined.

Reference numeral 42 denotes a transfer information extracting unit in the bus monitor 13, which interprets a bus protocol operating on a simulation and extracts data transfer information by the method described in the first embodiment. An address extraction unit 43 extracts a transfer destination address of a series of data transfer from a bus protocol operating on a simulation. Reference numeral 44 denotes a timer for measuring the operation simulation time, and reference numeral 45 denotes a log output unit that collects the extracted information and generates the data transfer log 14. The transfer information extraction unit 42, the timer 44, and the log output unit 45 are also incorporated in the bus monitors 13 and 25 of FIG. 1 of the first embodiment and FIG. 3 of the second embodiment.

Next, the operation will be described with reference to FIGS. 6 and 7. In the third embodiment, the method for calculating the data transfer performance of the system bus 1 in a system employing a plurality of arbitrary functional modules has been described. However, the system designer wants to confirm not only the performance of the system bus 1 but also This is whether the functional module can secure the required data transfer performance. This embodiment realizes this.

(1) First, when generating the test patterns 11a and 11b, the random pattern generators 12a and 12b simultaneously read the parameter files 31a and 31b, read the bus operation model identification data 41a and 41b, and generate the test patterns generated by themselves. 11a and 11b are
It recognizes which of the bus operation models 10a and 10b corresponds. (2) The random pattern generators 12a and 12b determine a transfer destination address which is one of the factors of the test patterns 11a and 11b, and the determination means at this time follows the following procedure.

For example, the system that executes the simulation is a system bus address space 47 as shown in FIG.
a, 47c. The random pattern generators 12a and 12b use a random function to determine which of the bus operation models 10a and 10b is to be transferred. For example, in the example shown in FIG. 6, the transfer is for the bus operation model B (the target is model B), and the transfer destination address at this time is 2000 to 2999.

(3) Next, the transfer destination address is determined from the space. At this time, the response space of each bus operation model 10a, 10b receiving the transfer is divided as shown in FIG. 6 according to the bus operation models 10a, 10b transmitting the transfer. For example, the random pattern generator 12a,
12b corresponds to bus operation model A (request source is model A)
If the transfer destination address is recognized as
2099, and a final transfer destination address is randomly selected from the range 2000 to 2099 using a random function.

The bus operation model B response space 47 shown in FIG.
Since b is the target address, the presence of the bus operation model B access space 48b as the request source in this means transfer from the bus operation model B to the same B, so this case does not occur. FIG. 6 shows an access space of a general operation model, including the own bus operation model.

As described above, the transfer destination bus operation model 10
The transfer address determination method described above is adopted for other models other than the models a and 10b. As a result, which bus operation model 10a or 10b has issued a certain data transfer can be determined from the transfer destination address (address issued by the request source).

Next, the address detection method is as follows. The bus monitor 13 uses the transfer information extraction unit 42, the timer 44, and the log output unit 45 to generate the data transfer log 14 by the method described in the first embodiment. Further, in the present embodiment, the transfer destination address is extracted from the data transfer operation of the system bus 1 by the address extraction unit 43 and transmitted to the log output unit 45, so that the data transfer log 14 as shown in FIG. The transfer destination address 44
Add.

Since the logged transfer destination address 49 is determined according to a predetermined rule as described above, if it is decoded, it is possible to identify which bus operation model 10a or 10b issued the data transfer. it can. According to the identification method, the bus transfer performance calculation tool 15 generates a total result 46 for each of the bus operation models 10a and 10b as shown in FIG.

In the above description, a method in which the request source can be determined only by the transfer destination address has been described. For example, an identifier (for example, the transfer source address) that can determine the request source of the data transfer is transferred together with the data. A protocol may be employed. That is, the function module may be any means that can determine the request source when transferring data.

According to the fourth embodiment of the present invention, bus operation model identification data 41a, 41b
An address that can be identified for each of the data buses 0a and 10b is set, and data is transferred based on the address. The address extraction unit 43 in the bus monitor 13 extracts the address. , 10b
Since the function to count the transfer performance for each is provided.
Data transfer performance for each bus operation model 10a, 10b can be collected individually. Therefore, the data transfer performance of each functional module, which is an important condition for building a system, can be easily determined at the early stage of development, shortening the time required for system design and improving the quality. Let it.

Embodiment 5 FIG. Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a simulation configuration diagram showing another embodiment of the present invention. The same parts as those in FIG. 5 are denoted by the same reference numerals. In FIG.
“a” and “46b” are tabulation results of the data transfer performance of each of the bus operation models 10a and 10b output by the bus transfer performance calculation tool, and are sequentially output for each simulation operation. The aggregation results 46a and 46b are the test patterns 11a and 11b of the corresponding bus operation models 10a and 10b, respectively.
Random pattern generator 12 that generates 11b
a and 12b are fed back to be input. It should be noted that the random pattern generators 12a and 12b are different from those described above and are based on the premise that the random pattern generators 12a and 12b adopt a method of sequentially generating test patterns 11a and 11b along with a simulation operation.

Next, the operation will be described. First, in the above-described embodiment, the amount of transfer generated in each of the bus operation models 10a and 10b is set and the data transfer interval is adjusted. However, the data transfer interval is determined on the condition that no bus contention occurs. . However, in an actual simulation, a bus contention occurs due to a plurality of bus operation models generating data transfer, and regardless of the bus transfer capability,
There was a problem that the data transfer amount was lower than the assumed data amount, and it was not possible to accurately grasp the ability value. This embodiment solves such a problem.

(1) The total result 46a of the bus operation model 10a output from the bus transfer performance calculation tool 15 is input to the random pattern generator 12a that has generated the test pattern (A) 11a. (2) The random pattern generator 12a sequentially adjusts the interval at which data transfer is issued so that the tally result approaches the value set in the parameter file (A) 31a,
A test pattern (A) 11a is generated.

(3) The bus operation model 10a reads and executes the adjusted test pattern 11a. (4) The bus transfer performance calculation tool 15 uses the bus monitor 13
With the data transfer log 14 output by the user as an input, a new totaling result 46a is output. (5) The tally result 46a is again input to the random pattern generator 12a, and the test pattern (A) 11
Determine the generation of a.

(6) By feeding back the tally result 46a to the random pattern generator 12a, the tally result 46a can approach the value set in the parameter file (A) 31a. (7) Random pattern generator 12b, parameter file (B) 31b, test pattern (B) 11
b, the same applies to the bus operation model 10b.

According to the fifth embodiment of the present invention, tabulation results 46a, 46 output by bus transfer performance calculation tool 15
b, the parameter files 31a,
By comparing the data transfer amount set in the parameter patterns 31a and 31b with the data transfer amount set in the parameter files 31a and 31b, the test patterns 11a and
Since the random pattern generators 12a and 12b having a function of generating the data transfer amount 11b are provided, when the data transfer amount set in the parameter files 31a and 31b is set as the target value, the combination of the functional modules is the target data transfer amount. This has the effect of making it easy to determine whether or not it can be realized.

Embodiment 6 FIG. Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a simulation configuration diagram showing another embodiment of the present invention. The same parts as those in FIG. 5 are denoted by the same reference numerals. In FIG. 9, 61,
62 is output from the bus operation models 10a and 10b,
This is a request signal for requesting a bus. The bus monitor 13 includes a transfer information extraction unit 42, an address extraction unit 43, a timer 44, and a log output unit 45, which have already been described.
A request detecting unit 63 notifies the log output unit 45 of a bus request when the bus request is received.

Next, the operation will be described. (1) For example, assume that the bus operation model 10b occupies the bus when the bus operation model 10a issues a data transfer request. (2) At this time, although the data transfer of the bus operation model 10a cannot be started, the request detecting unit 63 in the bus monitor 13 sends the request signal 61 to the bus operation model 10a.
a), the log output unit 45
The information is written to the data transfer log 14 through the. For example, the data transfer log 14 includes “REQ” described in FIG.
The request start log 65 is recorded so that the request is from which bus operation model, such as _A ".

(3) At this time, the number of data to be transferred 16 and the number of cycles 17 required for the transfer have no meaning, and are set to 0.
The transfer destination address 49 has no data. (4) After the data transfer of the bus operation model 10b is completed, the bus operation model 10a acquires the bus and the data transfer becomes possible. (5) Regarding data transfer, the data log 66 is recorded in the data transfer log 14 as described above.

(6) The bus transfer performance calculation tool 15 reads the data transfer log 14 and calculates the data transfer log 14 from the request time of the bus operation model 10 a based on the request start log 65 and the actual data transfer time based on the data log 66. By calculating as shown in FIG. 10, the Wait time from the start of one transfer request to the start of transfer is calculated. (7) Further, the number of cycles 17 required for the transfer included in the data log 66 is converted into time and added to the Wait time, thereby calculating the throughput time from the start of one transfer request to the end of the transfer. , Can be aggregated.

According to the sixth embodiment of the present invention, when the request signals 61 and 62 are connected to the bus monitor 13, the bus monitor includes a portion for identifying the start of a transaction, and the bus transfer performance calculation tool 15.
W from request to start of data transfer by internal logic
Since the ait time is measured, the time from the start of one transfer request to the end of the transfer can be collected, that is, the throughput of the bus can be calculated, and the connection to the bus can be performed. This has the effect of facilitating system application determination of the functional module.

Embodiment 7 FIG. Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a simulation configuration diagram showing another embodiment of the present invention. The same parts as those in FIG. 5 are denoted by the same reference numerals. In FIG. 11, 7
Reference numerals 1 and 72 are retry signals output from the respective bus operation models 10a and 10b. The bus monitor 13 has a retry signal 7 in addition to the data processing unit 21, the log output unit 23, and the timer 24 described in the fourth embodiment.
A retry detection unit 73 is provided for detecting a bus retry from the inputs 1 and 72.

Next, the operation will be described. (1) For example, when the bus operation model 10a issues a read request to the bus operation model 10b, the bus operation model 1
0b indicates that data was not ready. (2) At this time, the bus operation model 10b has a mechanism of outputting a retry request to the bus operation model 10a, thereby interrupting the request of the bus operation model 10a, and reading it out again after a while. (3) In the bus monitor 13, in the bus monitor 13, the retry detection unit 73 detects the occurrence of a retry from the retry signal output from the bus operation model, and through the log output unit 23, for example, a retry record 71 shown in FIG. As described above, the number of transfer data is forcibly recorded as 0 in the data transfer log 14. (4) The bus transfer performance calculation tool 15 receives the transfer data number = 0 when totaling the data transfer amount for each of the bus operation models 10a and 10b so as not to affect the total of the performance measurement. As described above, a measurement method that does not cause a measurement error due to retry can be obtained.

According to the seventh embodiment of the present invention, retry signals 71 and 72 are connected to bus monitor 13 to detect occurrence of a retry, and record the number of transfer data at the time of retry as 0 in data transfer log 14. System bus 1 that has retry processing as a bus specification.
In this case, the bus transfer performance can be accurately measured, and the range of application of the bus transfer performance measurement can be expanded.

Embodiment 8 FIG. Hereinafter, an eighth embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a simulation configuration diagram showing another embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals. In FIG. 13, 8
Reference numeral 1 denotes a parameter candidate file, which is a parameter that determines data transfer set in advance by a system designer, such as a data transfer amount (transfer occurrence frequency) during a bus master operation, a data transfer direction (read / write), and data transfer. Number of bursts for each, data transfer destination (transfer address)
Further, a combination of an access response time and the like at the time of the bus slave operation is described, for example, as shown in the drawing. The parameter candidate file 81 is read and processed by the random pattern generators 12a and 12b.

Next, the operation will be described. In the third embodiment, the parameter occurrence probability can be adjusted. However, it is not possible to specify a combination of some parameters. For example, in the case of a general system bus, a parameter combination for improving or deteriorating data transfer performance is determined by the bus specifications and the H / W configuration of the connection module. From such parameters, the test pattern 11
If a mechanism for generating a and 11b is provided, for example, the highest value or the worst value of the data transfer performance in a specific system can be estimated. This embodiment realizes this.

(1) First, the parameter candidate file 81
As described above, several combinations of various parameters that determine the operation of each of the bus operation models 10a and 10b are set in advance by the system designer. (2) Each random pattern generator 12a, 12b
Checks whether a parameter candidate file 81 exists for itself before generating the test patterns 11a and 11b.

(3) If the parameter candidate file 81 does not exist, the subsequent processing follows the operation described in the third embodiment. (4) If the parameter candidate file 81 exists,
The random pattern generators 12a and 12b read the file and simultaneously read the parameter files 31a and
31b is invalidated.

(5) Random pattern generator 12
In order to generate the test patterns 11a and 11b, the parameters a and 12b must determine various parameters. However, the random pattern generators 12a and 12b do not use a random function to determine the parameters themselves, and write the parameters in the parameter candidate file 81. Use a random function to select which of the contents. (6) Each parameter follows the content of the determined candidate. (7) By generating the test patterns 11a and 11b with the parameters determined by the present method, the corresponding bus operation models 10a and 10b execute only the operation according to some specific parameters.

According to the eighth embodiment of the present invention, the operation of each bus operation model 10a, 10b is made to follow one of the parameters set in the parameter candidate file 81 in advance. Many meaningful patterns can be generated, and the performance of the system under specific conditions can be measured, which has the effect of expanding the applicable range of bus transfer performance measurement.

Embodiment 9 Hereinafter, a ninth embodiment of the present invention will be described with reference to the drawings. FIG. 14 is a simulation configuration diagram showing another embodiment of the present invention, and the same parts as those in FIG. 5 are denoted by the same reference numerals. In FIG. 14, 41
Reference numerals a and 41c denote bus operation model identification data, and the test patterns 11a and 11c generated by the random pattern generators 12a and 12c indicate which bus operation model 1
This is a set value for determining whether the value is for 0a or 10c.
The relationship between this set value and the corresponding bus operation model 10a, 10c is predetermined.

Reference numerals 20 and 21 denote hierarchical buses and bus bridges similar to those shown in FIG. The bus operation model 10c is a hierarchical bus 20
It is connected to the. Reference numeral 25 denotes a bus monitor connected to the hierarchical bus, and a bus monitor 1 connected to the system bus 1.
It has the same structure as 3. 26 is a data transfer log generated by the bus monitor 25. Data transfer performance calculation tool 15
Has an interface for inputting a plurality of data transfer logs, and receives data transfer logs 14 and 26 as inputs.

Next, the operation will be described. (1) The random pattern generators 12a and 12c use the parameter file 31 as in the fourth embodiment.
a, 31c and bus operation model identification data 41a, 41c
Is read to generate test patterns 11a and 11c. (2) At this time, after the address space is determined according to the above-mentioned transfer destination address space determination method, the final transfer destination address is selected such that there is no duplication.
This is a device for distinguishing each data transfer from the others and for distinguishing a data transfer occurring on a different bus from a series of data transfers. In the fourth embodiment, the address space is artificially determined, but the address itself is determined by a random function. For example, in FIG. 6, it is artificially determined that the access space from the operation models B to A is 2000 to 2099, but whether the actual transfer address is 2001 or 2050 is determined by a random function. Therefore, there is a possibility that the same address is selected twice, and there is a possibility that the same address is duplicated. In the present embodiment, the above duplication is avoided by further restricting. The method is, for example,
It is conceivable to memorize the addresses generated in the past and, if the same address is selected, to re-select a lottery, or to artificially determine some of the randomly determined address digits so that they do not overlap.

(3) The bus transfer performance calculation tool 15 generates the data transfer logs 14 and 26 generated by the bus monitors 13 and 25.
Is input, data transfer on a different bus is identified as a series of data transfer from the transfer destination address, and its execution time is calculated. As shown in FIG. 15, a data transfer recording the same address in the data transfer log 14 of the system bus and the data transfer log 26 of the hierarchical bus can be identified as a series of data transfers, so that the execution time can be calculated.

According to the ninth embodiment of the present invention, random pattern generators 12a and 12c generate test patterns 11a and 11c composed of non-overlapping addresses, and bus transfer performance calculation tool 15 performs a series of data transfers on different buses. The data transfer execution time can be calculated by distinguishing the data transfer from the data transfer to another layer, so that it is easy to determine on which bus the connected functional module should be connected. There is.

Embodiment 10 FIG. The means for feeding back the data transfer amount for each functional module according to the fifth embodiment includes:
The present invention may be applied to the first, second, and eighth embodiments. In the first, second, and third embodiments, the data transfer probability is not set as in the parameter file (B) 31b shown in FIG. 4 of the third embodiment. Therefore, when a test pattern is generated, the parameter selection probability is adjusted by changing the distribution of random functions 0 to 99. When applied to the eighth embodiment, the probabilities are fixed in the parameter candidate file 81 of FIG. 13, but the fixed probabilities may be changed according to the data transfer amount fed back. .

The request signal detection and recording of the sixth embodiment and the retry signal detection and recording of the seventh embodiment can be applied to all the other embodiments.

Embodiment 11 FIG. Embodiments 1 to 10 above
Is a method for calculating data transfer performance by a simulator, but this calculation method can be used for all computer systems.

[0087]

As described above, the data transfer performance calculation means of the present invention generates various test patterns at random, executes data transfer based on the test patterns, and calculates the data transfer performance. Therefore, the performance of data transfer in various patterns can be measured.

[Brief description of the drawings]

FIG. 1 is a simulation configuration diagram showing a data transfer performance calculation method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a data transfer log output by a data transfer performance calculation method according to the first embodiment of the present invention.

FIG. 3 is a simulation configuration diagram showing a data transfer performance calculation method according to a second embodiment of the present invention.

FIG. 4 is a simulation configuration diagram showing a data transfer performance calculation method according to a third embodiment of the present invention.

FIG. 5 is a simulation configuration diagram showing a data transfer performance calculation method according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating an address space in a data transfer performance calculation method according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a data transfer log output by a data transfer performance calculation method according to a fourth embodiment of the present invention.

FIG. 8 is a simulation configuration diagram showing a data transfer performance calculation method according to a fifth embodiment of the present invention.

FIG. 9 is a simulation configuration diagram showing a data transfer performance calculation method according to a sixth embodiment of the present invention.

FIG. 10 is a diagram showing a data transfer log output by a data transfer performance calculation method according to a sixth embodiment of the present invention.

FIG. 11 is a simulation configuration diagram showing a data transfer performance calculation method according to a seventh embodiment of the present invention.

FIG. 12 is a diagram showing a data transfer log output by the data transfer performance calculation method according to the seventh embodiment of the present invention.

FIG. 13 is a simulation configuration diagram showing a data transfer performance calculation method according to an eighth embodiment of the present invention.

FIG. 14 is a simulation configuration diagram showing a data transfer performance calculation method according to a ninth embodiment of the present invention.

FIG. 15 is a diagram showing a data transfer log output by the data transfer performance calculation method according to the ninth embodiment of the present invention.

FIG. 16 is a block diagram showing a data transfer performance calculation method of a conventional example.

[Explanation of symbols]

1: System bus 10a, 10b, 10c: Bus operation model 11a: Test pattern (A) 11b: Test pattern (B) 11c: Test pattern (C) 12, 12, 12a, 12b, 12c, 24: Random pattern generator (pattern generation Means 13:
Bus monitor 14: Data transfer log 15: Bus transfer performance calculation tool (transfer capacity calculation means) 16: Transfer start time 17: Number of transfer data 18: Number of cycles required for transfer 20: Hierarchical bus 21: Bus bridge (operation model / 22: Hierarchical bus connection bus operation model 23: Test pattern 25: Hierarchical bus connection bus monitor 26: Data transfer log 27: Hierarchical bus transfer performance calculation tool 31a: Parameter file (A) 31b: Parameter file (B) 41a , 41b: Bus operation model identification data 42: Transfer information extraction unit 43: Address extraction unit 44: Timer 45: Log output unit 46: Total result 46a: Bus operation model A total result 46b: Bus operation model B total result 47a: Bus Operation model A response space 47b: Bus operation model B response space 47 c: Bus operation model C response space 48a: Bus operation model A access space 48b: Bus operation model B access space 48c: Bus operation model C access space 48d: Bus operation model D access space 49: Transfer destination address 61: Bus operation model Request signal from 10a 62: Request signal from bus operation model 10b 63: Request detection unit 64: Transaction type 65: Request start log 66: Data log 71: Retry signal from bus operation model 10a 72: From bus operation model 10b Retry signal 7
3: Retry detection unit 74: Retry log 81: Parameter candidate file

Claims (10)

[Claims] 1. A data transfer performance calculation method for calculating a data transfer performance of a system for transferring data between a plurality of functional modules connected via a system bus,
The functional module includes a pattern generating unit that randomly extracts parameters such as a data transfer destination, a transfer direction, and the number of bursts to generate a test pattern, and a bus operation that performs data transfer based on the generated test pattern. A module having a model, and a bus monitor for recording a data transfer state on the system bus;
A data transfer performance calculation method comprising a transfer capacity calculation means for calculating a data transfer capacity such as a data transfer amount based on a record of the bus monitor. 2. A data transfer performance calculation method for calculating a data transfer performance of a system for transferring data between a plurality of functional modules connected via a system bus,
The function module generates a test pattern by extracting a parameter file that sets the extraction probability for each parameter such as the data transfer destination, transfer direction, and number of bursts, and randomly extracting each parameter in this parameter file according to the extraction probability. A bus monitor that records a data transfer state on the system bus, and a bus monitor that records the data transfer status on the system bus. And a transfer capability calculating means for calculating a data transfer capability such as a data transfer amount based on the data transfer performance. 3. A data transfer performance calculation method for calculating a data transfer performance of a system for transferring data between a plurality of functional modules connected via a system bus.
The function module sets a plurality of sets of test patterns in advance by combining parameters such as a data transfer destination, a transfer direction, and the number of bursts, and a pattern generating means for randomly extracting these test patterns; A bus monitor that records a data transfer state on the system bus, and a data transfer capability such as a data transfer amount based on the record of the bus monitor. A data transfer performance calculation method comprising a transfer capacity calculation means for calculating the data transfer performance. 4. The data transfer performance calculation method according to claim 1, wherein an address for each function module is set, and a data request source can be determined for each function module. A means for determining a transfer address or a means for transferring an address of a data request source together with data is provided. When data is transferred, the data is transferred as data corresponding to an address. The bus monitor records the data transfer state corresponding to the address. And a transfer capacity calculating means for calculating a data transfer capacity such as a data transfer amount for each functional module based on the record of the bus monitor. 5. The data transfer performance calculation method according to claim 4, wherein the transfer capability calculation means feeds back the calculated data transfer capacity of each functional module to the corresponding function module, and the pattern generation means of the function module includes: A data transfer performance calculation method, wherein the occurrence probability of a data transfer interval is adjusted so that the fed back data transfer capability approaches the data transfer capability set in the parameter file. 6. The data transfer performance calculation method according to claim 1, wherein the bus monitor detects a request signal requesting the data transfer, and determines a point in time when the request signal is generated and the data transfer. A data transfer performance calculation method, wherein the transfer performance calculation means calculates a wait time or calculates a throughput from both the time points. 7. The data transfer performance calculation method according to claim 1, wherein the bus monitor generates a retry signal (re-data transfer request) generated when the function module cannot transfer data. Data transfer amount, and the retry signal is recorded as zero data transfer amount, and when data transfer based on the retry signal is executed, the data transfer amount at the time of execution is recorded. Calculation method. 8. The data transfer performance calculation method according to claim 1, wherein the system bus and other buses are hierarchically connected via a bus bridge that controls data transfer between these buses. In a configuration in which an arbitrary number of functional modules are connected to each of the buses, the bus monitor records the data transfer state of each of the buses, and the transfer capability calculation means performs the data transfer of each of the buses. A data transfer performance calculation method characterized in that a capacity is calculated. 9. The data transfer performance calculation method according to claim 4, wherein the system bus and other buses are hierarchically connected to each other via a bus bridge that controls data transfer between the buses. In a configuration in which an arbitrary number of function modules are connected to each of the buses, when setting the address for each of the function modules, set the addresses so as not to overlap between the layers, and transfer the data to the function modules. At the time of, transfer the data corresponding to the address,
The bus monitor records the data transfer state corresponding to the address for each bus, and the transfer capability calculation means determines that the data transfer record of each bus of the bus monitor has a data transfer record of the same address, and that the data transfer between the layers is performed. And a data transfer time between layers is calculated. 10. The data transfer performance calculation method according to claim 1, wherein one pattern generation means is used in place of the pattern generation means of any of a plurality of functional modules. A data transfer performance calculation method characterized by the above-mentioned.