JP2000323814A - Manufacturing method of wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board manufacturing method which can remove catalyst particles on an insulator layer exposed through patterning given to a plating layer, without interfering with a subsequent plating process. SOLUTION: A plated copper layer is formed on a layer-insulation layer, to which catalyst particles are given (#2 and #3). When an external layer pattern is made by patterning on the copper plating layer (#4), a layer-insulation layer and catalyst particles appear in the region between patterns. The catalyst particles are removed by using a treatment solution, the main component of which is potassium cyanide (#5). As an insoluble film, the main component of which is copper oxide, is formed on the surface of the external layer pattern in this process, and soft etching is performed immediately after the process to remove the film (#6). After that, a solder resist is formed, and nickel/gold platings are conducted thereaftes (#7 and #8).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board formed by laminating an insulator layer and a conductor layer. More particularly, the present invention relates to a method for manufacturing a wiring board in which a conductor plating layer is formed on an insulator layer by utilizing a catalytic action, and the conductor layer is patterned and further plated thereon.

[0002]

2. Description of the Related Art As a part of a manufacturing process of a wiring board, a conductor layer may be formed on an insulating layer used as an interlayer insulating layer. In this case, it is common to first form a thin layer of a conductor by electroless plating on the insulator layer, and then form a conductor layer of a required thickness on the insulator layer by electroplating at a high plating rate. This is because it is not possible to apply electroplating directly to an insulator. Here, since resins generally used as interlayer insulators do not have a catalytic activity to cause an electroless plating reaction, electroless plating is performed after catalyst particles are attached in advance. The formed conductor layer is subjected to pattern processing, and another plating is further applied to the upper layer. This is for improving bonding properties and appearance.

[0003]

However, the above-mentioned conventional process has the following problems. That is, when the conductor layer formed by plating is patterned, the interlayer insulating layer is partially exposed again. At this time, the catalyst particles adhering to the surface of the interlayer insulating layer are also exposed. Therefore, since the catalyst particles act when another plating is performed thereafter, plating is formed not only on the conductor pattern but also on the interlayer insulating layer. For this reason, the patterns are short-circuited. To avoid this, the same pattern processing must be performed again.

Here, it is known that the catalyst particles are generally fine powders of a noble metal such as palladium and can be removed by dissolving them with an oxidizing solution. Therefore, it is possible to remove the catalyst particles after patterning the conductor layer. However, when the catalyst particles are removed by this method, another plating thereafter cannot be applied to the conductor pattern.

In the above, it seems that there is no problem if the pattern processing is performed after plating the conductor layer on the interlayer insulating layer and then performing the subsequent plating. However, generally, another step such as solder resist formation is performed between the first plating step and another subsequent plating step. The formation of the solder resist needs to be performed after the patterning of the conductor layer. For this reason, such means cannot be often adopted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. That is, an object of the present invention is to provide a method of manufacturing a wiring board in which catalyst particles on an insulating layer exposed by patterning a plating layer are removed without disturbing a subsequent plating step. It is in.

[0007]

According to the present invention, a catalyst layer is attached to an insulating layer, and a plating layer is formed on the insulating layer by the catalytic action of the catalyst particles. (2) a method of manufacturing a wiring board including a step (3) of partially removing the plating layer thereafter.
The catalyst particles exposed on the insulator layer in the step (3) are dissolved and removed with an oxidizing solution (4), and immediately thereafter, an etching treatment is performed to form on the surface of the plating layer in the step (4). The method includes a step of removing the product (5) and thereafter further plating the surface of the plating layer (6).

In this manufacturing method, a starting material is a plate-like material whose surface is mostly an insulating layer. First, catalyst particles are attached to the insulator layer (1), and a plating layer is formed on the insulator layer by the catalytic action (2). This plating layer is usually formed by first using electroless plating and then using electroplating. However, the entire thickness of the plating layer may be formed by electroless plating. This plating layer is partially removed (3), and the remaining portion becomes a pattern layer. That is, pattern processing is performed.

[0009] The insulating layer is exposed where the plating layer has been removed by patterning. On its surface,
There are catalyst particles deposited in (1). The catalyst particles are dissolved and removed with an oxidizing solution (4).
At that time, the surface of the pattern layer is inevitably modified by the action of the oxidizing solution, and a film having no plating activity is generated. If this is left as it is, it will hinder the later plating process (6). Therefore, immediately after (4), an etching process is performed to remove the product (5). As a result, the surface of the pattern layer is brought into a state having the original plating activity.
Therefore, when further plating is performed thereafter (6), a new plating layer is formed on the surface of the pattern layer. At this time, no new plating layer is formed on the surface of the insulating layer since the catalyst particles have been removed in (4). In this way, the intended wiring board is manufactured.

Here, the etching treatment (5) for removing the surface products of the pattern layer must be performed immediately after the removal of the catalyst particles (4). The term “immediately” means that other steps such as formation of a solder resist layer are not interposed. This is because it is extremely difficult to remove the surface products of the pattern layer after passing through this kind of process. This is considered to be because a certain degree of heat history is added in this type of process. Further, unlike the pattern layer itself, the surface product of the pattern layer has no catalytic activity when the subsequent plating step (6) is performed by electroless plating. This is referred to above as having no plating activity.

In a typical example of the method for manufacturing a wiring board according to the present invention,
The catalyst particles are palladium particles, the plating layer in (2) is a copper plating layer, and the oxidizing solution in (4) is a solution containing cyan ions and hydroxide ions. That is, in this case, the palladium particles have catalytic activity for electroless copper plating. Therefore, the plating layer (2) can be formed by electroless copper plating. Alternatively, it can be performed by a combination of electroless copper plating and electrolytic copper plating. On the other hand, palladium
Since it also has catalytic activity when the subsequent plating step (6) is performed by electroless plating, it must be removed from the portion exposed by pattern processing (3). Palladium is
In a solution containing a cyanide ion and a hydroxide ion, a cyano complex is formed and dissolved. Therefore, the palladium particles on the insulating layer exposed by the pattern processing can be removed (4).

However, at that time, a product mainly composed of copper oxide is formed on the surface of the copper pattern layer. Since this product has no plating activity in the later plating step (6), there is a problem if it is used as it is. In particular, if another step is performed without removing this product, the removal of the product becomes extremely difficult due to its heat history. Therefore, if an etching treatment is immediately performed using a solution containing sulfuric acid and hydrogen peroxide (5), this product can be removed. Thus, the surface of the pattern layer becomes metallic copper. Since copper has a plating activity in a later plating step (6), a new plating layer is formed on the copper pattern layer. Here, on the insulating layer other than the pattern layer,
No plating layer is formed. This is because the palladium particles are removed in that part in (4) and there is no plating active.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the present embodiment, a wiring board 1 having the structure shown in FIG. 1 is manufactured. Although only one side is shown in FIG. 1, the back side has almost the same structure.

A wiring board 1 shown in FIG.
An inner layer pattern 3 partially provided on the surface (substantially the same also on the back surface) and an interlayer insulating layer 4 covering the inner layer pattern 3
(The same), an outer layer pattern 5 (the same) provided partially on the surface thereof, and a solder resist layer 9 partially covering the outer layer pattern 5. Then, a via hole 6 (same as above) for establishing conduction between the inner layer pattern 3 and the outer layer pattern 5 and a through hole 7 for conducting the inner layer pattern 3 with the back surface side are provided.
It is provided in some places. The core insulating layer 2, the interlayer insulating layer 4, and the solder resist layer 9 are all made of a resinous insulator. The inner layer pattern 3 is obtained by patterning a copper foil. The outer layer pattern 5 is a copper layer formed by plating. Further, the portion of the outer layer pattern 5 that is not covered with the solder resist layer 9 is made of nickel / metal alloy.
It is covered with a gold plating layer 10. In the present embodiment, the wiring board 1 of FIG. 1 is manufactured according to the process flow schematically shown in FIG.

(# 1, Previous Step) First, a substrate in a state shown in FIG. 3 is manufactured. The substrate in FIG. 3 is in a state before the outer layer pattern 5 in the wiring board 1 in FIG. 1 is formed. The process of obtaining the substrate shown in FIG. 3 from the raw materials is a combination of known techniques, so that detailed description is omitted and only an outline is given.

That is, a through-hole 7 is formed by drilling a hole in a double-sided copper-clad resin plate (for example, “MCL-E679, 12D” manufactured by Hitachi, etc.) as a core substrate, panel plating, and plug filling. Then, pattern processing is performed on the front and back copper foils. At this stage, the core insulating layer 2 and the inner layer pattern 3 in the substrate of FIG. 3 have been formed. Then, dry film on both sides (for example,
DuPont product name “Vialux7081” or the like) is laminated, exposed, and developed. Then, the interlayer insulating layer 4 having a hole at the position of the via hole 6 is built up. Thus, the substrate shown in FIG. 3 is obtained. When a through hole is formed from the outer layer pattern 5 in FIG. 1 to the outer layer pattern on the back surface, a through hole for this is formed at this time. Then, roughening or desmearing is performed for a later step.

(# 2, Catalyst Application) Next, catalyst particles are applied. This is because the interlayer insulating layer 4 has plating activity in the subsequent plating step # 3. That is, a catalyst solution (manufactured by Atotech) containing palladium chloride and an organic acid was added to FIG.
The substrate is immersed, and the catalyst particles of palladium are adhered to the whole. Thereby, as shown in FIG. 4, the palladium catalyst particles 8 are spread over the entire surface. FIG. 4 merely shows the catalyst particles 8 schematically, and does not suggest the actual size or distribution density of the catalyst particles 8.

(# 3, Copper Plating) Next, copper plating is applied to the entire surface. The copper plating layer formed here is used to form the outer layer pattern 5 by pattern processing. For this reason,
First, electroless copper plating is performed, and then electrolytic copper plating is performed. The reason why the electroless copper plating is performed first is that the plating layer is not formed on the non-conductive interlayer insulating layer 4 if the electrolytic copper plating is performed immediately. As a plating solution for electroless copper plating, a plating solution containing EDTA, copper sulfate, formaldehyde, sodium hydroxide, or the like as a main component may be used. According to the electroless copper plating, a copper plating layer is formed on the entire surface including the surface of the interlayer insulating layer 4 by the action of the catalyst particles 8 attached in the previous step # 2.

After forming a copper plating layer having a thickness of about 1 to 4 μm by electroless copper plating, after washing with water and drying, a further copper plating layer is formed by electrolytic copper plating at a high plating rate. At this time, since the interlayer insulating layer 4 is covered with the copper plating layer, the portion where the interlayer insulating layer 4 exists is also subjected to electroplating. The plating solution for the electrolytic copper plating may be a plating solution containing sulfuric acid and copper sulfate as main components, and an additive such as, for example, trade name “Kapalaside GL” manufactured by Atotech Japan. Thereby, a copper plating layer of about 20 μm is formed together with the plating layer of the electroless copper plating. Thus, as shown in FIG. 5, a substrate in a state where the whole is covered with the copper plating layer 51 is obtained. As is clear from the above, the copper plating layer 51 of FIG.
Strictly speaking, it has a two-layer structure of a lower layer formed by electroless copper plating and an upper layer formed by electrolytic copper plating.

(# 4, Patterning) Next, the copper plating layer 51 is subjected to pattern processing. This pattern processing is performed by photoetching. For this purpose, a dry film-shaped etching resist is applied, and is exposed and developed, and then the copper plating layer 51 is etched. As a result, as shown in FIG. 6, a state is obtained in which the copper plating layer 51 is subjected to pattern processing to form the outer layer pattern 5. In this state, the copper plating layer 51 has been partially removed. At that point, the interlayer insulating layer 4 is exposed. Then, at that location, the catalyst particles 8 attached in # 2 above are also exposed. This is because palladium has a smaller ionization tendency than copper and is not dissolved by etching for dissolving the copper plating layer 51.

(# 5, Catalyst Removal) Then, the exposed catalyst particles 8 are removed. This is because if the catalyst particles 8 are left untreated, a plating layer is formed not only on the outer layer pattern 5 but also on the interlayer insulating layer 4 in the step # 8. Here, the catalyst particles 8 are removed using a treatment solution containing potassium cyanide as a main component and further containing sodium hydroxide. In this treatment solution, palladium dissolves as a cyano complex. Specifically, the substrate in the state shown in FIG. 6 is dipped in the processing solution at room temperature for 1 minute, washed with water, dipped again in the processing solution at room temperature for 1 minute without drying, and washed with water. As a result, the exposed catalyst particles 8 are removed, and the state shown in FIG. 7 is obtained. FIG.
In the state (1), the catalyst particles 8 no longer remain at the portion where the interlayer insulating layer 4 is exposed.

In the state shown in FIG. 7, the catalyst particles 8 still exist between the interlayer insulating layer 4 and the outer layer pattern 5 where the outer layer pattern 5 remains. However, this will not be exposed in the table in the future, so it will not harm in # 8 and other subsequent processes. Therefore, this is ignored in the following description.

In the state shown in FIG. 7, although the outer layer pattern 5 has not been dissolved, the film 52 is formed on the skin. The film 52 is formed by reacting the outer layer pattern 5 with the processing solution of # 5, and has a thickness of 0.0
It is about 1 μm. The film 52 is a poorly soluble film containing copper oxide as a main component and has neither conductivity nor catalytic activity of electroless plating.

(# 6, Soft Etch) Then, the film 52
Is removed. This is because if the film 52 is left untreated, the plating layer will not be formed in the subsequent step # 8. Here, a treatment solution containing sulfuric acid and hydrogen peroxide as main components (or a MEC product name “MEC etch”) is used.
The coating 52 may be soft-etched with a commercially available soft-etching solution such as BOND CZ-8100). Specifically, the substrate in the state shown in FIG. 7 is immediately dipped in the processing solution at 40 ° C. without being dried with a drier or the like after the last water washing of # 5. Film 52
This is because once dried, there is a tendency to become more insoluble. Thereby, the film 52 is dissolved and removed. After the film 52 is removed, the substrate is pulled up, washed with water and dried.

As a result, the surface of the outer layer pattern 5 becomes metallic copper. This state is shown in FIG. The thickness of the outer layer pattern 5 in the state of FIG. 8 is reduced by about 2 μm as compared with the outer layer pattern 5 in the state of FIG. 6 as a result of the processes of # 5 and # 6. In # 6, instead of dipping the substrate in the processing solution, the processing solution may be sprayed on the substrate.

(# 7, Solder Resist Formation) Next, a solder resist is formed. For this purpose, a photosensitive resin material is applied to the substrate in the state shown in FIG. 8, dried, exposed and developed, and
Further, it is thermally cured to form a solder resist. As a photosensitive resin material for this purpose, Tamura's product name “C6G
Commercial products such as "2" can be used. When the solder resist is formed, the outer layer pattern 5 is partially covered with the solder resist 9, as shown in FIG. The other part of the outer layer pattern 5 is exposed.

If the solder resist 9 is formed prior to the above-mentioned soft etching (# 6), the film 5
2 becomes extremely insoluble and cannot be removed easily. This is because heat history is applied when the solder resist 9 is formed. Therefore, even if soft etching is performed thereafter, the film 52 cannot be removed, and the plating layer will not be formed in the subsequent step # 8. In the present embodiment, since the solder resist 9 is formed after the film 52 is removed by soft etching (# 6), such a case does not occur.

(# 8, Nickel / Gold Plating) Next, nickel / gold plating is performed. This is for improving the bonding property and appearance of the surface of the outer layer pattern 5. First, a nickel plating layer is formed by electroless plating using a plating solution containing nickel sulfate, citric acid, sodium hypophosphite, boric acid, and a surfactant. Next, a gold plating layer is formed by electroless plating using a plating solution containing potassium gold cyanide, ammonium chloride, sodium citrate, and sodium hypophosphite. As a result, a nickel / gold plating layer 10 is formed in a portion of the outer layer pattern 5 that is not covered with the solder resist 9, and the state shown in FIG. 1 is obtained.

If the catalyst of # 5 is not removed, a nickel / gold plating layer is also formed in a portion other than the outer layer pattern 5 where the interlayer insulating layer 4 is exposed, and a short circuit between the patterns occurs. Occurs. In the present embodiment, #
This is not the case because the catalyst particles 8 are removed from the interlayer insulating layer 4 at 5.

If the soft etching of # 6 is not performed immediately after the removal of the catalyst of # 5, the nickel / gold plating layer 10 is not formed even on the portion of the outer layer pattern 5 which is not covered with the solder resist 9. . For this reason, problems such as a bonding failure later occur. In the present embodiment, the soft etching of # 6 is performed immediately after the removal of the catalyst of # 5 to remove the film 52 on the surface of the outer layer pattern 5, and then the subsequent steps are performed. There is no.

As described above in detail, in the present embodiment, when the catalyst particles 8 are exposed together with the interlayer insulating layer 4 by patterning the copper plating layer 51 as the outer layer pattern 5, the treatment mainly comprising potassium cyanide is performed. The catalyst particles 8 exposed by the solution are removed. Immediately thereafter, soft etching is performed to remove the film 52 formed on the surface of the outer layer pattern 5. For this reason,
At the time of nickel / gold plating, the catalyst particles 8 are not present on the exposed interlayer insulating layer 4, and the surface of the outer layer pattern 5 is metallic copper. Therefore, the nickel / gold plating layer is not generated on the interlayer insulating layer 4 between the patterns, and the nickel / gold plating layer 10 is surely formed on the portion of the outer layer pattern 5 which is not covered with the solder resist. Is generated. Thus, the wiring board 1 without the short circuit between the outer layer patterns 5 and the defect of the nickel / gold plating is manufactured.

The above-described embodiment is merely an example, and does not limit the present invention. Therefore, naturally, the present invention can be variously modified and modified without departing from the gist thereof. For example, the present invention can be applied to a case of manufacturing a multilayer wiring board. Further, the specific structure and composition of each part may be appropriately changed.

[0033]

As apparent from the above description, according to the present invention, the catalyst particles on the insulating layer exposed by patterning the plating layer are removed without hindering the subsequent plating step. A method for manufacturing a wiring board as described above is provided. As a result, a wiring board free from short-circuits between patterns and defective upper layer plating can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a structure of a wiring board manufactured by a manufacturing method according to an embodiment.

FIG. 2 is a process flow chart of a manufacturing method according to an embodiment.

FIG. 3 is a sectional view showing a state where an interlayer insulating layer is formed.

FIG. 4 is a sectional view showing a state where catalyst particles are provided.

FIG. 5 is a sectional view showing a state where a copper plating layer is formed on the entire surface.

FIG. 6 is a cross-sectional view showing a state in which a copper plating layer is processed to form an outer layer pattern.

FIG. 7 is a cross-sectional view showing a state where exposed catalyst particles are removed.

FIG. 8 is a cross-sectional view showing a state where a film formed on an outer layer pattern is removed.

FIG. 9 is a sectional view showing a state where a solder resist is formed.

[Explanation of symbols]

 Reference Signs List 4 interlayer insulating layer 5 outer layer pattern 51 copper plating layer 52 film 8 catalyst particle

Claims (3)

[Claims] And (1) attaching catalyst particles to the insulating layer (1).
In the method for manufacturing a wiring board, the method includes the step of forming a plating layer on the insulating layer by the catalytic action of the catalyst particles (2), and then partially removing the plating layer (3). The catalyst particles exposed on the insulator layer by the process are removed by dissolving with an oxidizing solution (4), and immediately thereafter, an etching treatment is performed to form on the surface of the plating layer at the time of (4). A method for manufacturing a wiring board, comprising the steps of: removing a product (5); and thereafter further plating the surface of the plating layer (6). 2. The method for manufacturing a wiring board according to claim 1, wherein the catalyst particles are palladium particles, the plating layer in (2) is a copper plating layer, and the oxidizing solution is cyan ion and water. A method for manufacturing a wiring board, comprising: an oxide ion. 3. The method for manufacturing a wiring board according to claim 2, wherein the etching solution used in the step (5) contains sulfuric acid and hydrogen peroxide.