JP2000338961A - Image synthesis display device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To realize an image synthesis display device in which an image synthesis position can be arbitrarily specified even when a plurality of pixels are input simultaneously. SOLUTION: An arithmetic unit for outputting a boundary discrimination value representing a deviation between a position coordinate and a display coordinate of an input image, a plurality of combined display memories for storing a plurality of pixel data inputted at the same time, A data selection circuit for outputting the plurality of pixel data to the combined display memory corresponding to the designated display position; and an address selection circuit for selecting an address of the combined display memory based on the boundary determination value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing and displaying apparatus characterized in that in displaying a plurality of graphics images, superimposition by specifying image display positions and simultaneous transfer of a plurality of pixel data to speed up the operation. .

[0002]

2. Description of the Related Art A conventional image synthesizing and displaying apparatus has a configuration shown in FIG.

[0003] First, a horizontal start coordinate 700 of the display is displayed.
When the horizontal start coordinate 701 of the input image is designated, the DMA parameter 702 indicating the range of the data to be transferred is set to DM
A image 705 or a second image 706 sent to the A controller 703 and stored in the frame memory 704
Through the data bus 707 to obtain pixel data 708.

When the data width of one pixel is 8 bits and the data bus width is 32 bits, the DMA controller 7
03 indicates that each of the four pixels simultaneously transferred is
A data valid signal 713 indicating valid or invalid is output.

[0005] The four pixels of the data bus are the write data to the memory, and the first write data 70
9, second write data 710, third write data 711, and fourth write data 712.

In response to this, data valid signal 713
Are a first write control signal 714, a second write control signal 715, a third write control signal 716, and a fourth write control signal 717.

As described above, by adding a signal indicating validity or invalidity to each of the four pixels on the data bus, the horizontal start coordinate 701 of the input image stored in the frame memory 704 is determined in pixel units. Move, and even if the data bus contains pixel data outside the range of the input image,
By designating valid data with the data valid signal 713, only pixel data within the range of the input image can be transmitted by DMA transfer.

Next, a value obtained by removing the lower two bits from the horizontal start coordinate 700 of the display is set as a counter initial value 718, and an address counter 719 is operated.

The address 720 to the memory is commonly output to the first memory 721, the second memory 722, the third memory 723, and the fourth memory 724, which are the four memories for the composite display.

As described above, the operation of overwriting the four pixel data transferred continuously to the four memories is repeated for a plurality of images, whereby a plurality of images can be synthesized.

Here, the relationship between the four memories and the display pixels of the display is as follows.

A first memory 721 indicates a display pixel 0 at address 0, a display pixel 4 at address 1, and a second memory 7
Reference numeral 22 indicates a display pixel 1 at address 0, display pixel 5 at address 1, a third memory 723 indicates display pixel 2 at address 0, display pixel 6 at address 1, and a fourth memory 72.
4 is display pixel 3 at address 0 and display pixel 7 at address 1
Is shown.

Finally, the first read data 72 is stored in a range corresponding to the display areas of the four memories in which the synthesis has been completed.
5, display output data 73 from display output circuit 729 which reads data in the order of second read data 726, third read data 727, and fourth read data 728.
0 is output, and a composite screen is displayed on the display 731.

[0014]

In the image synthesizing and displaying apparatus shown in FIG. 7, as shown in FIG.
The case where the fifth and second images 706 both start from the 0th pixel with respect to the horizontal pixel position 800 of the frame memory 704 is used.

At this time, if the second image 706 is shifted and superimposed on the first image 705, the address counter initial value 7 corresponding to the second image to be overwritten is set.
18 must be shifted.

Since the initial value 718 of the address counter is a value obtained by removing the lower two bits from the horizontal start coordinate 700 of the display, the horizontal start coordinate 700 of the display must be shifted by at least four pixels.

As a result, the first display image 801 and the second display image 802 are shifted from the horizontal display pixel position 803 of the display 731 by 4 pixels horizontally as shown in FIG. That is, the display position can be moved only by an integral multiple of four pixels.

[0018]

In order to solve the above-mentioned problems, an arithmetic unit for outputting a boundary discriminating value indicating a difference between a horizontal start coordinate of an input image and a horizontal start coordinate of a display is provided. A plurality of combined display memories for storing pixel data; a data selection circuit for outputting the plurality of pixel data to the combined display memory corresponding to a display position in which the plurality of pixel data is designated by the boundary determination value; And an address selection circuit for selecting an address of the display memory.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram of an image synthesizing and displaying apparatus according to an embodiment of the present invention.

The operation of displaying a composite image from a plurality of input images will be described below.

First, a display horizontal start coordinate 100 and a horizontal start coordinate 101 of an input image are designated, and a DMA parameter 102 representing a range of data to be transferred is sent to a DMA controller 103. Pixel data is transferred from the first image 105 and the second image 106.

Here, the amount of data transferred at a time by DMA is one line.

This pixel data is stored in the frame memory 104
The data is transferred by DMA through a data bus 107 to the DMA controller 103 and a data bus 108 from the DMA controller 103 to the display circuit.

In this embodiment, it is assumed that the data bus width is 32 bits and the data width of one pixel is 8 bits.

At this time, the data bus 108 can simultaneously transfer data for four pixels.

In the DMA transfer of the input image, the horizontal start coordinate 101 of the input image is changed in units of one pixel, and even if a part of the data bus contains pixel data outside the range of the input image, In order to transfer only the pixel data within the range, four bits of a data valid signal 109 indicating whether the data is valid or invalid is added to the data of four pixels transferred at the same time for each pixel.

Next, an arithmetic unit 112 executes an operation of subtracting the lower two bits 111 of the horizontal start coordinate 101 of the input image from all the bits 110 of the horizontal start coordinate 100 of the display.

The value obtained by removing the lower 2 bits from the operation result of the operation unit 112 is the memory address 113 of the horizontal display start pixel, which is input to the address counter 114 as the initial value of the counter, and operates the counter.

From the address counter 114, a first address candidate 115 and a second address 115, which are two types of addresses used when storing data of four pixels, which are simultaneously input, by a DMA transfer of an input image into a memory. Candidate 1
16 is output.

The lower 2 bits of the operation result of the operation unit 112 are used as a boundary discrimination value 117 indicating the difference between the horizontal start coordinates of the input image and the horizontal start coordinates of the display.

Here, when the value of the lower two bits 111 of the horizontal start coordinate 101 of the input image is larger than the value of all the bits 110 representing the horizontal start coordinate 100 of the display, the negative of the operation result is obtained. The value is output as a bit string using a two's complement representation.

The four pixel data and the 4-bit data valid signal 109 on the data bus 108 are input to the data selector circuit 118, and in accordance with the boundary determination value 117,
First write data 120, second write data 1
21, third write data 122, fourth write data 123, first write control signal 124, second write control signal 125, third write control signal 12
6. The fourth write control signal 127 is output.

The first address candidate 115 and the second address candidate 116 are input to the address selector circuit 119, and the first address 128, the second address 129, Third address 1
30, the fourth address 131 is output.

The first write data 120, the first write control signal 124, and the first address 128 obtained as described above are input to the first memory 132, and the second write data 121 and the second write data The control signal 125 and the second address 129 are input to the second memory 133, and the third write data 122 and the third write control signal 12
6 and the third address 130 are input to the third memory 134, and the fourth write data 123, the fourth write control signal 127 and the fourth address 131 are stored in the fourth memory 13.
Enter 5

The write operation to these four memories is called D
By repeating during MA transfer, one of the input images
Pixel data for a line is stored in four memories.

The DMA transfer for one line of the second image 106 is performed after the DMA transfer for one line of the first image 105, so that the second image 106 is superimposed on the first image 105. The display image of the combined one line,
The data is stored in four memories: a first memory 132, a second memory 133, a third memory 134, and a fourth memory 135.

Finally, after the completion of the synthesis of the image data transferred by the DMA transfer, the first read data 136, the second read data 137, the third read data 138, and the fourth read data 136 which are outputs from the four memories. Read data 13
9 is input to the display output circuit 140, and the display output data 141 in the display order is selected and output to the display 142.

FIG. 2 shows a combination of inputs when data bus 108 and data valid signal 109 are input to data selector circuit 118.

The four pixel data on the data bus 108 are respectively divided into first pixel data 201 and second pixel data 2
02, third pixel data 203, fourth pixel data 20
4, the data valid signal 109 corresponds to the first pixel data valid signal 205, the second data valid signal 206, the third data valid signal 207, and the fourth data valid signal 208 corresponding to the four pixel data. Separate.

The data and the valid signal for the four pixels are divided into the data and the valid signal for one pixel, and the first register 209, the second register 210, and the third register 21
1, held in the fourth register 212 and output to the data selector circuit 118 as a first selector input 213, a second selector input 214, a third selector input 215, and a fourth selector input 216.

FIG. 3 shows a data selector circuit 118 for selecting the four selector inputs output in FIG. 2 according to the boundary determination value 117.

The reference numeral 301 in FIG.
2 is a first data selector for selecting the first write data 120 and the first write control signal 124.

The first data selector 301 selects the first selector input 213 when A = 00, and selects the second selector input 214 when A = 11, where A represents the boundary discrimination value 117. , A = 10, the third selector input 215 is selected, and when A = 01, the fourth selector input 216 is selected.

In FIG. 3A, this is expressed by writing the conditions of A = 00, A = 01, A = 10, and A = 11 in each selector input.

Similarly, FIGS. 3 (2), (3) and (4) show that
A second data selector 302, a third data selector 303, and a fourth data selector 304 for selectively outputting data and a control signal to the second memory 133, the third memory 134, and the fourth memory 135 are shown.

305, 306, 307, 308 in FIG.
9 shows the data paths of the four data selectors when the boundary determination value 117 is A = 01.

FIG. 4 shows a circuit of the address counter 114.

Memory address 113 of horizontal display start pixel
Is input as the initial value 401 of the counter, the +1 counter 402 which increases in accordance with the DMA transfer operates.

This counter value is stored in the first address candidate 11
5 and the value obtained by adding 1 to this address is output as the second address candidate 116.

FIG. 5 shows an address selector circuit 119 for selecting the two address candidates output in FIG. 4 according to the boundary discrimination value 117.

In FIG. 5A, reference numeral 501 denotes the first memory 13.
2 is a first address selector that selects a first address 128 to address 2.

When the boundary determination value 117 is represented by A, the first address selector 501 selects the first address candidate 115 when A = 00, and selects the second address candidate 115 when A = 01 or 10 or 11 To select the address candidate 116 of.

In FIG. 5A, this is expressed by writing the conditions of A = 00, A = 01, A = 10, and A = 11 in the input of each address candidate.

Similarly, FIGS. 5 (2) and 5 (3) show a second address selector 502 and a third address selector 503 for selectively outputting an address to the second memory 133 and the third memory 134, respectively. .

FIG. 5D shows the fourth memory 135.
Indicates that the fourth address 131, which is the address to, is always the first address candidate 115.

504, 505, 506, 507 in FIG.
Shows data paths of four address selectors when the boundary determination value 117 is A = 01.

An operation example of the above circuit will be described with reference to FIG.

FIG. 6A shows a first image 105 and a second image 106 in the frame memory 104.

Reference numeral 600 denotes a pixel position in the frame memory.

Here, the data bus width is 32 bits,
It is assumed that four pixels can be transferred at the same time.

FIG. 6 (2) shows the positions of the first display image 601 and the second display image 602 where the first image 105 and the second image 106 are displayed on the display 142.

For the first image 105, the horizontal start coordinates 100 of the display and the horizontal start coordinates 101 of the input image are both 0, and the boundary determination value 117 is 00.

In this case, in the data selector circuit, pixels at pixel positions 0, 1, 2, and 3 of the input image are transferred to pixels at display pixel positions 0, 1, 2, and 3 on the display. Pixel positions 0, 1,
The addresses are all 0 for pixels 2 and 3, and the addresses are all 1 for pixels at pixel positions 4, 5, and 6 in the input image.

As a result, in the frame memory 104, the pixels of one line from 0 to 6 at the pixel position 600 which is the range of the first image 105 are displayed on the display 142.
The upper display pixel position 603 is stored in the memory corresponding to one line from 0 to 6.

The second image 106 is placed on the first image 105
Is superimposed one pixel to the right, the horizontal start coordinate 100 of the display is 1, the horizontal start coordinate 101 of the input image is 0, and the boundary determination value 117 is 01.

Considering the transfer pixel 604 of the second image,
Since the data selector circuit 118 shows an example in which the boundary determination value 117 is 01 in FIG. 3, the pixels at the pixel positions 0, 1, 2, and 3 of the transfer pixel 604 of the second image are respectively The pixel at pixel position 0 is the display pixel position 60
3 becomes the second write data 121 corresponding to 1,
The pixel at the pixel position 1 becomes the third write data 122 corresponding to the display pixel position 603 of 2, and the pixel at the pixel position 2 becomes the fourth write data 123 corresponding to the display pixel position 603 of 3, The pixel at pixel position 3 is the first write data 120 whose display pixel position 603 corresponds to 4.
become.

The address selector circuit 119 shows an example in which the boundary discrimination value 117 is 01 in FIG. 5, so that the address of the first memory 132 is 1 and the other second memory 133 is The memory addresses of the memory 134 and the fourth memory 135 are 0.

In this way, pixel positions 0,
Pixels 1 and 2 are transferred to pixels at display pixel positions 1, 2 and 3 of the display whose memory address is 0, and pixels at pixel position 3 of the input image are displayed on the display at a memory address of 1 The image is transferred to the pixel at pixel position 4 and the transfer pixel 604 of the second image can be output to the display pixel 605 of the second display image. Therefore, the first display image 601 and the second display image 602 can be overlapped at an arbitrary position.

The present invention is not limited to a data bus width of 32 bits and a pixel data width of 8 bits. The data bus width and the pixel data width are arbitrary positive integers, and the data bus width is a pixel data width. This is applied when the data bus has a width equal to or larger than the width and the pixel data has a power of 2 in the data bus.

According to the present invention, an image position when a plurality of images are superimposed can be set to an arbitrary pixel position. However, in a circuit configured with a data bus width of 32 bits and a pixel data width of 8 bits, Instead of the pixel data of
When used in a configuration having two 4-bit pixel data, the image position when superimposing a plurality of images can be specified for every two pixels. This is also applied to the case where designation is made for each pixel of the power of 2.

The present invention is not limited to the amount of data transferred by DMA at one time, but includes a configuration in which data of one line is DMA-divided a plurality of times and a method of transferring data of a plurality of lines. The present invention is also applied to a configuration in which DMA transfer is performed at one time.

[0073]

As described above, according to the present invention, in a combined display for simultaneously transferring a plurality of pixels and combining at high speed,
The position of superimposition of a plurality of images can be set arbitrarily. The higher the degree of parallelism in simultaneous transfer, the greater the specified interval of superposition positions. Therefore, the higher the speed, the greater the effect.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an image synthesis and display device of the present invention.

FIG. 2 is a configuration diagram of pixel data on a data bus.

FIG. 3 is a data selection circuit diagram.

FIG. 4 is an address counter circuit diagram.

FIG. 5 is an address selection circuit diagram.

FIG. 6 is an explanatory diagram of image synthesis display.

FIG. 7 is a diagram showing a conventional image synthesis display device.

FIG. 8 is an explanatory diagram of a conventional image synthesis display.

[Explanation of symbols]

Reference Signs List 100 Horizontal start coordinate of display 101 Horizontal start coordinate of input image 102 DMA parameter 103 DMA controller 104 Frame memory 105 First image 106 Second image 107 Data bus from frame memory to DMA controller 108 From DMA controller to display circuit Data bus 109 Data valid signal 110 All bits of horizontal start coordinate value of display 111 Lower 2 bits of horizontal start coordinate value of input image 112 Operation unit 113 Memory address of horizontal display start pixel 114 Address counter 115 First address candidate 116 Second address candidate 117 Boundary determination value 118 Data selector circuit 119 Address selector circuit 120 First write data 121 Second write data 122 Third write data 123 Fourth Write data 124 First write control signal 125 Second write control signal 126 Third write control signal 127 Fourth write control signal 128 First address 129 Second address 130 Third address 131 Fourth address 132 first memory 133 second memory 134 third memory 135 fourth memory 136 first read data 137 second read data 138 third read data 139 fourth read data 140 display output circuit 141 display Output data 142 Display 201 First pixel data 202 Second pixel data 203 Third pixel data 204 Fourth pixel data 205 First data valid signal 206 Second data valid signal 207 Third data valid signal 208 Fourth data valid signal 209 first register 210 second register 211 third register 212 fourth register 213 first selector input 214 second selector input 215 third selector input 216 fourth selector input 301 first data selector 302 Second data selector 303 Third data selector 304 Fourth data selector 305 Example of selection of first data selector 306 Example of selection of second data selector 307 Example of selection of third data selector 308 Fourth data Example of selection of selector 401 Initial value of counter 402 +1 Counter 403 +1 Adder 501 First address selector 502 Second address selector 503 Third address selector 504 Example of selection of first address selector 505 Example of second address selector Selection example 506 Selection example of third address selector 507 Path of fourth address 600 Horizontal pixel position of frame memory 601 First display image 602 Second display image 603 Horizontal display pixel position of display 604 Transfer pixel position of second image Example 605 Example of display pixel of second display image 700 Horizontal start coordinate of display of conventional example 701 Horizontal start coordinate of input image of conventional example 702 DMA parameter of conventional example 703 DMA controller of conventional example 704 Frame memory of conventional example 705 First image of conventional example 706 Second image of conventional example 707 Data bus from conventional frame memory to DMA controller 708 Data bus from conventional DMA controller to display circuit 709 First write data of conventional example 710 Second write data of conventional example 711 Third write data 712 Conventional fourth write data 713 Conventional data valid signal 714 Conventional first write control signal 715 Conventional second write control signal 716 Conventional third write control signal 717 Fourth write control signal of conventional example 718 Initial value of address counter of conventional example 719 Address counter of conventional example 720 Address of conventional example 721 First memory of conventional example 722 Second memory of conventional example 723 of conventional example Third memory 724 Fourth memory of conventional example 725 First read data of conventional example 726 Second read data of conventional example 727 Third read data of conventional example 728 Fourth read data of conventional example 729 Conventional Example display output circuit 730 Conventional example display output data 731 Conventional example display 80 0 Horizontal pixel position of conventional frame memory 801 First display image of conventional example 802 Second display image of conventional example 803 Horizontal display pixel position of conventional display

Claims (1)

[Claims] An arithmetic unit for outputting a boundary discrimination value indicating a difference between a horizontal start coordinate of an input image and a horizontal start coordinate of a display; a plurality of combined display memories for storing a plurality of pixel data input simultaneously; A data selection circuit that outputs the plurality of pixel data to the combined display memory corresponding to a display position specified by the boundary determination value; and an address selection circuit that selects an address of the combined display memory based on the boundary determination value. Image synthesis display device.