JP2000353807A - Method for manufacturing thin film transistor, method for manufacturing active matrix substrate, and electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a TFT which is enhanced in transistor characteristics, even if a polycrystalline semiconductor film obtained by making an amorphous semiconductor undergo laser annealing process is used as an active layer, a method of manufacturing an active matrix substrate, and an electro-optic device provided with an active matrix substrate formed by this method. SOLUTION: In a method of manufacturing an active matrix substrate used for an electro-optic device such as a liquid crystal panel, when an amorphous semiconductor film 100 formed on a substrate 30 is turned polycrystalline by laser annealing and formed into a TFT, an oxide film present on the surface of the semiconductor film 100 at the time when laser annealing is carried out is set to 1/50 or smaller than the thickness of a gate insulating film, and in a laser annealing process, every point on the surface of the semiconductor film 100 is irradiated 20 to 200 times with a laser beam.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (hereinafter referred to as TFT) using a polycrystalline semiconductor film obtained by performing laser annealing on an amorphous semiconductor film as an active layer. The present invention relates to a method of manufacturing an active matrix substrate using a manufacturing method, and an electro-optical device using the active matrix substrate manufactured by the method.

[0002]

2. Description of the Related Art In manufacturing a TFT used as an active element of a liquid crystal display, a low-temperature process is being adopted so that an inexpensive glass substrate can be used instead of a quartz substrate. The low-temperature process generally means that the highest temperature of the process (the highest temperature at which the entire substrate simultaneously rises) is less than about 600 ° C. (preferably less than 500 ° C.), whereas the high-temperature process means the highest temperature of the process (the entire substrate). At the same time) is about 800 ° C or more, and 700 ° C such as thermal oxidation of silicon.
A high-temperature process of up to 1200 ° C. is performed.

However, in a low-temperature process, it is impossible to directly form a polycrystalline semiconductor film on a substrate. Therefore, an amorphous semiconductor film is formed using a plasma CVD method or a low-pressure CVD method. After this, it is necessary to crystallize this semiconductor film. As a method of this crystallization, for example, S
There are methods such as a PC method (Solid Phase Crystallization) and an RTA method (Rapid Thermal Annealing), but laser annealing (ELA: Excimer Laser Anion) by irradiating an excimer laser beam using XeCl is used.
nealing) suppresses the temperature rise of the glass substrate,
In addition, since polycrystalline Si having a large grain size can be obtained, it has recently become mainstream.

In a method of manufacturing a polycrystalline semiconductor film using this laser annealing method, first, as shown in FIG. 3A, a substrate 3 made of glass or the like cleaned by ultrasonic cleaning or the like is used.
0, the substrate temperature is about 150 ° C to about 450 ° C
Under the above temperature conditions, as shown in FIG. 3 (B), a base protective film 301 made of a silicon oxide film is formed on the entire surface of the substrate 30 by a plasma CVD method. Next, when the substrate temperature is about 15
An amorphous silicon (amorphous) semiconductor film 100 is formed on the entire surface of the substrate 30 by a method such as a plasma CVD method under a temperature condition of 0 ° C. to about 450 ° C. Next, FIG.
As shown in (C), laser annealing is performed by irradiating the semiconductor film 100 with laser light. In this laser annealing step, for example, as shown in FIG. 4, a line beam L0 (for example,
The semiconductor film 100 is irradiated with a laser beam having a repetition frequency of a laser pulse of 200 Hz (line beam), and the irradiation region is shifted in the Y direction. As a result, the amorphous semiconductor film 100
Melts once and crystallizes through a cooling and solidification process. In this case, the irradiation time of the laser beam to each region is very short, and the irradiation region is local to the entire substrate, so that the entire substrate is not heated to a high temperature at the same time.

[0005]

However, crystallization by laser annealing has the problem that the surface of the polycrystalline semiconductor film after crystallization has large irregularities. Using a semiconductor film having such large surface irregularities, T
When an FT is manufactured, the gate breakdown voltage is reduced, and this hinders a reduction in off-leak current or an improvement in reliability.

In order to solve such a problem, for example, Japanese Patent Laid-Open Publication No. 06-097196 discloses that an oxide film is formed on the surface of an amorphous semiconductor film and then irradiated with a laser, and then the oxide film is formed. There is disclosed a method of obtaining a smooth polycrystalline semiconductor film by removing GaN. However, in this method, since the laser is irradiated through the oxide film, the effective intensity of the laser is reduced when the oxide film is too thick, while the semiconductor film after polycrystallization is formed when the thickness of the oxide film is halfway. On the contrary, there is a problem that unevenness becomes severe on the surface.
Also, when removing the oxide film, a polycrystalline semiconductor film,
Alternatively, there is a problem that the substrate is damaged.

On the other hand, there is a method of improving the gate breakdown voltage by increasing the thickness of the gate insulating film when manufacturing a TFT. However, when the thickness of the gate insulating film is increased, the threshold voltage is linearly proportional to the thickness of the gate insulating film. Because of the correlation, there is a problem that the threshold voltage increases and the switching voltage of the TFT also increases.

[0008] In view of the above problems, an object of the present invention is to provide:
Even when a polycrystalline semiconductor film obtained by subjecting an amorphous semiconductor film to laser annealing is used as an active layer, a method for manufacturing a TFT having good transistor characteristics, and a method for manufacturing an active matrix substrate using this manufacturing method. An object of the present invention is to provide a manufacturing method and an electro-optical device using an active matrix substrate manufactured by the method.

[0009]

In order to solve the above problems, the present invention provides a film forming step of forming an amorphous semiconductor film on a substrate, and repeating a laser beam on the amorphous semiconductor film. A laser annealing step of irradiating the semiconductor film to make the semiconductor film polycrystalline, and a gate insulating film forming step of forming a gate insulating film on the surface of the polycrystalline semiconductor film, wherein the laser annealing step is performed. At the time of performing, the thickness of the oxide film existing on the surface of the amorphous semiconductor film is set to 1/50 or less of the thickness of the gate insulating film, and in the laser annealing step, the thickness of the surface of the semiconductor film is reduced. It is characterized by irradiating a laser beam 20 times or more per one place.

The present inventor has repeatedly examined the relationship between the thickness of the oxide film on the surface of the amorphous semiconductor film before laser annealing and the size of the irregularities on the surface of the polycrystalline semiconductor film after laser annealing. If the thickness of the oxide film formed on the surface of the amorphous semiconductor film at the time of performing the laser annealing step is small, unevenness on the surface of the polycrystalline semiconductor film after the laser annealing can be reduced. I got a new finding. In addition, as a result of the present inventors repeatedly examining the relationship between the roughness of the surface of the polycrystalline semiconductor film and the thickness of the gate insulating film, the roughness of the surface of the polycrystalline semiconductor film was found to be 1 / th of the thickness of the gate insulating film. When the value is 5 or less, a new finding is obtained that the gate breakdown voltage does not significantly decrease. Therefore, in the present invention, the thickness of the oxide film formed on the surface of the amorphous semiconductor film at the time of performing the laser annealing step is set to be 1/50 or less of the thickness of the gate insulating film. The size of the irregularities on the surface of the polycrystalline semiconductor film after the above is reduced to 1/5 or less of the thickness of the gate insulating film, whereby the decrease in gate breakdown voltage is kept within 10%. Further, in the laser annealing step, when the laser light is repeatedly irradiated, if the number of times of irradiation is less than 20, even if there is no oxide film on the semiconductor film surface at the time of starting the laser annealing,
We also obtained the finding that there is a tendency that the unevenness cannot be made sufficiently small. Therefore, in the present invention, the number of times of laser light irradiation in the laser annealing step is set to 20 or more, and irregularities generated on the surface of the polycrystalline semiconductor film after the laser annealing step are suppressed. Therefore, even when a polycrystalline semiconductor film obtained by performing laser annealing on an amorphous semiconductor film is used as an active layer, a TFT having good transistor characteristics in terms of threshold voltage, gate withstand voltage, and the like can be obtained. Can be manufactured.

In the present invention, in the laser annealing step, it is preferable that a laser beam is irradiated at least 80 times at one location on the surface of the semiconductor film.

In the present invention, it is preferable that in the laser annealing step, the laser light irradiation is performed 200 times or less per spot on the surface of the semiconductor film. When laser light is repeatedly irradiated in the laser annealing step, the more the number of times of irradiation, the more the crystallinity of the semiconductor film is improved and the TFT
Although the on-current of the TFT increases, the on-current of the TFT tends to decrease when the peak exceeds a certain number of times and then exceeds 200 times. Therefore, in the present invention, it is preferable to manufacture a TFT having a large on-current by limiting the number of times of laser light irradiation in the laser annealing step to 200 times or less.

In the present invention, when repeatedly irradiating a laser beam in the laser annealing step, a line beam is used as the laser beam, and an irradiation region of the line beam is partially irradiated in a direction orthogonal to a longitudinal direction of the line beam. It is preferable to irradiate the surface of the semiconductor film with a laser beam while superimposing. For example, if the width of the irradiation area of the line beam is 500 μm, the laser beam is irradiated 200 times when viewed from one place of the semiconductor film only by shifting the line beam at a pitch of 2.5 μm. Further, if the line beam is shifted at a pitch of 25 μm, the laser beam is emitted 20 times from one position of the semiconductor film.
That is, if the line beam is shifted at a pitch of 6 μm, the laser light is irradiated about 80 times when viewed from one place of the semiconductor film.

In the present invention, when the thickness of the oxide film formed on the surface of the amorphous semiconductor film at the time of performing the annealing step is set to be not more than 1/50 of the thickness of the gate insulating film, For example, after the film forming step and before performing the laser annealing step, an etching step of removing an oxide film formed on the surface of the amorphous semiconductor film is performed. In the present invention, in this etching step,
For example, wet etching is performed on the surface of the amorphous semiconductor film using an etching solution containing hydrogen fluoride. In the etching step, dry etching using an etching gas containing fluorine may be performed on the surface of the amorphous semiconductor film. Here, after performing the etching step and before performing the laser annealing step, an exposure time during which the semiconductor film is exposed to an oxygen-containing atmosphere is T time, and a thickness of the gate insulating film is t angstroms. When the exposure time and the thickness of the gate insulating film, the following equation

It is preferable that the relationship be satisfied. On the surface of the semiconductor film after the oxide film is removed by the etching step, the growth speed of the oxide film is generally about 10 Å / hour at most in the atmosphere up to オ ン 50 Å, so that the thickness of the gate insulating film is reduced. Assuming that t (angstrom), the allowable thickness of the surface oxide film is t
/ 50 (angstrom) or less. Therefore, the exposure time in the air after removing the oxide film in the etching step may be t / 50/10 = t / 500 (hour).

In the present invention, when the thickness of the oxide film formed on the surface of the amorphous semiconductor film at the time of performing the annealing step is set to be not more than 1/50 of the thickness of the gate insulating film, After the film forming step, a method may be used in which the surface of the amorphous semiconductor film is kept in a non-oxidizing atmosphere and is not exposed to an oxidizing atmosphere until the laser annealing step is performed.

In the present invention, the laser annealing step is preferably performed in a non-oxidizing atmosphere.

Such a method of manufacturing a TFT can be used, for example, to manufacture at least a TFT for pixel switching on an active matrix substrate of an electro-optical device.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but before that, common contents (TFT structure and basic manufacturing method thereof) will be described. Keep it.

[Structure of TFT] FIGS. 1 and 2 are a plan view and a sectional view of a TFT, respectively. T shown here
The FT is formed as a pixel switching TFT on an active matrix substrate of a liquid crystal device (electro-optical device) described later. That is, as shown in FIG. 1, one of a group of pixels formed on an active matrix substrate is shown by extracting a part of a pixel region, a pixel including a plurality of transparent ITO (Indium Tin Oxide) films in a matrix. An electrode 8 is formed, and each of these pixel electrodes 8
Are connected to TFTs 10 for pixel switching. Also, along the vertical and horizontal boundaries of the pixel electrode 8,
A data line 90, a scanning line 91, and a capacitance line 92 are formed, and the TFT 10 is connected to the data line 90 and the scanning line 91. That is, the data line 90 is electrically connected to the source region 16 of the TFT 10 via the contact hole, and the pixel electrode 8 is electrically connected to the drain region 17 of the TFT 10 via the contact hole. The scanning line 91 extends so as to face the channel forming region 15 of the TFT 10. Note that the storage capacity 40
Is a silicon film 40a (semiconductor film / shaded region in FIG. 1) corresponding to an extended portion of a silicon film 10a (semiconductor film / shaded region in FIG. 1) for forming the pixel switching TFT 10. ) Is made to be conductive, and the lower electrode 41 is used as a lower electrode 41, and a capacitance line 92 is overlapped on the lower electrode 41 as an upper electrode.

FIG. 2 shows a cross section taken along line AA 'of the pixel region thus configured. As can be seen from this figure, an insulating underlying protective film 301 is formed on the surface of the transparent substrate 30 which is the base of the active matrix substrate 11.
Are formed, and island-shaped silicon films 10a and 40a are formed on the surface of the underlying protective film 301. A gate insulating film 13 having a thickness of about 1000 angstroms is formed on the surface of the silicon film 10a.
The scanning line 91 passes as a gate electrode on the surface of No. 3.
In the silicon film 10a, a region facing the scanning line 91 via the gate insulating film 13 is a channel forming region 15.
It has become. A source region 16 having a low-concentration source region 161 and a high-concentration source region 162 is formed on one side of the channel forming region 15, and a low-concentration drain region 171 and a high-concentration drain region 172 are provided on the other side. A drain region 17 is formed.

A first interlayer insulating film 18 and a second interlayer insulating film 19 are formed on the surface side of the pixel switching TFT 10 configured as described above, and the data formed on the surface of the first interlayer insulating film 18 is formed. The line 90 corresponds to the first interlayer insulating film 18.
Is electrically connected to the high-concentration source region 162 through a contact hole formed in the semiconductor device. First interlayer insulating film 18
A drain electrode 14 formed at the same time as the data line 90 is formed on the surface of the substrate, and the drain electrode 14 is electrically connected to the high-concentration drain region 172 via a contact hole formed in the first interlayer insulating film 18. are doing. The pixel electrode 8 is formed on the surface of the second interlayer insulating film 19, and the pixel electrode 8 is electrically connected to the drain electrode 14 via a contact hole formed in the second interlayer insulating film 19. I have. Here, the second interlayer insulating film 19 is formed of a lower interlayer insulating film 191 obtained by firing a polysilazane coating film and a CV
It has a two-layer structure with an upper interlayer insulating film 192 made of a silicon oxide film formed by the method D. Pixel electrode 8
A surface protection film 45 made of a silicon oxide film or an organic film is formed on the surface side of the surface protection film 45, and an alignment film 46 made of a polyimide film is formed on the surface of the surface protection film 45. The alignment film 46 is a film obtained by performing a rubbing process on a polyimide film.

The lower electrode 41 made of a high-concentration region is formed on the silicon film 40a extending from the high-concentration drain region 172. The capacitance line 92 faces the lower electrode 41 via an insulating film (dielectric film) formed simultaneously with the gate insulating film 13. Thus, the storage capacitor 40 is formed.

Here, the TFT 10 preferably has an LDD (lightly doped drain) structure as described above, but implants impurity ions into regions corresponding to the low-concentration source region 161 and the low-concentration drain region 171. It may have an offset structure that is not performed. Also,
The TFT 10 may be a self-aligned TFT in which high-concentration source and drain regions are formed in a self-aligned manner by implanting impurity ions at a high concentration using the scanning lines 91 as a mask. In this embodiment, the TFT 10 has a single gate structure in which only one gate electrode (scanning line 91) is arranged between the source and drain regions. However, even if two or more gate electrodes are arranged between them. Good. At this time, the same signal is applied to each gate electrode.
If the TFT 10 is formed of a dual gate (double gate) or triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced and a stable switching element can be obtained.

[TFT Manufacturing Method]
A method of manufacturing the FT 10 will be described with reference to FIGS. 3, 5, 6, 7, and 8 are process cross-sectional views illustrating a method of manufacturing the active matrix substrate 11 of the present embodiment.
This corresponds to a cross section taken along line A '. However, here, only the method of manufacturing the pixel TFT 100 will be described.
The description and illustration of the method of manufacturing the storage capacitor 40 and the like are omitted. FIG. 4 is a schematic configuration diagram of the laser annealing apparatus.

In order to manufacture a TFT on a glass substrate, first, it is necessary to form a polycrystalline semiconductor film on the glass substrate without deforming the glass substrate. In order to form a polycrystalline semiconductor film under such restrictions, FIG.
As shown in FIG. 3B, after preparing a substrate 30 made of glass or the like which has been cleaned by ultrasonic cleaning or the like, the substrate temperature is about 150 ° C. to about 450 ° C., as shown in FIG.
Base protective film 3 made of a silicon oxide film on the entire surface of substrate 30
01 is formed by a plasma CVD method. As the raw material gas at this time, for example, a mixed gas of monosilane and laughing gas, TEOS and oxygen, or disilane and ammonia can be used.

Next, the substrate temperature is increased from about 150 ° C. to about 450 ° C.
A semiconductor film 100 made of an amorphous silicon film is formed on the entire surface of the substrate 30 by a plasma CVD method under a temperature condition of ° C. As the source gas at this time, for example, disilane or monosilane can be used (film formation step).

Next, as shown in FIG. 3C, laser annealing is performed by irradiating the semiconductor film 100 with laser light (laser annealing step).

In this laser annealing step, as shown in FIG. 4, the irradiation area L of the laser beam is in the X direction (main scanning direction).
The semiconductor film 100 is irradiated with a long line beam L0 (for example, a line beam having a laser pulse repetition frequency of 200 Hz). As a result, the amorphous semiconductor film 1
00 is once melted and crystallized through a cooling and solidification process.
In this case, the irradiation time of the laser beam to each region is very short, and the irradiation region is local to the entire substrate, so that the entire substrate is not heated to a high temperature at the same time. Therefore, the glass substrate used as the substrate 30 is inferior in heat resistance as compared with the quartz substrate, but is not deformed or cracked by heat.

In an annealing apparatus 300 shown in FIG. 4, an XY stage 310 on which a glass substrate 30 on which a semiconductor film 100 made of an amorphous silicon film is formed is mounted.
And a laser light source 320, and an optical system 325 that emits and condenses the laser light emitted from the laser light source 320 as a line beam L0 toward the substrate 30 mounted on the stage 310. In the example shown here, the irradiation area L of the line beam L0 extends in the X direction with a size of about 300 mm. To perform laser annealing on the entire surface of the substrate 30, the XY stage 310 moves in the Y direction. Will go.

Here, if the width of the irradiation area of the line beam is 500 μm, the laser beam is irradiated 200 times from one place of the semiconductor film 100 only by shifting the line beam at a pitch of 2.5 μm. It will be. If the line beam is shifted at a pitch of 25 μm,
When viewed from one position of the semiconductor film 100, the laser light is emitted 20 times,
That is, if the line beam is shifted at a pitch of 6 μm, the laser light is irradiated about 80 times from one point of the semiconductor film 100.

Next, as shown in FIG. 5A, a resist mask 551 is formed on the surface of the semiconductor film 100 by using a photolithography technique.

Next, the semiconductor film 100 is patterned via the resist mask 551 to form an island-shaped semiconductor film 10a (active layer) as shown in FIG. 5B.

Next, as shown in FIG.
Under the following temperature conditions, the semiconductor film 10 is formed by the CVD method or the like.
A gate insulating film 13 made of a silicon oxide film having a thickness of about 1000 angstroms is formed on the surface of a (gate insulating film forming step). The source gas at this time is, for example, T
A mixed gas of EOS and oxygen gas can be used.
As the gate insulating film 13, a silicon nitride film may be used.

Next, as shown in FIG. 5D, a tantalum film 910 for forming a gate electrode and the like is formed on the insulating substrate 3.
After the formation over the entire surface, a resist mask 552 is formed using a photolithography technique.

Next, the tantalum film 3 is patterned via the resist mask 552, and as shown in FIG.
A scanning line 91 (gate electrode) is formed.

Next, as shown in FIG.
Using the scanning line 91 (gate electrode) as a mask, about 0.1 × 1
Implanting low concentration impurity ions (phosphorus ions) at a dose of 0 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² ,
On the pixel TFT portion side, a low-concentration source region 161 and a low-concentration drain region 171 are formed in self-alignment with the gate electrode. Here, since it is located immediately below the gate electrode, the portion where the impurity ions are not introduced becomes the channel region 15 as it is as the semiconductor film.

Next, as shown in FIG.
In the portion T, a resist mask 55 wider than the gate electrode is used.
3 is formed, and high concentration impurity ions (phosphorus ions) are implanted at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² to form high concentration source and drain regions 162 and 172. Form. Thus, FIG.
As shown in (C), a source region 16 having a low-concentration source region 161 and a high-concentration source region 162 is formed, and a drain region 17 having a low-concentration drain region 171 and a high-concentration drain region 172 is formed.

Instead of these impurity introduction steps, a high-concentration impurity (phosphorus ion) is implanted in a state where a resist mask 553 wider than the gate electrode is formed without implanting a low-concentration impurity. A region and a drain region may be formed. It is needless to say that a high-concentration impurity (phosphorus ion) may be implanted on the gate electrode to form a source region and a drain region having a self-aligned structure.

Although not shown, the pixel portion and the N-channel TFT portion are covered and protected with a resist in order to form a P-channel TFT portion of the peripheral driving circuit, and about 0. By implanting boron ions at a dose of 1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² , P-channel source / drain regions are formed in a self-aligned manner. Note that, as in the case of forming the N-channel TFT portion, about 0.1 ×
After introducing a low-concentration impurity (boron ion) at a dose of 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² to form a low-concentration region in the polysilicon film, a mask wider than the gate electrode is formed. Forming high concentrations of impurities (boron ions)
From about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ²
To form a source region and a drain region having an LDD structure. Instead of implanting low-concentration impurities, high-concentration impurities (phosphorous ions) may be implanted in a state where a mask wider than the gate electrode is formed, to form a source region and a drain region having an offset structure. By these ion implantation steps, it is possible to make a CMOS and the peripheral drive circuit can be built in the same substrate.

Next, as shown in FIG.
A silicon oxide film or N
SG film (silicate glass film containing neither boron nor phosphorus)
After forming the first interlayer insulating film 18 made of a material having a thickness of about 3000 Å to 15,000 Å, a contact hole and a cutting hole are formed in the first interlayer insulating film 18 by using a photolithography technique. Is formed.

Next, the first through the resist mask 554
6E, the source region 1 of the first interlayer insulating film 18 is etched as shown in FIG.
Contact holes are formed in portions corresponding to 62 and the drain region 172, respectively.

Next, as shown in FIG. 7A, an aluminum film 900 for forming a source electrode or the like is formed on the surface side of the first interlayer insulating film 18 by a sputtering method or the like, and then photolithography is performed. A resist mask 555 is formed using a technique.

Next, the aluminum film 900 is etched through the resist mask 555, and as shown in FIG. 7B, the source electrode made of the aluminum film electrically connected to the source region 162 through the contact hole. (Part of the data line 90) and the drain electrode 1 electrically connected to the drain region 172 via a contact hole.
4 is formed.

Next, as shown in FIG. 7C, an interlayer insulating film 191 formed by firing a coating film of perhydropolysilazane or a composition containing the same is formed on the surface side of the source electrode 90 and the drain electrode 14. . Further, an upper interlayer insulating film 192 made of a silicon oxide film having a thickness of about 500 Å to about 15,000 Å is formed on the surface of the interlayer insulating film 191 by a CVD method using TEOS under a temperature condition of about 400 ° C., for example. Form.
These interlayer insulating films 191 and 192 form a second interlayer insulating film 19. Here, perhydropolysilazane is a kind of inorganic polysilazane, and is a coating type coating material that is converted into a silicon oxide film by firing in the air. For example, polysilazane manufactured by Tonen Corp. is an inorganic polymer having-(SiH2 NH)-as a unit and is soluble in an organic solvent such as xylene.
Therefore, a solution of the inorganic polymer in an organic solvent (for example,
20% xylene solution) as a coating solution by a spin coating method (for example, 2000 rpm, 20 seconds), followed by baking in air at 450 ° C., reacting with moisture and oxygen, and forming a silicon film by a CVD method. A dense amorphous silicon oxide film equal to or more than an oxide film can be obtained. Therefore, the interlayer insulating film 191 formed by this method is used.
(Silicon oxide film) has the same reliability as the interlayer insulating film formed by the CVD method,
It flattens irregularities caused by the above.

Next, as shown in FIG. 7C, a resist mask 556 for forming contact holes in the insulating films 18 and 19 is formed by using a photolithography technique.

Next, the second resist mask 556 is used.
The interlayer insulating film 19 is etched to form a contact hole at a portion corresponding to the drain electrode 14 as shown in FIG.

Next, as shown in FIG. 8A, an ITO film 80 having a thickness of about 400 angstroms to about 2000 angstroms is formed on the surface side of the second interlayer insulating film 19 by a sputtering method or the like. A resist mask 557 for patterning the ITO film 80 is formed by using a photolithography technique.

Next, through the resist mask 557, the IT
The O film 80 is etched to form the pixel electrode 8 electrically connected to the drain electrode 14 as shown in FIG.

Next, as shown in FIG. 8C, a surface protection film 45 made of a silicon oxide film or an organic film is formed on the surface of the pixel electrode 8.

Next, as shown in FIG. 8D, a polyimide film (alignment film 46) is formed on the surface of the surface protection film 45. To this end, a polyimide varnish obtained by dissolving 5 to 10% by weight of polyimide or polyamic acid in a solvent such as butyl cellosolve or n-methylpyrrolidone is subjected to flexographic printing, followed by heating and curing (firing). Then, the substrate on which the polyimide film is formed is rubbed in a certain direction with a puff cloth made of rayon-based fibers, and the polyimide molecules are arranged in a certain direction near the surface. As a result, the liquid crystal molecules are arranged in a certain direction by the interaction between the liquid crystal molecules and the polyimide molecules that are filled later.

[Summary of the Present Invention] In such a method of manufacturing the TFT 10, after the film forming step shown in FIG. 3B is performed, a non-process is performed until the laser annealing step shown in FIG. 3C is performed. When a thick oxide film is formed on the surface of the crystalline semiconductor film 100, the gate withstand voltage of the TFT 10 is reduced unless a very thick gate insulating film 13 is formed.

Therefore, in this embodiment, the surface state of the amorphous semiconductor film 100 at the time of performing the laser annealing step is optimized based on the findings shown in FIGS. Large irregularities are prevented from being formed on the surface of the conductive semiconductor film.

FIG. 9 is a graph showing the relationship between the thickness of the oxide film on the surface of the amorphous semiconductor film before laser annealing and the size of the irregularities on the surface of the polycrystalline semiconductor film after laser annealing. . In this figure, the horizontal axis represents the thickness of the oxide film on the surface of the amorphous semiconductor film before laser annealing (in Angstroms), and the vertical axis represents the 10 μm square of the polycrystalline semiconductor film after laser annealing. (In the specification of the present application, simply referred to as unevenness / unit angstrom). FIG. 9 shows the results obtained under the two conditions of the maximum and minimum slopes of the graph among the measurement results obtained by changing the energy density conditions during laser annealing. As is apparent from this figure, when the thickness of the oxide film on the surface of the amorphous semiconductor film before laser annealing is within 100 Å or less, the surface of the amorphous semiconductor film is not The smaller the thickness of the formed oxide film, the smaller the unevenness can be suppressed on the surface of the polycrystalline semiconductor film after laser annealing. Conversely, when the thickness of the oxide film increases by 1 Å in the range of 10 Å to 80 Å, the unevenness of the surface of the semiconductor film increases by about 10 Å to 15 Å.

FIG. 10 is a graph showing the relationship between the surface roughness of the polycrystalline semiconductor film and the gate breakdown voltage. In this figure, the horizontal axis represents 10 μm of the surface of the polycrystalline semiconductor film.
Maximum height difference within a corner (in the specification of the present application, this is simply referred to as unevenness.
The vertical axis represents the amount of change in the gate applied voltage when the gate leakage current shows a specified value (takes a value from a height difference to 0, which is taken as 100%), and is a polycrystalline semiconductor. This corresponds to the rate of decrease in gate withstand voltage based on the gate withstand voltage when the unevenness of the film surface is 0. Here, since the gate insulating film is set at 1000 Å, the surface of the polycrystalline semiconductor film has irregularities of 200 Å, that is, １ ／ or less of the thickness of the gate insulating film, as is apparent from this figure. If so, the reduction in gate breakdown voltage can be suppressed within 10%.

Here, in order to suppress irregularities on the surface of the polycrystalline semiconductor film to 200 angstrom or less, according to the results shown in FIG. 9, the oxide film on the surface of the amorphous semiconductor film before the laser annealing is formed. The thickness may be about 20 angstroms or less, that is, 1/50 or less of the thickness of the gate insulating film.

Therefore, in the present embodiment,
At the time of performing the laser annealing step, the amorphous semiconductor film 10
By controlling the thickness of the oxide film formed on the surface of No. 0 to 1/50 or less of the thickness of the gate insulating film and optimizing the laser beam irradiation conditions in the annealing step, Semiconductor film 100 is appropriately polycrystallized, and the polycrystalline semiconductor film 100 after the laser annealing process is performed.
By setting the size of the irregularities on the surface to 1/5 or less of the thickness of the gate insulating film, the reduction in gate withstand voltage is kept within 10%. Note that the “oxide film formed on the surface of the amorphous semiconductor film at the time of performing the laser annealing process” here means that the oxide film naturally occurs in the air during the transfer of the substrate or during the drying after washing. In addition to a grown natural oxide film, this also includes an oxide film formed artificially by oxygen plasma or the like to obtain a clean gate interface, or an oxide film formed by a CVD method.

[Embodiment 1] In this embodiment, of the method of manufacturing a TFT, the process of manufacturing a polycrystalline semiconductor film described with reference to FIG. 3 is improved as follows.

First, as shown in FIG. 3A, after preparing a substrate 30 made of glass or the like, the temperature is increased from about 150 ° C. to about 4 ° C.
Under a temperature condition of 50 ° C., as shown in FIG. 3B, an underlayer protective film 301 made of a silicon oxide film is formed on the entire surface of the substrate 30.
Is formed by a plasma CVD method.

Next, when the substrate temperature is from about 150 ° C. to about 450 ° C.
Under the temperature condition of ° C., the film thickness is 300 Å to 1500 Å, for example, 10 Å on the entire surface of the substrate 30.
The semiconductor film 100 made of an amorphous silicon film having a thickness of 00 Å is formed by plasma CVD or low pressure CVD.
It is formed by a method.

Next, scrub cleaning is performed with pure water and a nylon brush to remove dust adhering during film formation / transportation, and then NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 25
0 for 5 minutes and rinsed with pure water for 10 minutes.

Next, HF (hydrofluoric acid): H ₂ O =
Wet etching is performed for 30 seconds to 1 minute with a 1:50 etchant to completely remove the silicon oxide film formed on the surface of the amorphous semiconductor film 100 (etching step).

Thereafter, rinsing is performed for 10 minutes in a pure water tank to which ultrasonic vibration is applied. Finally, drain the water by spin drying.

Then, promptly, for example, within one hour, using a laser annealing apparatus, as shown in FIG.
An excimer laser beam of 308 nm is, for example, 400
Irradiation is performed at an energy density of mJ / cm ² . The beam shape is set to 200 mm × 400 μm by an appropriate optical system, and the entire surface of the substrate is irradiated while being shifted by a predetermined pitch in the minor axis direction (laser annealing step). The laser annealing performed here is performed in a non-oxidizing atmosphere such as a vacuum or an inert gas. However, if for some reason, for example, a trouble in the transport system, the elapsed time from the etching step using an etching solution of HF: H ₂ O = 1: 50 to entering the laser annealing apparatus becomes 2 hours, H
Wet etching is performed for 30 seconds to 1 minute with an etching solution of F: H ₂ O = 1: 50.

That is, the exposure time during which the semiconductor film is exposed to an oxygen-containing atmosphere after performing the etching process and before performing the laser annealing process is defined as T time, and the thickness of the gate insulating film is defined as t angstroms. Then, the exposure time and the thickness of the gate insulating film maintain a relationship satisfying the following equation: T ≦ t / 500. That is, on the surface of the semiconductor film after the oxide film is removed by the etching process, the growth rate of the silicon oxide film is generally up to about 10 angstroms / hour up to 50 angstroms in the air. Assuming that the thickness is t (angstrom), the allowable thickness of the surface oxide film is t / 50.
(Angstrom) or less, the exposure time in the air after removing the oxide film in the etching step is t / 5.
0/10 = t / 500 (time) is the limit. For example, if the thickness of the gate insulating film is 1000 angstroms, the time during which exposure in the air is allowable is 2 hours. Therefore, it is preferable to perform the laser annealing step within one hour after the etching step.

FIG. 11 shows the laser light irradiation conditions (the number of laser light irradiations when viewed from one location on the semiconductor film surface) in the laser annealing step, and the polycrystalline property of the amorphous semiconductor film. Of the semiconductor surface after phase transition to the semiconductor film of FIG.

FIG. 11 shows the laser light irradiation conditions when the oxide film does not exist on the surface of the semiconductor film 100 at the time of performing the laser annealing step (the number of laser light irradiations when viewed from one position on the semiconductor film surface). The solid line L11 indicates the relationship between the thickness of the semiconductor film 100 after the phase transition to the polycrystalline semiconductor film 100 and the thickness of the oxide film (gate insulating layer) on the surface of the semiconductor film 100 at the time of performing the laser annealing process. In the case where an oxide film having a thickness of 1/50 or more times the thickness of the film 13 is present, the irradiation conditions of the laser light (the number of laser light irradiations when viewed from one position on the surface of the semiconductor film) are large. The solid line L12 shows the relationship with the size of the irregularities on the semiconductor surface after the phase transition to the crystalline semiconductor film.

As is apparent from this figure, a thick oxide film (an oxide film having a thickness of 1/50 or more times the thickness of the gate insulating film) exists on the surface of the semiconductor film 100 at the time of performing the laser annealing step. In such a case, as the number of laser light irradiation increases, the roughness of the surface of the semiconductor film 100 after the phase transition to polycrystal tends to increase.

On the other hand, when the oxide film does not exist on the surface of the semiconductor film 100 at the time of performing the laser annealing step, the surface of the semiconductor film 100 after the phase transition to polycrystal increases as the number of times of the laser light irradiation increases. When the number of laser light irradiations is about 20 times, the surface roughness of the semiconductor film 100 after the phase transition to polycrystal becomes 200 Å or less. However, if the number of irradiations of laser light exceeds about 60 to about 80 times, even if the number of irradiations is further increased,
The unevenness does not become smaller any more and becomes substantially constant.

Therefore, in this embodiment, in the annealing step,
Laser light irradiation is performed 20 times or more at one location on the surface of the semiconductor film 100. That is, the line beam is shifted at a pitch of 25 μm or less. Further, by irradiating the laser light more than 80 times at one place on the surface of the semiconductor film 100, the unevenness of the surface of the semiconductor film after the phase transition to the polycrystal is surely reduced to 20.
It can be suppressed to 0 angstrom or less. That is, the line beam is shifted at a pitch of 6 μm or less.

FIG. 12 shows the irradiation conditions of the laser beam in the laser annealing step when the oxide film does not exist on the surface of the semiconductor film 100 at the time of performing the laser annealing step (when viewed from one point on the semiconductor film surface). The relationship between the number of laser light irradiations) and the degree of crystallinity of the polycrystalline semiconductor film 100 obtained by phase transition of the amorphous semiconductor film 100 is shown. Here, the degree of crystallinity of the polycrystalline semiconductor film 100 in which the amorphous semiconductor film 100 has undergone phase transition can be measured as the magnitude of the ON current of the TFT formed from the semiconductor film 100. It can be said that the crystallinity of the semiconductor film 100 is high and preferable.

As shown in FIG. 12, when the irradiation conditions of the laser beam (the number of times of irradiation of the laser beam as viewed from one position on the surface of the semiconductor film) are increased, the on-current of the TFT is increased. The peak is from 110 to about 120 times, and when the number of times of laser light irradiation is further increased, the on-current of the TFT tends to decrease. In addition, when the number of laser light irradiations exceeds 200, the on-current is reduced as compared with the case where laser annealing is not performed. Therefore, in this embodiment, the number of laser light irradiations when viewed from one location on the surface of the semiconductor film 100 is limited to about 200 times or less. That is, the line beam is shifted at a pitch of 2.5 μm or more.

Thereafter, after performing the patterning process shown in FIGS. 5A and 5B, in the gate insulating film forming process shown in FIG. 5C, the gate insulating film having a thickness of 1000 Å is formed by the plasma CVD method. The film 13 is formed (gate insulating film forming step).

As described above, in the method of manufacturing the TFT of this embodiment, the step of removing the oxide film on the surface of the semiconductor film before the annealing step is performed, so that the TFT is present on the surface of the amorphous semiconductor film. The thickness of the oxide film is one of the thickness of the gate insulating film.
/ 50 or less, and in the annealing step, conditions are set such that the laser light is irradiated about 20 times to about 200 times, preferably about 80 times to about 200 times, at one location on the surface of the semiconductor film. Therefore, when the amorphous semiconductor film is polycrystallized by laser annealing, no large irregularities exceeding 200 angstroms are formed on the surface of the obtained polycrystalline semiconductor film. 1
Even if the threshold voltage of the TFT is reduced by reducing the thickness to 2,000 Å, the gate breakdown voltage does not decrease. Therefore, according to this embodiment, the switching voltage is low, and
A highly reliable TFT can be manufactured. Since the number of irradiations is limited to 200 or less so as not to excessively anneal, a TFT having a large on-current can be manufactured.

[Embodiment 2] In this embodiment, since the basic process is the same as that of Embodiment 1, the description is omitted, but the laser annealing step from the etching step is performed in a short time. For this purpose, a semiconductor film processing apparatus shown in FIG. 13 is used.

FIG. 13 shows a semiconductor film processing apparatus 60 according to this embodiment.
0 is a schematic configuration diagram. As shown in FIG. 13, a semiconductor film processing apparatus 600 according to the present embodiment includes a substrate in which an amorphous semiconductor film is formed and a substrate in which the semiconductor film is polycrystallized by laser annealing of the amorphous semiconductor film. Cassette type loader / unloader unit 6 for unloading
And a shower type wet etching apparatus for etching the surface of an amorphous semiconductor film on a substrate with an etching solution containing hydrogen fluoride (HF: H2 O = 1: 50). 620 and a cleaning apparatus 630 for performing shower cleaning with water (cleaning liquid) on the surface of the amorphous semiconductor film on the substrate after the wet etching.
A drying device 640 for drying and removing water adhering to the surface of the amorphous semiconductor film on the substrate; and a laser annealing device 650 for performing laser annealing on the amorphous semiconductor film on the dried substrate. Are configured. The laser annealing device 650 includes a vacuum load lock 651, a laser annealing chamber 652, a laser optical system 325, a laser light source 320, and the like. In the semiconductor film processing apparatus 600, the substrate carried into the loader / unloader section 610 is transferred to the wet etching apparatus 620, the cleaning apparatus 630, the drying apparatus 640, and the laser annealing apparatus 650, and then is loaded into the loader / unloader section. 610
The transport mechanism 660 for returning to the state of FIG. Here, the transport mechanism 660 includes a first transport system 661 that transports the substrate loaded into the loader / unloader unit 610 to the wet etching device 620, and a conveyor system that transports the substrate from the wet etching device 620 to the cleaning device 630. Second
Transport system 662 and the washing device 630 to the drying device 640
And a third transfer system 663 for transferring the substrate to the third transfer system. It should be noted that the drying device 640 to the laser annealing device 6
Of substrate to laser 50 and laser annealing device 650
The first transfer system 661 transfers the substrates from the loader to the loader / unloader unit 610.

In this semiconductor film processing apparatus 600, when the substrate on which the amorphous semiconductor film is formed is loaded into the loader / unloader section 610 in a cassette state, the first transport of the transport mechanism 660 is performed. The system 661 takes out the substrate from the cassette and carries it into the wet etching apparatus 620. In the wet etching apparatus 620, the substrate is transported by the second transport system 662 of the conveyor type, the etchant is applied to the substrate as a shower, and the oxide film on the surface of the amorphous semiconductor film formed on the substrate is completely removed. Removed. Subsequently, the substrate is transferred to a second conveyor system 662 of a conveyor type.
Cleaning device 630 using pure water shower for rinsing
The etching solution is removed by a pure water shower to which ultrasonic vibration is applied.

Next, the third transport system 66 of the transport mechanism 660
3 puts the substrate into a spin-type drying device 640. Here, the substrate is rotated at a high speed, and moisture on the substrate is removed by centrifugal force. Next, the first transport system 6 of the transport mechanism 660
Numeral 61 denotes a vacuum load lock 6 for drying the substrate from the drying device 640.
After the substrate is evacuated, the substrate is carried into the chamber 652 of the laser annealing apparatus 650. Here, the inside of the chamber 652 for laser annealing is set in a non-oxidizing atmosphere using a vacuum or an inert gas, and in this non-oxidizing atmosphere, the amorphous semiconductor film on the substrate becomes a laser. Receive annealing. as a result,
The amorphous semiconductor film over the substrate becomes a polycrystalline semiconductor film. Thereafter, the first transport system 661 of the transport mechanism 660
Moves the substrate from the inside of the chamber 652 for laser annealing to the vacuum load lock 651. Then, the transport mechanism 66
The first transport system 661 returns the substrate to the cassette of the loader / unloader unit 610. Hereinafter, the same processing is performed on all the substrates.

As described above, the semiconductor film processing apparatus 6 of the present embodiment
In the case of 00, since the etching device 620 and the laser annealing device 650 are integrated, the substrate can be transferred to the laser annealing step in a short time after etching the amorphous semiconductor film. Therefore, no thick oxide film is formed on the surface of the amorphous semiconductor film after the wet etching. Therefore, at the time of performing the laser annealing step, the thickness of the oxide film formed on the surface of the amorphous semiconductor film can be controlled to 1/50 or less of the thickness of the gate insulating film. The size of the irregularities on the surface of the polycrystalline semiconductor film after the etching is reduced to 1/5 or less of the thickness of the gate insulating film, so that the reduction in gate withstand voltage can be kept within 10%.

[Embodiment 3] In this embodiment, the basic process is the same as that of Embodiment 2, and therefore detailed description thereof will be omitted. For the purpose, a semiconductor film processing apparatus shown in FIG. 14 is used. Further, the semiconductor film processing apparatus is configured to perform dry etching as an etching step.

In FIG. 14, a semiconductor film processing apparatus 700
A cassette-type loader / unloader unit for carrying in a substrate on which an amorphous semiconductor film is formed and carrying out a substrate in which a semiconductor film is polycrystallized by laser annealing of the amorphous semiconductor film 710 and a gas / RF supply unit 722 for etching the amorphous semiconductor film on the substrate using an etching gas containing fluorine.
And a laser annealing apparatus 750 that performs laser annealing on the amorphous semiconductor film on the substrate after the dry etching has been performed by the dry etching apparatus 720. Also,
The substrate loaded into the loader / unloader section 710 is loaded into the semiconductor film processing apparatus 700 by the dry etching apparatus 72.
0, and a transport mechanism 760 that returns the loader / unloader unit 710 after being transported to the laser annealing device 750,
And a housing 790 for holding the substrate transfer path in a non-oxidizing atmosphere. As described above, in this semiconductor film processing apparatus 700, since the substrate is transferred in a vacuum,
The laser annealing device 750 includes a laser annealing chamber 752, a laser optical system 325, a laser light source 320, and the like, and has no vacuum load lock.

In this semiconductor film processing apparatus 700, the substrate which has been subjected to formation of an amorphous semiconductor film, scrub cleaning, rinsing for about one minute by a pure water shower to which ultrasonic vibration is applied, and spin drying is placed in a cassette. Loader
When transported into the unloader unit 710, the transport mechanism 760
Takes out the substrate from the cassette and carries it into the dry etching apparatus 720. This dry etching apparatus 720
Then, etching is performed with CHF3 gas for 30 seconds.
The oxide film is removed from the surface of the amorphous semiconductor film formed on the substrate. Next, the transport mechanism 760 carries the substrate into the chamber of the laser annealing device 750. Here, the inside of the chamber for laser annealing is set in a non-oxidizing atmosphere using a vacuum or an inert gas, and the amorphous semiconductor film on the substrate is subjected to laser annealing in this non-oxidizing atmosphere. Receive. As a result, the amorphous semiconductor film on the substrate becomes a polycrystalline semiconductor film. After a while
The transport mechanism 760 removes the substrate from the laser annealing chamber and returns the substrate to the cassette of the loader / unloader unit 710. Hereinafter, the same processing is performed on all the substrates. During this time, the inside of the housing 790 is kept in a vacuum.

According to such a semiconductor film processing apparatus 700, the etching apparatus 720 and the laser annealing apparatus 750
Are integrated, and the amorphous semiconductor film on the substrate surface is not exposed to an oxidizing atmosphere when the substrate is transferred between these devices. No oxide film is formed on the substrate. Therefore, the thickness of the oxide film formed on the surface of the amorphous semiconductor film at the time of performing the laser annealing step is reduced to 1 / th of the thickness of the gate insulating film.
Since it can be controlled to 50 or less, the size of the irregularities on the surface of the polycrystalline semiconductor film after performing the laser annealing step is set to 1/5 or less of the thickness of the gate insulating film, and the reduction of the gate breakdown voltage is reduced to within 10% Can fit.

[Embodiment 4] In this embodiment, FIG.
After forming the amorphous semiconductor film on the surface of the substrate 30 as shown in FIG. 3, the surface of the amorphous semiconductor film is not oxidized until the annealing step is performed as shown in FIG. Keep in oxidizing atmosphere and do not expose to oxidizing atmosphere. Therefore,
Since no oxide film is formed on the surface of the amorphous semiconductor film at the time of performing the laser annealing step, almost no irregularities are formed on the surface of the polycrystalline semiconductor film after performing the laser annealing step. Therefore, in a TFT using this semiconductor film as an active layer, a decrease in gate breakdown voltage does not occur.

In order to carry out such a method, in this embodiment, a semiconductor film processing apparatus 800 shown in FIG. 15 is used.
In the semiconductor film processing apparatus 800, a loader / unloader unit 810 for loading and unloading a substrate.
And gas for forming an amorphous semiconductor film on a substrate
A film forming apparatus 870 (CVD film forming apparatus) including an RF supply unit 872 and a laser annealing apparatus 850 that performs laser annealing on an amorphous semiconductor film on a substrate formed by the film forming apparatus 870 are configured. ing. Further, in the semiconductor film processing apparatus 800, after the substrate carried into the loader / unloader unit 810 is transported to the film forming device 870 and the laser annealing device 850, the substrate is loaded.
And a housing 890 for holding the substrate transfer path in a non-oxidizing atmosphere.

The semiconductor film processing apparatus 80 thus configured
0, when the substrate is loaded into the loader / unloader unit 810 in a state of being loaded in the cassette, the transport mechanism 860
Takes out a substrate from a cassette and performs a single-wafer type film forming apparatus 8
Carry in 70. In this film forming apparatus 870, a semiconductor film made of an amorphous silicon film having a thickness of 1000 Å is formed on a whole surface of a substrate by plasma CVD or low pressure CVD.
It is formed by a method. Next, the transport mechanism 860 carries the substrate into the chamber of the laser annealing device 850. Here, the inside of the chamber 852 for laser annealing is set to a non-oxidizing atmosphere using a vacuum or an inert gas. In this non-oxidizing atmosphere, the amorphous semiconductor film on the substrate is subjected to laser irradiation. Receive annealing. As a result, the amorphous semiconductor film on the substrate becomes a polycrystalline semiconductor film. Thereafter, the transport mechanism 860 removes the substrate from the laser annealing chamber and removes the substrate from the loader / unloader unit 81.
Return to cassette 0. Hereinafter, the same processing is performed on all the substrates. During this time, the inside of the housing 890 is kept at a vacuum.

As described above, the semiconductor film processing apparatus 80 of the present embodiment
In the case of 0, the film forming apparatus 870 and the laser annealing apparatus 850 are integrated, and the substrate is handled in a vacuum when the substrate is transferred between these apparatuses. Therefore, since the amorphous semiconductor film on the substrate surface is not exposed to an oxidizing atmosphere, no oxide film is formed on the surface of the amorphous semiconductor film. Therefore, since no oxide film is formed on the surface of the amorphous semiconductor film at the time of performing the laser annealing step, almost no irregularities are formed on the surface of the polycrystalline semiconductor film after performing the laser annealing step. Therefore, in a TFT using this semiconductor film as an active layer, a decrease in gate breakdown voltage does not occur.

[Structure of Liquid Crystal Panel] As an example of using a TFT formed by such a method, an example in which this TFT is formed on an active matrix substrate for pixel switching and for a driving circuit will be described.

FIGS. 16 and 17 are a plan view of the electro-optical device used in the liquid crystal display device according to the present embodiment, as viewed from the counter substrate side, and an electro-optical device cut along the line HH 'in FIG. It is sectional drawing of an apparatus.

In these figures, an electro-optical device 1 used for a liquid crystal display device has an active matrix substrate 11 on which pixel electrodes 8 are formed in a matrix and a counter electrode 31.
Is formed between the opposing substrate 12 and the substrates,
And a liquid crystal 39 sandwiched therebetween. The active matrix substrate 11 and the opposing substrate 12 are bonded to each other with a predetermined gap therebetween by a sealing material 52 containing a gap material formed along the outer peripheral edge of the opposing substrate 12. A liquid crystal enclosing area 40 is defined between the active matrix substrate 11 and the opposing substrate 12 by a sealing material 52.
9 is enclosed. A spacer 37 may be interposed between the active matrix substrate 11 and the counter substrate 12 in the liquid crystal sealing region 40. However, when the electro-optical device 1 is used as a light valve of a projection display device, the arrangement of the spacer 37 is generally omitted to prevent the image of the spacer 37 from being projected. As the sealing material 52, an epoxy resin, various ultraviolet curable resins, or the like can be used. The gap material to be mixed with the sealing material 52 is about 2 μm
Inorganic or organic fibers or spheres of about 10 μm are used.

The opposing substrate 12 is smaller than the active matrix substrate 11, and the peripheral portion of the active matrix substrate 11 is bonded so as to protrude from the outer peripheral edge of the opposing substrate 12. Therefore, the active matrix substrate 11
Drive circuits (scanning line drive circuit 70 and data line drive circuit 6)
0) and the input / output terminals 45 are exposed from the counter substrate 12. Here, since the sealing material 52 is partially interrupted, the liquid crystal injection port 241 is formed by the interrupted portion. For this reason, after the opposing substrate 12 and the active matrix substrate 11 are bonded to each other, if the inner region of the sealing material 52 is set in a reduced pressure state, the liquid crystal 39 can be injected under reduced pressure from the liquid crystal injection port 241 and after the liquid crystal 39 is sealed, The liquid crystal injection port 241 may be closed with the sealant 242. The opposing substrate 12 is also provided with a light shielding film 54 for cutting off the screen display area 7 inside the sealing material 52. In each of the corners of the opposing substrate 12, a vertical conducting material 56 for establishing electric conduction between the active matrix substrate 30 and the opposing substrate 12 is formed.

Here, if the delay of the scanning signal supplied to the scanning line does not matter, it goes without saying that the scanning line driving circuit 70 may be provided on only one side. Further, the data line driving circuits 60 may be arranged on both sides along the side of the screen display area 7. For example, an odd-numbered data line supplies an image signal from a data line driving circuit disposed along one side of the screen display area 7, and an even-numbered data line extends along an opposite side of the screen display area 7. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines are driven in a comb-like manner, the data line driving circuit 6
Since the formation area of 0 can be expanded, a complicated circuit can be formed. On the side of the side of the active matrix substrate 11 facing the data line drive circuit 60, a precharge circuit or an inspection circuit may be provided by using a portion under the light shielding film 54 or the like. In addition,
Instead of forming the data line driving circuit 60 and the scanning line driving circuit 70 on the active matrix substrate 11, for example, a TAB (tape automated, bonding) substrate on which a driving LSI is mounted is mounted on the peripheral portion of the active matrix substrate 11. May be electrically and mechanically connected to the terminal group formed through the anisotropic conductive film. The type of liquid crystal 39 to be used, that is, TN (twisted nematic) mode, STN (super TN) is provided on the light incident side surface or light emitting side of the opposing substrate 12 and the active matrix substrate 11.
Mode, etc., normally white mode /
Depending on the normally black mode, polarizing film,
A retardation film, a polarizing plate and the like are arranged in a predetermined direction.

When the electro-optical device 1 of this embodiment is configured as a transmission type, it is used, for example, in a projection type liquid crystal display device (liquid crystal projector). In this case, the three electro-optical devices 1 are used as light valves for RGB, and each of the electro-optical devices 1 receives light of each color separated through a dichroic mirror for RGB color separation as projection light. Respectively. Therefore, no color filter is formed in the electro-optical device 1 of the present embodiment. However, a color liquid crystal display device such as a color liquid crystal television, etc., in addition to the projection type liquid crystal display, is formed by forming an RGB color filter together with a protective film in a region facing each pixel electrode 8 on the counter substrate 12. Can be. Furthermore, a dichroic filter that creates RGB colors by utilizing the interference effect of light may be formed by stacking a number of interference layers having different refractive indexes on the counter substrate 12. According to the counter substrate with the dichroic filter, a brighter color display can be performed.

(Configuration of Active Matrix Substrate) FIG.
FIG. 8 is a block diagram schematically showing the configuration of the active matrix substrate 11. As shown in FIG. 18, a pixel switching TFT 10 connected to a data line 90 and a scanning line 91 is provided on an active matrix substrate 11 for a liquid crystal display device.
There is a liquid crystal cell 94 to which an image signal is input from. For the data line 90, a data line drive circuit 60 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is formed. For the scanning line 91, a scanning line driving circuit 70 including a shift register 88 and a level shifter 89 is formed.

In the pixel region, a storage capacitor 40 (capacitance element) is formed between the storage capacitor 4 and the capacitor line 92.
0 has the function of improving the charge retention characteristics of the liquid crystal cell 94. Incidentally, the storage capacitor 40 may be formed between the scanning line 91 and the preceding stage.

(Structure of Opposing Substrate) FIG. 19 is a sectional view of an end of the electro-optical device 1. In FIG. 19, a counter substrate 12 is a lens array substrate in which a plurality of microlenses 430 (small convex lenses) raised toward each of the pixel electrodes 8 are formed in a matrix corresponding to the pixel electrodes 8 of the active matrix substrate 30. 43 and a transparent thin glass 4 bonded to the lens array substrate 43 with an adhesive 48 so as to cover the microlenses 430.
9. The counter electrode 31 is formed on the surface of the thin glass 49. Of the surface of the counter electrode 31,
The light shielding film 6 is formed in a region corresponding to the boundary region of the micro lens 430. On the surface of the thin glass 49, a surface protection film 44 made of a silicon oxide film or an organic film is formed on the surface of the counter electrode 31 and the light shielding film 6, and an alignment film 47 made of a polyimide film is formed on the surface of the surface protection film 44. Are formed. Like the alignment film 46 of the active matrix substrate 11, the alignment film 47 is also a film that has been subjected to a rubbing process of rubbing in a certain direction with a puff cloth made of rayon fiber.

In the electro-optical device 1 using the opposing substrate 12 having such a configuration, of the light incident from the opposing substrate 12, the light irradiated to the channel forming region of the TFT 10 is blocked by the light shielding film 6. At the same time, obliquely incident light and the like are collected by the microlenses 430 toward the pixel electrodes 8. Therefore, even if the width of the light shielding film 6 formed on the side of the opposing substrate 12 is narrow,
The light can be prevented from entering the channel forming region of the TFT 10 by the microlens 430 even if the light shielding film 6 is not provided on the side of. Therefore, deterioration of the transistor characteristics of the TFT 10 can be prevented, so that reliability can be improved. Further, the width of the light shielding film 6 formed on the side of the opposing substrate 12 can be reduced, or
Since the light shielding film 6 may be omitted from the side 2, it is possible to prevent the light amount contributing to display from being reduced by the light shielding film 6. Therefore, the contrast and brightness of the liquid crystal display device can be significantly improved.

In the opposing substrate 12 having such a configuration, a sealing material 52 containing a gap material is applied to a peripheral region 120 of the formation region of the microlens 430 or a region slightly inside the outer peripheral edge of the active matrix substrate 11. By 52, the opposing substrate 12 and the active matrix substrate 11 are bonded.

[Application of Electro-Optical Apparatus to Electronic Apparatus] Next, an example of an electronic apparatus including the electro-optical apparatus 1 will be described with reference to FIG.
This will be described with reference to FIG.

First, FIG. 20 is a block diagram showing a configuration of an electronic apparatus having an electro-optical device configured similarly to the electro-optical device 1 according to each of the above embodiments.

In FIG. 20, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, electro-optical device 1006, clock generation circuit 10
08, and a power supply circuit 1010. The display information output source 1000 is a ROM (Read Only Memory).
y), a memory such as a random access memory (RAM), an optical disk, and a tuning circuit for tuning and outputting an image signal of a television signal.
Based on the clock from 08, the image signal of a predetermined format is processed and output to the display information processing circuit 1002. The display information output circuit 1002 includes, for example, an amplifier
It includes well-known various processing circuits such as a polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, or a clamp circuit, and sequentially generates a digital signal from input display information based on a clock signal, and generates a clock. The signal is output to the drive circuit 1004 together with the signal CLK. The drive circuit 1004 drives the electro-optical device 1006. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that, like the electro-optical device 1 described above, the active matrix substrate 11 that forms the electro-optical device 1006
The drive circuit 1004 may be formed on the active matrix substrate 11, and in addition, the display information processing circuit 1002 may be formed on the active matrix substrate 11.

As the electronic apparatus having such a configuration, when the electro-optical device 1 is configured as a transmission type, a projection type liquid crystal display device (liquid crystal projector) described later with reference to FIG. A computer (PC) and an engineering workstation (EWS), a pager, or a mobile phone, word processor, television, viewfinder or monitor direct view video tape recorder, electronic organizer, electronic desk calculator, car navigation device, POS terminal, A touch panel and the like can be given.

The projection type liquid crystal display device 1100 shown in FIG.
Prepares three liquid crystal modules each including the electro-optical device 1 in which the drive circuit 1004 is mounted on the active matrix substrate 11, and respectively prepares the light valves 100 for RGB.
The projector is configured as R, 100G, and 100B. In this liquid crystal projector 1100, when light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three mirrors 11
06 and two dichroic mirrors 1108 separate light components R, G, and B corresponding to the three primary colors R, G, and B (light separating means), and the corresponding light valve 100.
R, 100G, 100B (electro-optical device 100 / liquid crystal light valve). At this time, the light component B is
Since the optical path is long, the input lens 112 is used to prevent light loss.
2, relay lens 1123, and exit lens 1124
And is guided through a relay lens system 1121 composed of Light components R, G, and B corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B, respectively.
Are incident on a dichroic prism 1112 (light combining means) from three directions and are combined again, after which the projection lens 1
The image is projected as a color image on a screen 1120 or the like via the line 114.

[0104]

As described above, the TF according to the present invention
In the method of manufacturing T, the thickness of the oxide film formed on the surface of the amorphous semiconductor film at the time of performing the laser annealing step is set to 1/50 or less of the thickness of the gate insulating film, and By optimizing the number of irradiations, the size of the irregularities on the surface of the polycrystalline semiconductor film after the laser annealing step is reduced to 1/5 or less of the thickness of the gate insulating film. Therefore, even when a polycrystalline semiconductor film obtained by subjecting an amorphous semiconductor film to laser annealing is used as an active layer, a decrease in gate breakdown voltage can be reduced by 10 even without forming a thick gate insulating film.
%, For example, it is possible to manufacture a TFT having favorable transistor characteristics in terms of gate withstand voltage and threshold voltage.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a pixel formed on an active matrix substrate.

FIG. 2 is a cross-sectional view taken along line AA 'of FIG.

FIGS. 3A to 3C are process cross-sectional views illustrating a method of manufacturing the TFT shown in FIG.

FIG. 4 is a schematic configuration diagram of a laser annealing apparatus used in a laser annealing step performed in FIG.

FIGS. 5A to 5E are cross-sectional views showing the steps performed after the step shown in FIG. 3 in the method for manufacturing the TFT shown in FIG.

6 (A) to 6 (E) are cross-sectional views showing steps performed after the step shown in FIG. 5 in the method of manufacturing the TFT shown in FIG. 1.

FIGS. 7A to 7D are cross-sectional views showing respective steps performed after the step shown in FIG. 6 in the method of manufacturing the TFT shown in FIG.

FIGS. 8A to 8D are cross-sectional views showing the steps performed after the step shown in FIG. 7 in the method of manufacturing the TFT shown in FIG.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing the TFT shown in FIG. 1 in which the thickness of an oxide film on the surface of an amorphous semiconductor film before laser annealing and the size of irregularities on the surface of a polycrystalline semiconductor film after laser annealing; 6 is a graph showing the relationship of.

FIG. 10 is a graph showing a relationship between irregularities on the surface of a polycrystalline semiconductor film and gate breakdown voltage in the method of manufacturing the TFT shown in FIG.

11A and 11B show laser light irradiation conditions (the number of laser light irradiations when viewed from one location on a semiconductor film surface) in a laser annealing step and a method for manufacturing a TFT shown in FIG. 4 is a graph showing a relationship between the phase of a semiconductor film and the size of irregularities on a semiconductor surface after a phase transition to a polycrystalline semiconductor film.

FIG. 12 is a laser annealing step in the case where an oxide film does not exist on the surface of the semiconductor film at the time of performing the laser annealing step and in the case where a thick oxide film exists on the surface of the semiconductor film in the method of manufacturing the TFT shown in FIG. Of the laser light irradiation conditions (the number of laser light irradiations as viewed from one location on the surface of the semiconductor film) and the magnitude of the ON current of the TFT formed from the polycrystalline semiconductor film obtained by this annealing step. It is a graph which shows a relationship.

FIG. 13 is a schematic configuration diagram of a semiconductor film processing apparatus used in a method of manufacturing a TFT according to the present invention.

FIG. 14 is a schematic configuration diagram of another semiconductor film processing apparatus used for the TFT manufacturing method according to the present invention.

FIG. 15 is a schematic configuration diagram of still another semiconductor film processing apparatus used in the TFT manufacturing method according to the present invention.

FIG. 16 is a plan view of an electro-optical device for an active matrix type liquid crystal display device to which the present invention is applied.

FIG. 17 is a sectional view taken along line HH ′ of FIG. 16;

18 is a block diagram of the active matrix substrate shown in FIG.

FIG. 19 is an enlarged sectional view showing an end of the electro-optical device shown in FIG.

20 is a block diagram illustrating a circuit configuration of an electronic apparatus illustrating an example of use of the electro-optical device illustrated in FIGS. 16 and 17. FIG.

21 is an overall configuration diagram of a projection type liquid crystal display device showing an example of use of the electro-optical device shown in FIGS. 16 and 17. FIG.

[Explanation of symbols]

 Reference Signs List 1 electro-optical device 8 pixel electrode 10 pixel switching TFT 11 active matrix substrate 12 counter substrate 13 gate insulating film 39 liquid crystal 43 lens array substrate 52 sealing material 90 data line 94 liquid crystal cell 100 semiconductor film 320 laser light source 325 laser optical system 600 , 700, 800 Semiconductor film processing apparatus 610, 710 820 Loader / unloader section 620 Wet etching apparatus 630 Cleaning apparatus 640 Drying apparatus 650, 750, 850 Laser annealing apparatus 651 Vacuum load lock 652, 752, 852 Laser annealing chamber 660, 760, 860 Transport mechanism 661 First transport system 662 Second transport system 663 Third transport system 720 Dry etching device 722, 872 Gas / RF supply unit 790, 890 870 Deposition equipment

Continued on the front page F-term (reference) 2H092 GA36 GA51 JA25 JA35 JB69 KA05 KA10 KA12 KB25 MA05 MA07 MA08 MA18 MA30 MA37 MA41 NA22 PA03 PA04 PA08 PA09 PA10 PA11 QA07 QA10 RA05 5F052 AA02 BA07 BB07 CA08 DA02 DB03 EA01 A15 JA10 FA10 AA08 AA12 BB01 BB02 BB04 CC02 DD02 DD13 DD24 DD25 EE04 EE27 FF02 FF03 FF23 FF29 FF30 GG02 GG13 GG24 GG25 GG26 GG45 GG47 HJ01 HJ04 HJ13 HL03 HL23 HM14 HM15 NN17 NN17 NN17 NN03 NN03 NN18 NN03 NN18 NN03 NN18 QQ30

Claims (12)

[Claims] A film forming step of forming an amorphous semiconductor film on a substrate; a laser annealing step of irradiating the amorphous semiconductor film with laser light to polycrystallize the semiconductor film; A gate insulating film forming step of forming a gate insulating film on the surface of the polycrystalline semiconductor film, wherein the laser annealing step is performed on the surface of the amorphous semiconductor film at the time of performing the laser annealing step. The thickness of the oxide film is not more than 1/50 of the thickness of the gate insulating film, and in the laser annealing step, the semiconductor film is irradiated with laser light at least 20 times per location on the surface of the semiconductor film. Manufacturing method of a thin film transistor. 2. The method according to claim 1, wherein in the laser annealing step, at least a part of
A method for manufacturing a thin film transistor, comprising irradiating a laser beam 80 times or more per location. 3. The method according to claim 1, wherein in the laser annealing step, at least a part of
A method for manufacturing a thin film transistor, wherein irradiation of a laser beam is performed 200 times or less per location. 4. The method according to claim 1, wherein
In the laser annealing step, a line beam is used as the laser beam, and the surface of the semiconductor film is irradiated with the laser beam while partially overlapping the irradiation region of the line beam in a direction orthogonal to the longitudinal direction of the line beam. A method for manufacturing a thin film transistor. 5. The method according to claim 1, wherein
At the time of performing the laser annealing step, the thickness of the oxide film formed on the surface of the amorphous semiconductor film is set to be 1/50 or less of the thickness of the gate insulating film. An etching step of removing an oxide film formed on a surface of the amorphous semiconductor film before performing the laser annealing step. 6. The method for manufacturing a thin film transistor according to claim 5, wherein in the etching step, wet etching using an etching solution containing hydrogen fluoride is performed on a surface of the amorphous semiconductor film. . 7. The method for manufacturing a thin film transistor according to claim 5, wherein in the etching step, dry etching using an etching gas containing fluorine is performed on a surface of the amorphous semiconductor film. 8. The method according to claim 5, wherein
After performing the etching step, the exposure time during which the semiconductor film is exposed to an oxygen-containing atmosphere until the laser annealing step is performed is T time, and the thickness of the gate insulating film is t angstroms. A method for manufacturing a thin film transistor, wherein the exposure time and the thickness of the gate insulating film satisfy a relationship of the following expression: T ≦ t / 500. 9. The method according to claim 1, wherein
At the time of performing the laser annealing step, the thickness of the oxide film formed on the surface of the amorphous semiconductor film is set to be 1/50 or less of the thickness of the gate insulating film. A method of manufacturing the thin film transistor, wherein the surface of the amorphous semiconductor film is kept in a non-oxidizing atmosphere until the laser annealing step is performed. 10. The method according to claim 1, wherein the laser annealing step is performed in an atmosphere containing no oxygen. 11. An active matrix substrate, wherein at least a pixel switching thin film transistor is manufactured on an active matrix substrate of an electro-optical device by using the method of manufacturing a thin film transistor according to any one of claims 1 to 10. Manufacturing method. 12. An electro-optical device using the active matrix substrate defined in claim 11.