JP2000358169A - External synchronization compensating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an external synchronization compensating circuit which can process the video signals without breaking a display image and also can perform smooth switching of video signals. SOLUTION: This circuit includes an external synchronization timing generation circuit 8 which generates an external reset timing signal at the fall of a synchronizing signal, a counter means which selects the external reset timing signal or the count value as an input signal in response to an internal/external synchronization switching signal and resets the count value according to an input signal, an external synchronization compensation timing generation circuit 9 which monitors the count value and then transmits and outputs an external reset timing signal if the count value is included in a compensation range that is previously set, and a timing decoder which generates a timing signal according to the count value and generates a timing signal in response to the external reset timing signal which is outputted from the circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external synchronization compensating circuit particularly designed for a set base having a plurality of video signal processing circuits.

[0002]

2. Description of the Related Art Recently, digitization / SOC (Syst
(Em On a Chip) has been advanced, and even in the video field set base, all signal processing circuits are
The number of cases in which the components are integrated on a chip and integrated into an LSI is increasing.

However, there are still cases where an existing analog video processing circuit or the like is used, and as shown in FIG. 4, two analog video processing circuits are mounted on the same set board (video field set base 100A).
One or more video signal processing circuits (analog video signal processing circuit 20, digital video signal processing circuit 21) may be used.

A conventional video field set base 1 shown in FIG.
00A, the output signals 20b and 22a of these two video signal processing circuits are transmitted to the analog mixer 23 on the board.
Switch with. In the case of such a circuit configuration, the output signal 20b of the analog video signal processing circuit 20, as shown in FIG.
And an output signal 22a of the digital video signal processing circuit 21 converted into an analog signal by the D / A converter 22.
Are synchronized, the output signal 23a is not disturbed even if the analog mixer 23 switches the output. However, when the output signal 20b and the output signal 22a are not synchronized, it is necessary to perform external synchronization of the video signal.

Usually, at the time of such synchronization, countermeasures such as blacking out the screen (black screen output) and not using the output of the circuit performing the synchronization are taken.

[0006]

However, the prior art has the following problems. FIG. 5 is an electric circuit diagram showing an example of a conventional synchronization circuit, and FIG.
6 is a timing chart of the synchronization circuit shown in FIG. The synchronization circuit shown in FIG. 5, for example, is provided inside the digital video signal processing circuit 21 shown in FIG. 4, and generates the horizontal timing signal 13a for generating the output signal 22a. . The horizontal counter 4a shown in FIG.
It has been reset at 5. At this time, the horizontal counter 4a normally counts the decode value, and the horizontal timing decoder 6 also decodes the timing normally. The operation timing at this time is (A) (normal timing) in FIG.

[0007] Here, the inside of FIG.
The switching circuit 26 is switched by the external synchronization switching signal 14
The input signal of the counter 24 is set to the internal reset timing 2
When switching from 5 to the external reset timing signal 18, the counter 24 switches its reset timing to the external reset timing signal 18. However, the internal reset timing 25 and the external reset timing signal 18 are completely asynchronous, and it is not known at what timing the reset operation is performed. For example, when the reset is performed by the external reset timing signal 18 at the timing as shown in FIG. 6B, a decoding error occurs and the correct horizontal timing signal 13a cannot be generated (FIG. 6: xa). Therefore, the processing in the digital video signal processing circuit 21 (FIG. 4) using the horizontal timing signal 13a also fails.

Conventionally, after resetting by the external reset timing signal 18, an erroneous video signal is generated by blacking out the screen for a period until the video signal processing is normally performed, for example, one frame period. The output was not displayed. That is, at the time of external synchronization, there is a problem that nothing is temporarily displayed on the display screen.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a video signal without causing a breakdown on a display screen without blackout (black screen output) or the like. It is another object of the present invention to provide an external synchronization compensating circuit capable of performing a process and smoothly switching a video signal.

[0010]

Means for Solving the Problems In order to solve the above problems, the present invention has the following constitution. The gist of the invention according to claim 1 is an external synchronization adjustment compensation circuit configured on a set base having a plurality of video signal processing circuits,
An external synchronization timing generation circuit for generating and outputting an external reset timing signal at the falling edge of an externally input synchronization signal; and counting the external reset timing signal in response to an internal / external synchronization switching signal input externally Counter means for selecting one of the values as an input signal and resetting the count value in accordance with the input signal; and the count value and the external reset timing signal output from the external synchronization timing generation circuit being input. Monitoring the count value, and if the count value is within a preset compensation range, an external synchronization compensation timing generation circuit that passes and outputs the external reset timing signal, and a video signal generation circuit that generates a video signal based on the count value. For generating the external synchronization compensation timing. Wherein the external reset timing signal is outputted, it consists in the external synchronizing combined compensation circuit comprising: a timing decoder for generating the timing signal based on the external reset timing signal. The gist of the invention described in claim 2 is that the external synchronization compensation timing generation circuit compares the preset compensation range with the counter value output from the counter means, and determines that the compensation range is smaller than the counter value. A comparison means for outputting a signal indicating a gate ON when the signal is large, an output of the comparison means connected to one input, and the external reset timing signal output from the external synchronization timing generation circuit to another input. 2. An external synchronization adjustment compensating circuit according to claim 1, further comprising: a gate means which is inputted and passes and outputs said external reset timing signal only when a signal indicating a gate ON is received from said comparing means. The gist of the invention according to claim 3 is that the comparing means includes a decoding circuit A that decodes the preset compensation range and compares it with the counter value. In the synchronization compensation circuit. The gist of the invention according to claim 4 is that, when the compensation range is larger than the counter value, the comparing means outputs an H level signal indicating a gate ON, and the gate means outputs the H level signal from the comparing means. 4. An external synchronization adjustment compensation circuit according to claim 2, wherein the AND gate is an AND gate that passes and outputs the external reset timing signal only when a signal arrives. The gist of claim 5 is that the timing decoder comprises:
A decoding circuit B for decoding the counter value output from the counter means; one input connected to the output of the decoding circuit B; and the other input connected to the AND gate of the external synchronization compensation timing generation circuit And an OR gate that outputs an H level when one of the inputs is at an H level, and a flip-flop that has an input connected to the output of the OR gate and generates a timing signal for generating a video signal. An external synchronization adjustment compensating circuit according to claim 4 is provided. The gist of the invention according to claim 6 resides in the external synchronization adjustment compensation circuit according to any one of claims 1 to 5, wherein the timing decoder generates a horizontal timing for generating a video signal. The gist of the invention according to claim 7 is that the timing decoder generates a vertical timing for generating a video signal.
5. The external synchronization adjustment compensating circuit according to any one of 5. The gist of the invention according to claim 8 is that the counter means selects one of the external reset timing signal and the count value as the input signal in response to an internal / external synchronization switching signal input from the outside. And a counter circuit for resetting a count value according to the input signal.
7. The external synchronization adjustment compensating circuit according to any one of 7. The gist of the invention according to claim 9 resides in an IC provided with the external synchronization compensation circuit according to claims 1 to 8. The gist of the invention described in claim 10 resides in a signal processing circuit including the external synchronization compensation circuit described in claims 1 to 8. The gist of the invention according to claim 11 resides in an electric circuit board including the external synchronization compensation circuit according to claims 1 to 8.
The gist of the invention according to claim 12 is an external synchronization adjustment compensation method configured on a set board having a plurality of video signal processing circuits, wherein the external synchronization timing generation circuit comprises:
An external reset timing signal is generated and output at the falling edge of a synchronization signal input from the outside, and the counter means
One of the external reset timing signal and the count value is selected as an input signal according to an internal / external synchronization switching signal input from outside, and the count value is reset according to the input signal. The generation circuit inputs the count value and the external reset timing signal output from the external synchronization timing generation circuit, and the external synchronization compensation timing generation circuit includes:
The count value is monitored, and if the count value is within a preset compensation range, the external reset timing signal is passed through and the timing decoder outputs a timing signal for generating a video signal based on the count value. Is generated, and when the external reset timing signal of the external synchronization compensation timing generation circuit is output, the timing signal is generated based on the external reset timing signal.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram illustrating a system configuration of an external synchronization compensation circuit according to an embodiment of the present invention. As shown in FIG. 1, the external synchronization compensation circuit according to the present embodiment has two types of signal processing circuits (own video signal processing circuit 1 and external video signal processing circuit 10). The own video signal processing circuit 1 includes a synchronizing signal generation circuit 2 for generating timing and a video signal processing circuit 3 for changing the state of a video signal.

The synchronizing signals (VSYNC, HSYNC) from the external video signal processing circuit 10
And the synchronization signal generation circuit 2 performs synchronization adjustment processing (processing for matching the horizontal timing and the vertical timing of the video signal between the external video signal processing circuit 10 and the own video signal processing circuit 1). . Synchronous signal generation circuit 2
(Horizontal timing signal 13a, vertical timing signal 13b) are processed by the video signal processing circuit 3 and output to the outside as a video signal output 12.

An external synchronization compensation timing generation circuit 9 provided in accordance with the present invention generates compensation timing for each data handled in the series of processing in order to compensate the synchronization timing of the data, and generates a compensation timing signal as a compensation timing signal. It outputs to the horizontal timing decoder 6 and the vertical timing decoder 7.

First, an outline of the operation of the present embodiment will be described. The external synchronization timing generation circuit 8 outputs synchronization signals (VSYNC, HS) from the external video signal processing circuit 10.
YNC) is detected, and an external reset timing signal 18 which is an external synchronization timing is generated.

Next, in this embodiment, the external synchronization compensation timing generation circuit 9 generates a compensation timing signal based on the external reset timing signal 18 output from the external synchronization timing generation circuit 8.

With the compensation timing signal thus obtained, the horizontal counter 4 and the horizontal timing decoder 6
The vertical counter 5 and the vertical timing decoder 7 generate the horizontal timing signal 13a.
3b is generated and supplied to the video signal processing circuit 3. The horizontal counter 4 and the vertical counter 5 correspond to the horizontal counter 4 described above.
a (FIG. 5), and the description is omitted. The video signal processing circuit 3 performs processing such as NTSC encoding, etc., depending on the timing of the supplied horizontal and vertical timing signals 13a and 13b, depending on the case, and outputs it as a video signal output 12.

FIG. 2 is an electric circuit diagram showing the internal configuration of the external synchronization compensation timing generation circuit 9 and the horizontal timing decoder 6 shown in FIG. As shown in FIG.
The horizontal timing decoder 6 includes a decoding circuit 16 and
OR6a and timing decode flip-flop 19
It consists of. Further, the external synchronization compensation timing generation circuit 9 includes a horizontal external synchronization compensation timing generation circuit 9.
a and a vertical external synchronization compensation timing generation circuit 9b. The horizontal external synchronization compensation timing generation circuit 9a generates a compensation timing signal based on the output of the horizontal counter 4 and outputs it to the horizontal timing decoder 6, and the vertical external synchronization compensation timing generation circuit 9b outputs the output of the vertical counter 5 A compensation timing signal is generated based on the signal and output to the vertical timing decoder 7.

Horizontal external synchronization compensation timing generation circuit 9a
Is composed of a compensation range decoding circuit 17 and an AND 6b. The compensation range decoding circuit 17 of the external synchronization compensation timing generation circuit 9 monitors the horizontal timing signal output from the horizontal counter 4 and outputs an H level if the count value is within a preset compensation period. The AND 6 b outputs an external reset timing signal 18, which is an external synchronous reset timing, during the compensation period (the output of the compensation range decode circuit 17 is at H level).
When (H level) is input, an H level is output as a compensation timing signal.

In response, the OR 6a of the horizontal timing decoder 6 outputs the external reset timing signal 18 in place of the ordinary decode signal from the decode circuit 16. The timing decode flip-flop 19
Internal timing generation is performed based on the output of R6a.
The configurations and functions of the vertical external synchronization compensation timing generation circuit 9b and the vertical timing decoder 7 are the same as those of the horizontal external synchronization compensation timing generation circuit 9a and the horizontal timing decoder 6, respectively, and the description is omitted.

The operation of the horizontal external synchronization compensation timing generation circuit 9a and the horizontal timing decoder 6 according to the present embodiment will be described below. First, the normal (internal synchronization timing) operation will be described with reference to the timing chart of FIG. Normal horizontal timing decoder 6
Generates an internal timing signal by enabling an output signal obtained by the decoding circuit 16 decoding the counter value of the horizontal counter 4 operating at internal timing.

On the other hand, the reset operation based on the external synchronization timing will be described with reference to the timing chart of FIG. At the time of external synchronization, the horizontal counter 4
The counter value generated from the external synchronization timing is reset by the external reset timing signal 18.

At this time, the timing of the internal counter of the horizontal counter 4 and the external reset timing signal 18 are asynchronous, and it is uncertain at what timing the counter is reset. If the counter is reset at this uncertain timing, the count value that should be counted is skipped, a decoding error occurs, and an internal timing signal that should be output cannot be generated.

Therefore, the external synchronization compensation timing generation circuit 9 sets a compensation period by the compensation timing signal, and when an external reset operation (the arrival of the external reset timing signal 18) occurs during the compensation period, the external reset is performed. The timing signal 18 is replaced with the counter decode signal, and this is enabled to generate an internal timing signal.

Since the external synchronization compensating circuit according to the embodiment is configured as described above, no matter at what timing the external synchronization is adjusted, the video signal processing inside the circuit can be performed without failure. The effect that it can be made to play is produced.

In the present embodiment, the present invention is not limited to this, and can be applied to a mode suitable for applying the present invention.

Further, the number, position, shape, etc. of the above-mentioned constituent members are not limited to the above-mentioned embodiment, but can be set to a suitable number, position, shape, etc. for carrying out the present invention.

In each of the drawings, the same components are denoted by the same reference numerals.

[0028]

Since the present invention is configured as described above, the following effects can be obtained. Regardless of the timing at which synchronization with the outside is achieved, the video signal processing inside the circuit can be processed without failure. In addition, since a video signal output synchronized with an external video signal can be output, blackout processing is not required at the time of signal switching, and continuous video can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system configuration of an external synchronization compensation circuit according to an example of an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing an internal configuration of an external synchronization compensation timing generation circuit 9 and a horizontal timing decoder 6 shown in FIG.

3A is a timing chart at the internal synchronization timing of the horizontal external synchronization compensation timing generation circuit 9a and the horizontal timing decoder 6 shown in FIG. 1, and FIG. 3B is a timing chart at the external synchronization timing. is there. FIG.

FIG. 4 is an electric circuit diagram showing a configuration of a conventional video field set board 100A.

FIG. 5 is an electric circuit diagram showing a configuration of a conventional synchronization circuit.

6A is a timing chart at a normal timing of the synchronization circuit shown in FIG. 5, and FIG. 6B is a timing chart at an external synchronization timing.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 own video signal processing circuit 2 synchronization signal generation circuit 3 video signal processing circuit 4 horizontal counter 4 a horizontal counter 5 vertical counter 6 horizontal timing decoder 6 a OR 6 b AND 7 vertical timing decoder 8 external synchronization timing generation circuit 9 external synchronization compensation timing generation circuit 9a Horizontal external synchronization compensation timing generation circuit 9b Vertical external synchronization compensation timing generation circuit 10 External video signal processing circuit 11 Video signal output 12 Video signal output 13a Horizontal timing signal 13b Vertical timing signal 14 Internal / external synchronization switching signal 16 Decoding circuit 17 Compensation Range decode circuit 18 External reset timing signal 19 Timing decode flip-flop 20 Analog video signal processing circuit 20a Synchronous signal 20b Output signal 21 Digital video signal processing circuit 2 D / A converter 22a outputs the signal 22b output signals 23 Analog mixer 23a outputs the signal 24 counter 25 internal reset timing 26 switching circuit 100A video field set foundation

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C020 AA11 BA07 BA09 BA11 BB07 CA13 CA15 5J106 AA03 BB04 DD09 DD17 DD46 HH09 HH10 JJ06 KK24

Claims (12)

[Claims] 1. An external synchronization compensation circuit configured on a set board having a plurality of video signal processing circuits, wherein an external reset timing signal is generated and output at a falling edge of an externally input synchronization signal. An external reset timing signal generating circuit, which selects one of the external reset timing signal and the count value as an input signal according to an internal / external synchronization switching signal input from the outside, and counts the count value according to the input signal. Counter means for resetting, and the count value and the external reset timing signal output from the external synchronization timing generation circuit are input, the count value is monitored, and the count value is within a preset compensation range. If so, the external synchronization compensation timing generation circuit for passing and outputting the external reset timing signal A timing signal for generating a video signal based on the count value, and when the external reset timing signal of the external synchronization compensation timing generation circuit is output, the timing signal is generated based on the external reset timing signal. An external synchronization compensation circuit, comprising: a timing decoder for generating the timing signal. 2. The external synchronization compensation timing generation circuit compares the preset compensation range with the counter value output from the counter means, and turns on a gate when the compensation range is larger than the counter value. A comparison means for outputting a signal representing the external reset timing signal output from the external synchronization timing generation circuit to one input. 2. The external synchronizing compensation circuit according to claim 1, further comprising: gate means for passing and outputting said external reset timing signal only when a signal indicating a gate ON comes from the means. 3. The external synchronization adjustment compensation circuit according to claim 2, wherein said comparison means includes a decoding circuit A for decoding said compensation range set in advance and comparing with said counter value. 4. The comparison means outputs an H level signal indicating a gate ON when the compensation range is larger than the counter value, and the gate means outputs a signal of the H level from the comparison means. 4. The external synchronization adjustment compensating circuit according to claim 2, wherein only an AND gate that passes and outputs the external reset timing signal is provided. 5. The timing decoder, comprising: a decoding circuit B for decoding the counter value output from the counter means; one input connected to an output of the decoding circuit B;
The other input is connected to the output of the AND gate of the external synchronization compensation timing generation circuit. If one of the inputs is at the H level, the OR gate outputs an H level. The input is connected to the output of the OR gate. The external synchronization compensation circuit according to claim 4, further comprising a flip-flop that generates a timing signal for generating a video signal. 6. The external synchronization compensation circuit according to claim 1, wherein said timing decoder generates horizontal timing for generating a video signal. 7. The external synchronization compensation circuit according to claim 1, wherein said timing decoder generates a vertical timing for generating a video signal. 8. A switching circuit for selecting one of the external reset timing signal and the count value as the input signal in response to an internal / external synchronization switching signal input from the outside, 8. The external synchronization adjustment compensating circuit according to claim 1, further comprising: a counter circuit for resetting a count value according to a signal. 9. An IC comprising the external synchronization compensation circuit according to claim 1. 10. A signal processing circuit comprising the external synchronization compensation circuit according to claim 1. 11. An electric circuit board comprising the external synchronization compensation circuit according to claim 1. 12. A method for compensating external synchronization on a set board having a plurality of video signal processing circuits, wherein an external synchronization timing generation circuit is configured to perform an external reset at a falling edge of a synchronization signal input from the outside. Generating and outputting a timing signal; a counter means selecting one of the external reset timing signal and the count value as an input signal in accordance with an internal / external synchronization switching signal input from the outside;
Resetting a count value in response to the input signal; inputting the count value and the external reset timing signal output from the external synchronization timing generation circuit to an external synchronization compensation timing generation circuit; The circuit monitors the count value, and if the count value is within a preset compensation range,
Passing the external reset timing signal, a timing decoder generating a timing signal for generating a video signal based on the count value, and outputting the external reset timing signal of the external synchronization compensation timing generation circuit, An external synchronization adjustment compensation method, wherein the timing signal is generated based on the external reset timing signal.