JP2000511002A5 - - Google Patents
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- Publication number
- JP2000511002A5 JP2000511002A5 JP1998529278A JP52927898A JP2000511002A5 JP 2000511002 A5 JP2000511002 A5 JP 2000511002A5 JP 1998529278 A JP1998529278 A JP 1998529278A JP 52927898 A JP52927898 A JP 52927898A JP 2000511002 A5 JP2000511002 A5 JP 2000511002A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Description
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP97200847.8 | 1997-03-21 | ||
| EP97200847 | 1997-03-21 | ||
| PCT/IB1998/000248 WO1998043361A2 (en) | 1997-03-21 | 1998-02-27 | Iddq testable programmable logic array and a method for testing such a circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000511002A JP2000511002A (ja) | 2000-08-22 |
| JP2000511002A5 true JP2000511002A5 (ja) | 2005-10-06 |
Family
ID=8228131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10529278A Ceased JP2000511002A (ja) | 1997-03-21 | 1998-02-27 | Ｉｄｄｑ試験できるプログラム可能論理アレイ及びそのような回路を試験するための方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6127838A (ja) |
| JP (1) | JP2000511002A (ja) |
| DE (1) | DE69829929T2 (ja) |
| TW (1) | TW384474B (ja) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6762618B1 (en) * | 2002-10-11 | 2004-07-13 | Lattice Semiconductor Corporation | Verify scheme for a multi-level routing structure |
| US7352170B2 (en) * | 2006-06-13 | 2008-04-01 | International Business Machines Corporation | Exhaustive diagnosis of bridging defects in an integrated circuit including multiple nodes using test vectors and IDDQ measurements |
| US7541832B1 (en) * | 2007-04-30 | 2009-06-02 | Arizona Board Of Regents For And On Behalf Of Arizona State University | Low power, race free programmable logic arrays |
| US8044676B2 (en) * | 2008-06-11 | 2011-10-25 | Infineon Technologies Ag | IDDQ testing |
| US8476917B2 (en) * | 2010-01-29 | 2013-07-02 | Freescale Semiconductor, Inc. | Quiescent current (IDDQ) indication and testing apparatus and methods |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4212026A (en) * | 1977-06-24 | 1980-07-08 | International Business Machines Corporation | Merged array PLA device, circuit, fabrication method and testing technique |
| DE3009945C2 (de) * | 1979-03-15 | 1987-03-19 | Nippon Electric Co., Ltd., Tokio/Tokyo | Funktionsprüfbarer, integrierter Schaltkreis |
| DE3135368A1 (de) * | 1981-09-07 | 1983-03-31 | Siemens AG, 1000 Berlin und 8000 München | Verfahren und anordnung zur funktionspruefung einer programmierbare logikanordnung |
| US4768196A (en) * | 1986-10-28 | 1988-08-30 | Silc Technologies, Inc. | Programmable logic array |
| JPH01109921A (ja) * | 1987-10-23 | 1989-04-26 | Ricoh Co Ltd | プログラマブルロジックアレイ |
| JP2575899B2 (ja) * | 1989-10-26 | 1997-01-29 | 株式会社東芝 | プリチャージ式論理回路 |
| JP3129761B2 (ja) * | 1991-05-02 | 2001-01-31 | 株式会社東芝 | Ｐｌａのテスト容易化回路 |
-
1997
- 1997-07-21 TW TW086110345A patent/TW384474B/zh not_active IP Right Cessation
-
1998
- 1998-02-27 DE DE69829929T patent/DE69829929T2/de not_active Expired - Lifetime
- 1998-02-27 JP JP10529278A patent/JP2000511002A/ja not_active Ceased
- 1998-03-03 US US09/033,728 patent/US6127838A/en not_active Expired - Lifetime