JP2003100706A - Dry etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dry etching method which can improve uniformity of the depth of etching over the surface of a wafer. SOLUTION: In this dry etching method, the primary rear surface of a silicon wafer W is covered with a thermal buffer film 20, and the primary front surface of the silicon wafer W is etched while the thermal buffer film 20 is cooled by blowing a cooling gas or the like. The thermal buffer film 20 is integrally formed with the silicon wafer W, and a silicon oxide film having a smaller heat conductivity than that of a single crystal or a silicon nitride film is adopted. Since the thermal buffer film 20 reduces the dispersion of cooling temperature over the surface, the temperature over the surface to be etched can be uniformalized, and then the uniformity in etching depth can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for dry etching a silicon wafer.

[0002]

2. Description of the Related Art In order to achieve high integration and high density of semiconductor devices, it is important to advance miniaturization of transistors and wirings, which largely depends on the progress of photoetching technology. Regarding the etching technique, there are wet etching using a chemical solution and dry etching not using it, but dry etching is overwhelmingly advantageous from the viewpoint of fine processing.

Generally speaking, dry etching is a method in which plasma is generated by applying a high frequency to a suitable gas, and ions or radicals obtained from the plasma are applied to the wafer to perform etching. Among them, RIE (Reactive Ion Etching), in which reactive ions are extracted from plasma by utilizing self-bias voltage to perform etching while keeping the wafer at a low temperature of 0 ° C. or lower, is anisotropic etching. well known. As a method for cooling a wafer, a mechanism for directly blowing a gas such as He onto the back surface of the wafer to cool it, a mechanism for cooling the support table on which the wafer is placed with a coolant such as water, etc. are provided in the etching apparatus. It is normal.

[0004]

However, it is difficult to uniformly cool the entire disk-shaped wafer, and the temperature distribution within the surface tends to be non-uniform. This becomes more remarkable as the diameter of the wafer increases. If a temperature difference occurs in the plane of the wafer, a difference in etching rate occurs and the etching depth becomes uneven, which is not preferable. As device miniaturization progresses and stricter dimensional accuracy is required, variations in etching depth may lead to specific problems. Therefore, more precise etching technology is desired.

An object of the present invention is to provide a dry etching method for making the etching depth in the surface uniform.

[0006]

Means for Solving the Problems and Actions / Effects In order to solve the above problems, the dry etching method of the present invention is a dry etching method in which etching is performed while cooling from the main back surface side of the silicon wafer. The back surface is covered with a thermal buffer film, and the main surface of the silicon wafer is etched.

During the dry etching process, the wafer is positively cooled from the side opposite to the etching surface (main back surface side) by using an appropriate cooling means. In the present invention, the thermal buffer film formed on the surface layer portion on the main back surface side is directly cooled. This thermal buffer film alleviates variations in the cooling temperature within the surface. That is, even if there is some difference in the cooling temperature on the back surface side, the difference is buffered by the thermal buffer film. After all, since the in-plane temperature distribution can be made uniform in the vicinity of the contact interface between the thermal buffer film and the silicon single crystal portion, a temperature difference on the etching surface is unlikely to occur. Therefore, it is possible to improve the uniformity of the etching depth within the surface.

[0008]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the accompanying drawings. Among the dry etching methods, it has been described that RIE, in which reactive ions are extracted from plasma by utilizing self-bias voltage and anisotropic etching is the mainstream. Therefore, a parallel plate type RIE device, which is one form of a device for performing RIE, will be described as a typical example.

First, FIG. 1 schematically shows a parallel plate type RIE apparatus. The parallel plate type RIE device 1 has a gas inlet 10
And metal vacuum chamber 2 having a gas outlet 11
Inside, the grounded anode (anode) 3 and high frequency power supply R
And a cathode (cathode) 4 connected to F. A vacuum pump is attached to the gas outlet 11 so that the inside of the chamber 2 can be evacuated and adjusted to an appropriate pressure. While maintaining the inside of the chamber 2 at an appropriate pressure, an etching gas is introduced into the chamber 2 from the gas inlet 10 and a high frequency is applied between the anode 3 and the cathode 4 to apply the etching gas to the introduced etching gas. It is a mechanism to generate plasma based on.

With the generation of plasma, many electrons having a higher mobility than ions flow into the electrodes. At the same time, since the blocking capacitor 5 is negatively charged, the cathode 4 is negatively biased. Therefore, the reactive ions are accelerated to a negative voltage due to their self-bias and bombard the silicon wafer W placed on the cathode 4. In this way, the reactive ions collide with the silicon wafer W from the direction perpendicular to the thickness direction, and anisotropic etching can be performed.

The cathode 4 functions as a susceptor for positioning and holding the silicon wafer W which is the material to be etched by electrostatic force. The upper part of the cathode 4 facing the anode 3, that is, the contact portion with the silicon wafer W is constituted by a quartz electrode member 13. Since the entire upper surface of the cathode 4 is covered with the quartz electrode member 13, it is possible to prevent ions from spattering the main body of the cathode 4 and contaminating the silicon wafer W.

FIG. 2 is an enlarged view of the cathode 4. The cathode 4 is provided with a gas ejection mechanism for cooling the wafer. That is, for example, a cooling gas such as He gas is introduced into the cooling gas flow portion 12 formed so as to penetrate the cathode 4, and the cooling gas is cooled to the main back surface side opposite to the etching surface of the silicon wafer W. It is said that the gas can be blown at an appropriate pressure. The cooling gas flow portion 12 opening on the upper surface of the anode 4 and the central portion of the silicon wafer W which is the material to be etched are arranged so as to substantially coincide with each other. Then, the cooling gas flowing through the cooling gas flow portion 12 hits the back surface side of the silicon wafer W and branches through the flow, and passes through a very small gap formed between the anode 4 and the silicon wafer W. And exhausted into the chamber 2.

FIG. 3 is a schematic top view when the cathode 4 is observed from the anode 3 side. As shown in this figure, the cooling gas flowing through the cooling gas flow section 12 first cools the central portion of the silicon wafer W. Then, it flows outward in the radial direction along the main back surface and is exhausted from the peripheral edge of the silicon wafer W. With this cooling mechanism, the silicon wafer W is kept at 0 ° C. even during the etching process.
It is possible to keep below. A cooling mechanism in which an appropriate cooling medium is contained in the cathode 4 or a circulation channel of the cooling medium is formed can also be adopted.

By keeping the silicon wafer W at a low temperature, side etching due to radicals can be suppressed. However, the radicals that have reached the position where they are bombarded by the reactive ions cause chemical etching by utilizing the translational kinetic energy of the reactive ions (under the so-called ion assist effect). In this way, in RIE, etching progresses in cooperation with chemical reaction and physical sputtering. The dry etching method mainly using RIE is indispensable in situations where high etching accuracy is required, such as when forming alignment marks for positioning on a silicon wafer W and when forming trenches for trench isolation. To be done.

Although not limited to the cooling mechanism as described above, it is considerably difficult to cool the entire back surface side of the silicon wafer W at a constant temperature, and in such a case, a temperature difference occurs within the surface of the wafer. If the temperature distribution on the etched surface becomes uneven, the etching depth also becomes uneven, which is not desirable. Therefore, in the dry etching method of the present invention, the main back surface side of the silicon wafer W is covered with the thermal buffer film 20 having a thermal conductivity smaller than that of the silicon single crystal, and the main surface side is cooled while cooling the thermal buffer film 20. Etching (see FIGS. 1 and 2). This thermal buffer film 20 is
The thermal buffer film 2 has the effect of transmitting the cooling effect to the main surface side in the form of alleviating the variation of the cooling temperature within the surface.
It is possible to keep the temperature distribution on the etching surface more uniform as compared with the case of directly cooling without forming 0.

When the thermal conductivity of the thermal buffer film 20 is larger than that of the silicon single crystal portion to be etched, the heat generated by the etching is more easily transferred to the back surface side, and therefore the effect desired by the present inventors. Is hard to get. A high buffering effect is obtained when it has a thermal conductivity smaller than that of a silicon single crystal. It should be noted that the magnitude of the thermal conductivity is taken into consideration in the temperature range reached by the silicon wafer W during the etching process, for example, from minus several tens of degrees Celsius to plus several hundreds of degrees Celsius.

Usually, in order to give a uniform cooling effect to the etched surface, it is very troublesome to devise and improve the cooling means. However, according to the present invention, as shown in FIG.
The desired cooling effect can be sufficiently realized even with the simple cooling mechanism shown in FIG.

The thermal buffer film 20 is preferably one that can be integrally formed with the silicon wafer W, and for example, a silicon oxide film, a silicon nitride film or the like can be adopted. The silicon oxide film is suitable because it can be easily formed by a known thermal oxidation method or CVD method. When the CVD method is adopted, silicon dioxide is deposited on the main back surface side surface layer of the silicon wafer W by the CVD method. The silicon nitride film can also be formed by the thermal nitriding method or the CVD method. Regarding thermal conductivity, silicon single crystal: about 150 W / m · K, silicon dioxide (SiO ₂ ): about 1.5 W / m · K, silicon nitride (Si ₃ N ₄ ): about 20 W / m · K, And is preferable.

More specifically, when the thermal buffer film 20 is a silicon oxide film, its thickness is 0.2 μm or more.
It is desirable to adjust to 5 μm or less. When the thickness of the silicon oxide film 20 is less than 0.2 μm, the effect of transmitting the cooling effect to the main surface side cannot be sufficiently expected in the form of relaxing the in-plane temperature difference generated on the back surface side. For example, since the natural oxide film has a thickness of less than 0.2 μm, the effect of the present invention cannot be obtained. On the other hand, if the thickness exceeds 1.5 μm, the heat conductivity may be excessively lowered, cooling itself may be insufficient, and the cost for forming the oxide film increases, which is not preferable.

Further, since the buffering effect of the thermal buffer film 20 tends to depend on the film thickness thereof, this thermal buffer film 20
It is also possible to control the in-plane distribution of the etching depth on the main surface side based on the adjustment of the thickness. Thermal buffer film 20
When the thermal buffer film 20 is a silicon oxide film, the formation thickness is preferably 0.2 μm or more and 1.5 μm or less as described above, but the optimum value varies depending on the diameter of the silicon wafer W to be etched. . This is because the larger the diameter of the silicon wafer W, the larger the variation in the temperature distribution in the plane. Furthermore, the cooling temperature varies depending on the flow rate of the cooling gas, and the etching conditions vary depending on the flow rate and type of the etching gas used, the output of the applied high frequency power source, and the like. Therefore,
Under the etching conditions to be actually performed, the thickness of the thermal buffer film 20 is variously changed and dry etching is performed to determine in advance which thickness can achieve the most uniform etching depth. It is desirable to investigate and obtain knowledge about suitable values.

[0021]

EXAMPLE The following experiment was conducted to confirm the effect of the present invention. First, a silicon single crystal wafer W obtained by slicing a silicon single crystal ingot manufactured by a known single crystal growth method such as CZ (Czochralski) method is subjected to lapping, polishing, etc., and then backside is formed by a CVD method. A 0.4 μm silicon oxide film was formed on the side. Next, the main surface side serving as an etching surface was masked and patterned into a predetermined line width.

Using the silicon wafer W thus manufactured as the material to be etched, the parallel plate type R shown in FIG.
Using the IE apparatus 1, the main surface side was dry-etched to a depth of 0.7 μm. The flow rate of the He gas for cooling the back surface of the silicon wafer W is 50 cm ³ / m in the standard state.
In, the silicon wafer W was sufficiently cooled before generating plasma. The etching gas is CF ₄ and He.
Etching gas mixed with a ratio of 4: 1 is 200 cm
^It was introduced into the chamber 2 at a flow rate of ³ / min. The pressure in the chamber 2 was maintained at 680 mTorr, and the output of the high frequency power supply RF was 280 W. The measurement result of the in-plane etching depth is shown in FIG.

Next, as a comparative example, a silicon wafer W having no CVD oxide film formed on the main back surface side was subjected to dry etching by masking and patterning the main surface side under the same conditions as in the above embodiment. The measurement result of the in-plane etching depth is shown in FIG.

As can be seen from the measurement result of FIG. 4B, in the comparative example, the etching depth increases from the central portion of the silicon wafer W toward the peripheral portion. This result is considered to suggest that the cooling gas is blown to the central portion of the silicon wafer W so as to flow outward in the radial direction, so that the peripheral portion is less likely to be cooled than the central portion. . On the other hand, according to the method of the present invention, as shown in the measurement result of FIG. 4A, the in-plane etching depth is kept substantially uniform. Also from this result, by adopting the present invention,
It is clear that the in-plane etching depth can be made uniform.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a parallel plate type RIE apparatus.

FIG. 2 is an enlarged view of a cathode in the device of FIG.

FIG. 3 is a diagram schematically illustrating the flow of cooling gas in the apparatus of FIG.

FIG. 4 is a graph showing measurement results of in-plane distribution of etching depth.

[Explanation of symbols]

20 Thermal buffer film (silicon oxide film) W Silicon wafer

Claims (4)

[Claims] 1. A dry etching method in which etching is performed while cooling from the main back surface side of a silicon wafer, wherein the main back surface of the silicon wafer is covered with a thermal buffer film,
A dry etching method comprising etching the main surface of the silicon wafer. 2. The dry etching method according to claim 1, wherein the thermal buffer film has a thermal conductivity smaller than that of a silicon single crystal. 3. The dry etching method according to claim 1, wherein the thermal buffer film is a silicon oxide film or a silicon nitride film formed integrally with the silicon wafer. 4. The thermal buffer film is 0.2 μm or more and 1.5 or more.
The dry etching method according to claim 3, wherein the dry etching method is a silicon oxide film having a thickness of less than or equal to μm.