JP2003174141A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability as a semiconductor device, such as mechanical strength and moisture resistance, capable of improving a degree of integration by forming a wiring pattern on the entire surface of a multilayer board, and manufacturing thereof. Provide a method. SOLUTION: Wiring pads 41b of a two-layer board 52
Are formed thereon, a barrier metal layer 61 and an Au layer 62 are formed, and a semiconductor element 70 is formed thereon.
Implement Further, the prepreg 31 having the opening 31a provided thereon and another two-layer plate 54 are aligned and heat-pressed. No boundary surface between the insulating resin filled around the semiconductor element 70 and the two-layer plate 54 appears on the surface of the obtained semiconductor device 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
More specifically, the present invention relates to a semiconductor device with a built-in semiconductor element and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, semiconductor elements are embedded in a multilayer board in which a plurality of printed wiring boards are laminated in multiple stages.
A so-called buried type semiconductor device is known. FIG. 16 is a cross-sectional view of a typical embedded semiconductor device 100. Figure 1
As shown in FIG. 6, in this semiconductor device 100, three layers of printed wiring boards 101, 102, 103 are stacked,
Wiring patterns 104, 105, 106, 10 of four layers in total
7 are arranged, and the respective wiring patterns 104 to 107
Are interconnected by interlayer connecting members such as through holes 108A to 108E. The semiconductor element 120 is mounted on the wiring pad 109 arranged between the printed wiring boards 101 and 102.
Reference numeral 20 is embedded in a space 110 obtained by hollowing out a part of the printed wiring boards 102 and 103.

[0003]

By the way, in order to manufacture such an embedded type semiconductor device 100, a part of the printed wiring boards 102 and 103 is hollowed out from one side to embed the semiconductor element 120. Space 110 for this
After mounting the semiconductor element 120, it is common to embed the semiconductor element 120 by filling the gap around the semiconductor element 120 with an insulating sealing material 130 such as epoxy resin and curing it.

However, as described above, the printed wiring board 10
When a part of 2, 103 is mechanically hollowed out, the mechanical strength of the printed wiring boards 102, 103 is reduced, or the cut surface of the printed wiring boards 102, 103 at the time of hollowing out and the filled insulating sealing material 130. There is a problem in that moisture easily enters from the boundary surface of and and the moisture resistance is reduced.

Further, since the wiring pattern cannot be formed in the portion where the hollowed-out portion of the printed wiring board 103 is filled with the insulating sealing material 130, the wiring pattern cannot be formed by utilizing this portion and the degree of integration cannot be increased. There is a problem.

The present invention is an invention made to solve the above conventional problems. That is, the present invention provides a semiconductor device having high reliability as a semiconductor device such as mechanical strength and moisture resistance, and further capable of forming a wiring pattern on the entire surface of a multilayer board to improve the degree of integration, and a manufacturing method thereof. The purpose is to

[0007]

According to the method of manufacturing a semiconductor device of the present invention, an interlayer connecting member is inserted in the thickness direction of an insulating substrate, and conductor plates electrically connected by the interlayer connecting member are provided on both surfaces. A step of forming a wiring pattern and an electrode pad by patterning the provided two-layer conductor plate; a step of forming a silver paste bump on the electrode pad; and a barrier metal layer formed on the surface of the silver paste bump. And a step of forming a weldable metal layer on the surface of the silver paste bumps, a step of mounting a semiconductor element on the silver paste bumps, and opening a portion corresponding to the semiconductor element on the two-layer plate. A step of aligning the insulating substrate precursor and a two-layer board with bumps having conductor bumps on the wiring pattern of the two-layer board, the two-layer board, the insulating substrate precursor, and the two-layer board with bumps Under heating the plate and The bumps are inserted into the insulating substrate precursor by pressing, the two-layer plate and the two-layer plate with bumps are electrically connected, and the insulating substrate precursor is cured. And

Another method of manufacturing a semiconductor device according to the present invention comprises a step of forming a conductor bump at a predetermined position of one conductor plate, an insulating substrate precursor and another conductor plate on the conductor bump of the conductor plate. And a step of aligning, and pressing the one conductor plate, the insulating substrate precursor and the other conductor plate under heating to insert the conductor bump into the insulating substrate precursor, the one conductor Electrically connecting a plate and the other conductor plate, patterning the one conductor plate and / or another conductor plate to form a wiring pattern and an electrode pad, and silver on the electrode pad A step of forming a paste bump,
A step of forming a barrier metal layer on the surface of the silver paste bumps, a step of forming a weldable metal layer on the surface of the silver paste bumps, a step of mounting a semiconductor element on the silver paste bumps; Above, a step of aligning an insulating substrate precursor having an opening corresponding to the semiconductor element and a two-layer board with bumps, the two-layer board, an insulating substrate precursor, and the two-layer board with bumps And pressurizing under heating to insert the bumps into the insulating substrate precursor, electrically connecting the two-layer plate and the two-layer plate with bumps, and curing the insulating substrate precursor. It is characterized by having.

In the above-mentioned method for manufacturing a semiconductor device, as an example of the two-layer plate, a step of forming a conductor bump on a conductor plate, and an insulating substrate precursor and another conductor plate are superposed on the conductor bump. Step, pressing the stacked conductor plate, the insulating substrate precursor, and another conductor plate under heating to cause the conductor bump to penetrate the insulating substrate precursor and cure the insulating substrate precursor. The semiconductor substrate manufactured by the manufacturing method comprising

In the above method of manufacturing a semiconductor device, an Ni layer can be given as an example of the barrier metal layer.
An example of the weldable metal is Au.

In the method of manufacturing a semiconductor device described above, as a method of forming the conductor bump, a method of forming the conductor bump with a conductive paste by using a printing technique can be mentioned.

In the method of manufacturing a semiconductor device described above, as a method of forming the conductor bump, a method of forming the conductor bump by depositing a plating metal on the surface of the supporting substrate can be mentioned.

In the method of manufacturing a semiconductor device described above, as a method of forming the conductor bump, a method of forming the conductor bump by etching the surface of the supporting substrate can be mentioned.

A semiconductor device according to the present invention comprises: a first substrate having an interlayer connecting member inserted therethrough; and a first substrate laminated on the first substrate,
A second substrate having an interlayer connecting member inserted therein, a third substrate laminated on the second substrate and having an interlayer connecting member inserted therein, and arranged on an outer surface of the first substrate. A first wiring pattern, a second wiring pattern and an electrode pad arranged between the first substrate and the second substrate, and an electrode pad included in the second substrate. A semiconductor element mounted thereon, a third wiring pattern provided between the second substrate and the third substrate, and a third wiring pattern provided on an outer surface of the third substrate. And a wiring pattern of.

Another semiconductor device of the present invention comprises: a first substrate having an interlayer connecting member inserted therethrough; a second substrate laminated on the first substrate and having an interlayer connecting member inserted therethrough; The second
And a fourth substrate laminated on the third substrate and having an interlayer connecting member inserted thereinto, a fourth substrate laminated on the third substrate and having an interlayer connecting member inserted therethrough, and the fourth substrate. A fifth substrate laminated on the first substrate and having an interlayer connecting member inserted therethrough;
A first wiring pattern disposed on the outer surface of the substrate of
A second wiring pattern and a first electrode pad arranged between the first substrate and the second substrate; and a second wiring pattern included in the second substrate The mounted first semiconductor element, the second substrate and the third
A third wiring pattern disposed between the third substrate and the fourth substrate, a fourth wiring pattern disposed between the third substrate and the fourth substrate, and a second electrode pad, A second semiconductor element included in a fourth substrate and mounted on the second wiring pad, and a fifth wiring provided between the fourth substrate and the fifth substrate. Pattern and the fifth
A sixth wiring pattern arranged on the outer surface of the substrate of
It is characterized by including.

In the present invention, the semiconductor element is housed in the opening of the insulating substrate precursor, and the insulating substrate is further stacked on the opening to completely cover the semiconductor element. It is possible to obtain a semiconductor device having high reliability and capable of forming a wiring pattern on the entire surface of a multilayer board to improve the degree of integration, and a manufacturing method thereof.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described below. 1 and 2 are flowcharts of the method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 3, 4 and 5 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.

In order to manufacture the semiconductor device according to this embodiment, first, a so-called two-layer board having wiring patterns formed on both surfaces of an insulating substrate is prepared. FIG. 1 shows a flowchart of the method for manufacturing the two-layer board, and FIG. 3 shows a cross-sectional view of the two-layer board in the process of being manufactured. To manufacture this two-layer board, first, as shown in FIG. 3A, a conductor board 10 such as a copper foil is prepared. The conductor bumps 20, 20, ... Are formed on the conductor plate 10 by using a printing technique.

As a method for forming the conductor bumps 20, 20, ..., For example, masking is performed in which holes are provided in the bump forming portions (step 1). A conductive paste, for example, a paste-like composition in which fine metal particles such as silver are dispersed in a liquid resin such as an epoxy resin is filled in the holes (step 2). A squeegee (step 3) is applied from the upper surface of the masking, and the masking is peeled off (step 4).
In this way, after forming the substantially conical conductor bumps 20, 20, ... As shown in FIG. 3B, the conductor bumps 20, 20, ... Are dried and cured (step 5). .

Next, as shown in FIG. 3C, a prepreg (insulating substrate precursor) 30 is formed on the conductor bumps 20, 20, ... In a reinforcing material such as a glass fiber mat, epoxy resin or the like. 1. The insulating resin impregnated with the insulating resin is laminated, and another conductor plate 40 such as a copper foil is laminated on the prepreg 30 (step 6). In this state, heat press, that is, pressurizing under heating (step 7). By this heat pressing, the conductor bumps 2
0, 20, ... Penetrate through the prepreg 30 to electrically connect the conductor plate 10 and the conductor plate 40, and at the same time, the prepreg 30 is hardened, and as shown in FIG. A layered printed wiring board 50 is obtained. By patterning the conductor plates 10 and 40 on the surface of the two-layer printed wiring board 50 by etching or the like (step 8), the two-layer board 52 having the wiring patterns 11 and 41a is formed.

Next, the wiring pattern 41a on the two-layer board 52
Of these, as shown in FIG. 4F, electrode pads 41b, 41b, ... Formed at positions corresponding to the electrodes of the semiconductor element.
Silver paste bumps 60, 60, ... Are formed on top. The method of forming the silver paste bumps 60, 60, ... Is substantially the same as the method of forming the conductor bumps 20, 20 ,.

That is, masking is performed by forming a hole in the bump forming portion (step 1a). A conductive composition, for example, a paste-like composition in which fine metal particles such as silver are dispersed in a liquid resin such as an epoxy resin is filled in the holes (step 2a). In this method, a squeegee (step 3a) is applied from the upper surface of the masking, and the masking is peeled off (step 4a).

However, the silver paste bumps 6 formed here
The size of 0, 60, ... is 300 to 500 μm in height,
The bottom radius is 150 to 350 μm. This is to correspond to the size of the semiconductor element 70 described later.

Next, after the masking is peeled off, the silver paste bumps 60, 60, ... Are cured (step 5a), and then Ni plating treatment (step 6a) such as electrolytic plating or electroless plating is performed. , And the surface of the electrode pad 41b at the bottom thereof is formed with a Ni layer 61 as a barrier metal layer as shown in FIG. 4 (g) (step 6a). Then, an Au layer 62 is formed by performing an Au plating process (step 7a) on the Ni layer 61. Thus, FIG. 4 (h)
A substrate with bumps 52A as shown in FIG.

Next, the bumped substrate 52 thus obtained
Silver paste bumps 60 of A, 60, ...
As shown in (i), ACF (anisotropic conductive adhesive layer)
63 is arranged, and the semiconductor element 70 is so arranged that the electrode plates 71, 71, ... Face the electrode pads 41b, 41b ,.
Are aligned (step 8a).

Then, when the semiconductor element 70 and the substrate with bumps 52A are pressed in this state, the silver paste bumps 60, 60, ... Are ACF (anisotropic conductive adhesive layer) as shown in FIG. 4 (j). The electrode plates 71, 71, ... Are pierced through 63 and pressed (step 9a). At this time, Au layers 62, 62, ... Are formed on the surfaces of the silver paste bumps 60, 60, ... And the electrode plates 71, 71 ,. And electrode plate 71,
An Al-Au junction is formed between the electrode pads 41b, 41b, ... And the electrode plates 71, 71 ,.
It is electrically joined via a CF (anisotropic conductive adhesive layer) 63. Thus, the mounted substrate 53 on which the semiconductor element 70 is mounted as shown in FIG. 4 (j) is obtained.

Next, the perforated prepreg 31 and the bumped two-layer board 54 are aligned on the mounted substrate 53 thus obtained as shown in FIG. 5 (k) (step 10a).
The prepreg 31 used here is one in which a reinforcing material such as glass fiber is impregnated with an insulating liquid thermosetting resin such as epoxy resin, and a portion corresponding to a semiconductor element is punched out to provide an opening 31a. 2 layer board with bump 5
In FIG. 4, wiring patterns are formed on both surfaces of an insulating material layer in which an interlayer connecting member is inserted, and conductor bumps are formed on the wiring patterns.

Next, in this state, the mounted substrate 53, the perforated prepreg 31, and the two-layer plate 54 with bumps are subjected to heat press to be heated and pressed (step 11a). As a result, as shown in FIG.
The conductive bumps No. 4 penetrate through the perforated prepreg 31 to electrically connect the mounted substrate 53 and the bumped two-layer board 54. At the same time, the epoxy resin impregnated in the perforated prepreg 31 flows out to expel air from the gap between the opening 31a of the perforated prepreg 31 and the semiconductor element 70 housed therein to seal this gap. . Furthermore,
The heat of this heat press cures the epoxy resin to obtain the so-called four-layer wiring type semiconductor device 70-embedded semiconductor device 1 as shown in FIG.

As described above, in the semiconductor device 1 according to the present embodiment, the semiconductor element 70 is embedded inside the multilayer board, and the resin for sealing the periphery of the semiconductor element 70 and the outer periphery of this resin are surrounded. The interface with the multilayer board is not exposed on the surface of the semiconductor device 1. Therefore, it is possible to prevent moisture from penetrating along the boundary surface, and as a result, a semiconductor device having high moisture resistance can be obtained.

Further, in the semiconductor device 1 according to the present embodiment, the mounted semiconductor element 70 is embedded inside, and the surfaces of the two-layer plates 53 and 54 are only exposed on the surface of the semiconductor device 1. Is. Therefore, this two-layer plate 53,
By using the surface of 54, another wiring pattern, a semiconductor element, etc. can be mounted, and the integration degree of a semiconductor device can be improved further.

(Second Embodiment) The second embodiment of the present invention will be described below.
Manufacturing of the semiconductor device according to the embodiment will be described. FIG. 6 is a flowchart of the method for manufacturing a semiconductor device according to this embodiment, and FIGS. 7 and 8 are cross-sectional views of the semiconductor device according to this embodiment in the process of being manufactured.

In order to manufacture the semiconductor device according to the present embodiment, the two-layer plate 52 is formed according to the steps 1 to 8 shown in FIGS. 3A to 3E of the first embodiment. .

Then, a photosensitive resin is applied to the surface of the two-layer plate 52 by a method such as coating to form a photosensitive resin layer 80 (step 1b). Next, in the wiring pattern 41a on the two-layer board 52, as shown in FIG. 7F, electrode pads 41b, which are formed at positions corresponding to the electrodes of the semiconductor element,
.. are formed on the upper surface of the photosensitive resin layer 80 at positions corresponding to 41b. As a method of forming this plating hole, for example, the electrode pad 41
Masking at a position directly above b, 41b, ... (not shown)
Is formed (step 2b), exposed from above this masking (step 3b), and immersed in a solvent for development (step 4b).

By performing a plating process such as electrolytic plating or electroless plating on the photosensitive resin layer 80 having the plating holes 81 formed therein, the plating bumps 64, 64, ... As shown in FIG. Are formed (step 5b).
Next, as shown in FIG. 7I, the photosensitive resin layer 80
Are removed (step 6b), and the plated bumps 64, 64,
Expose ... Then, Ni plating (step 7b) is applied on the plating bumps 64, 64, ..., As shown in FIG.
A Ni layer 61 as a barrier metal layer is formed as shown in FIG. Then, Au plating (step 8b) is further applied thereon to form an Au layer 62 as shown in FIG. 7 (k).

Hereinafter, as in the first embodiment, A
The CF 63 and the semiconductor element 70 are aligned with each other as shown in FIG. 8 (l) (step 9b), and pressure is applied to the CF63 and the semiconductor element 70 in FIG. 8 (m).
It is mounted as shown in (step 10b). Then
As shown in FIG. 8 (n), the perforated prepreg 31 and the two-layer board 54 with bumps are aligned on it (step 11b). Next, heat pressing is performed in this state (step 12b). Thus, a so-called four-layer wiring type semiconductor device 70-embedded semiconductor device 1B as shown in FIG. 8 (O) is obtained.

According to the present embodiment, the semiconductor element 70 is mounted using the metal plated bumps 64, so that mounting can be performed more reliably.

(Third Embodiment) The third embodiment of the present invention will be described below.
Manufacturing of the semiconductor device according to the embodiment will be described. FIG. 9 is a flowchart of the method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 10 and 11 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.

In order to manufacture the semiconductor device according to this embodiment, the two-layer plate 52 is formed according to the steps 1 to 8 shown in FIGS. 1A to 1E of the first embodiment. .

Then, as shown in FIG.
The Cu layer 65 is formed on the surface of the layer plate 52 by attaching a metal plate such as a copper foil or a metal layer or by plating or the like (step 1c). Next, the wiring pattern 4 on the two-layer board 52
As shown in FIG. 10 (g), electrode pads 41b, 41 formed at the positions corresponding to the electrodes of the semiconductor element in 1a.
Masking 82, 82, ... Is formed on the upper surface of the Cu layer 65 at a position corresponding to b, ... (Step 2c).

Cu with masking 82, 82, ...
By performing an etching process on the layer 65, the structure shown in FIG.
Etching bumps 66, 6 as shown in FIG.
, 6 are formed (step 3c). Then, FIG.
As shown in (i), the masking 82, 82, ... Is removed (step 4c), and the etching bumps 66, 66 ,.
Expose. Next, the etching bumps 66, 66,
The Ni plating (step 5c) is applied on the top of Fig.
Ni layer 6 as a barrier metal layer as shown in (j)
1 is formed. Then, Au plating (step 6c) is applied from above to form the Au layer 6 as shown in FIG.
Form 2.

Thereafter, as in the first embodiment, the AC
The F63 and the semiconductor element 70 are aligned with each other as shown in FIG. 11 (l) (step 7c) and mounted by pressing (step 8c), and the perforated prepreg 31 and the two-layer board 54 with bumps are mounted thereon. By aligning (step 9c) and heat-pressing (step 10b), as shown in FIG.
A so-called four-layer wiring type semiconductor device 70-embedded semiconductor device 1C as shown in (O) is obtained.

According to the present embodiment, since the semiconductor element 70 is mounted using the metal etching bumps 66, the mounting can be performed more reliably.

(Fourth Embodiment) The fourth embodiment of the present invention will be described below.
The embodiment will be described. FIG. 12 is a flowchart of the semiconductor device manufacturing method according to the present embodiment.
FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment which is being manufactured. The semiconductor device according to the present embodiment employs a structure in which, in addition to the semiconductor element 70, a passive element 75 such as a capacitor or a resistor is mounted in the semiconductor device and then embedded.

To manufacture the semiconductor device according to this embodiment, the two-layer plate 51a is formed in the same manner as steps 1 to 8 of the first embodiment. Electrode pads 41c and 41c for mounting the passive element 75 are formed on the two-layer plate 51a. Using this two-layer plate 51a, a semiconductor device is formed through the same steps as steps 1a to 11a of the first embodiment (steps 1d to 11d). Among these steps, in the manufacturing method according to the present embodiment, when mounting the semiconductor element 70 in step 9d, the passive element 75 is also mounted via the electrode pads 41c and 41c.

Hereinafter, steps 9a to 1 of the first embodiment will be described.
Similar to 1a, the prepreg 32 is sandwiched and aligned (step 10d), and heat pressed (step 11).
In d), in the method according to this embodiment, the prepreg 32 is also provided with the opening 33 to accommodate the passive element 75. Therefore, in the finally obtained semiconductor device 1D, in addition to the semiconductor element 70, the passive element 75 is embedded inside.

In the semiconductor device 1D according to the present embodiment, not only the semiconductor element 70 but also the passive element 75 is included inside, and the surface of the two-layer plate is only exposed. Further, other wiring patterns, other elements and the like can be mounted, and a semiconductor device with a higher degree of integration can be obtained.

The present invention is not limited to the contents described in the above embodiment. For example, in the embodiment of the invention described above, the structure in which only one stage of the semiconductor element is built in the intermediate substrate of the so-called four-layer type multi-layer board having the wiring pattern of four layers has been described as an example. As shown in, the semiconductor element can be built in two steps inside a so-called 6-layer type multilayer board having a 6-layer wiring pattern.

[0048]

According to the present invention, a semiconductor element is housed in the opening of a core material insulating substrate precursor, and an insulating substrate is further stacked on the opening to completely cover the semiconductor element. It is possible to obtain a semiconductor device and a manufacturing method thereof, which have high reliability as a semiconductor device, such as high performance, and can form a wiring pattern on the entire surface of the multilayer board to improve the degree of integration.

[Brief description of drawings]

FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment.

FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment.

FIG. 3 is a sectional view of the semiconductor device according to the first embodiment in the process of being manufactured.

FIG. 4 is a sectional view of the semiconductor device according to the first embodiment in the process of being manufactured.

FIG. 5 is a sectional view of the semiconductor device according to the first embodiment in the process of being manufactured.

FIG. 6 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment.

FIG. 7 is a cross-sectional view of a semiconductor device in the process of being manufactured according to a second embodiment.

FIG. 8 is a cross-sectional view of a semiconductor device in the process of being manufactured according to the second embodiment.

FIG. 9 is a flowchart of a method for manufacturing a semiconductor device according to a third embodiment.

FIG. 10 is a cross-sectional view of a semiconductor device in the process of being manufactured according to a third embodiment.

FIG. 11 is a sectional view of a semiconductor device in the process of being manufactured according to a third embodiment.

FIG. 12 is a flowchart of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIG. 13 is a sectional view of a semiconductor device in the process of being manufactured according to a fourth embodiment.

FIG. 14 is a flowchart of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIG. 15 is a sectional view of a semiconductor device in the process of being manufactured according to a fourth embodiment.

FIG. 16 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 52 ... 2 layer board, 41a ... Wiring pattern, 41b ... Electrode pad, 60 ... Conductor bump (silver paste bump), 61 ... Ni layer (barrier metal layer), 62 ...
Au layer, 63 ... ACF, 30 ... Prepreg, 70 ... Semiconductor element, 71 ... Electrode plate.

Claims (9)

[Claims] 1. A two-layer conductor plate is patterned by wiring, in which an interlayer connecting member is inserted in a thickness direction of an insulating substrate and conductor plates electrically connected by the interlayer connecting member are provided on both surfaces. Forming a pattern and an electrode pad; forming a silver paste bump on the electrode pad; forming a barrier metal layer on the silver paste bump surface; and a weldable metal layer on the silver paste bump surface. A step of forming a semiconductor element on the silver paste bumps, an insulating substrate precursor in which a portion corresponding to the semiconductor element is opened, and a wiring pattern of a two-layer board on the two-layer board. A step of aligning a two-layer board with bumps provided with conductor bumps to the two-layer board, an insulating substrate precursor, and the two-layer board with bumps by heating under pressure to insulate the bumps. Insert into the substrate precursor Then, the step of electrically connecting the two-layer board and the two-layer board with bumps and curing the insulating substrate precursor is provided. 2. A step of forming a conductor bump on a predetermined position of one conductor plate; a step of superposing an insulating substrate precursor and another conductor plate on the conductor bump of the conductor plate; A plate, an insulating substrate precursor, and the other conductor plate are pressed under heating so that the conductor bump is inserted into the insulating substrate precursor, and the one conductor plate and the other conductor plate are electrically connected. A step of connecting, a step of patterning the one conductor plate and / or another conductor plate to form a wiring pattern and an electrode pad, a step of forming a silver paste bump on the electrode pad, the silver paste bump Forming a barrier metal layer on the surface; forming a weldable metal layer on the surface of the silver paste bump; mounting a semiconductor element on the silver paste bump; Semiconductor element equivalent part An insulating substrate precursor having an opening, and a step of aligning a two-layer plate with bumps, the two-layer plate, the insulating substrate precursor, and the two-layer plate with bumps under pressure by heating A step of inserting a bump into the insulating substrate precursor, electrically connecting the two-layer plate and the two-layer plate with bumps, and curing the insulating substrate precursor. Device manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the two-layer plate forms a conductor bump on the conductor plate, and an insulating substrate precursor is formed on the conductor bump. A step of stacking a body and another conductor plate, and pressing the stacked conductor plate, the insulating substrate precursor, and the other conductor plate under heating so that the conductor bump penetrates the insulating substrate precursor. And a step of curing the insulating substrate precursor together with a step of manufacturing the insulating substrate precursor. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the barrier metal layer is N.
A method for manufacturing a semiconductor device, which is an i-layer, wherein the weldable metal is Au. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the conductor bump forms the conductor bump with a conductive paste using a printing technique. A method for manufacturing a semiconductor device, which is a process. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the conductor bump is performed by depositing a plating metal on the surface of the support base. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the conductor bumps forms the conductor bumps by etching the surface of the supporting substrate. A method of manufacturing a semiconductor device, comprising: 8. A first substrate on which an interlayer connecting member is inserted, a second substrate laminated on the first substrate and inserting an interlayer connecting member, and on the second substrate. A third substrate laminated and having an interlayer connection member inserted therethrough; a first wiring pattern provided on an outer surface of the first substrate; and the first substrate and the second substrate. A second wiring pattern and an electrode pad arranged between them; a semiconductor element included in the second substrate and mounted on the electrode pad; the second substrate and the third substrate; A semiconductor device comprising: a third wiring pattern disposed between the first wiring pattern and a third wiring pattern disposed on the outer surface of the third substrate. 9. A first substrate having an interlayer connecting member inserted therethrough, a second substrate laminated on the first substrate, having an interlayer connecting member inserted therethrough, and a second substrate provided on the second substrate. A third substrate laminated and having an interlayer connecting member inserted therein; a fourth substrate laminated on the third substrate and having an interlayer connecting member inserted therethrough; laminated on the fourth substrate. A fifth substrate having an interlayer connecting member inserted therethrough, a first wiring pattern provided on an outer surface of the first substrate, and between the first substrate and the second substrate. A second wiring pattern and a first electrode pad arranged, a first semiconductor element included in the second substrate and mounted on the first electrode pad, and the second substrate And a third wiring pattern arranged between the third substrate and the third substrate, and arranged between the third substrate and the fourth substrate A formed fourth wiring pattern and a second electrode pad, a second semiconductor element included in the fourth substrate and mounted on the second electrode pad, the fourth substrate and the A semiconductor device comprising: a fifth wiring pattern provided between the fifth substrate and the fifth substrate; and a sixth wiring pattern provided on an outer surface of the fifth substrate.