JP2004012995A - Image display device - Google Patents

Abstract

Provided is an image display device capable of realizing enlarged display quickly and with low power consumption, and being mountable on a small device.
A control circuit (23) changes the frequency of a line buffer read clock (RCK) of a digital video signal (DATA) stored in a first line buffer during a certain horizontal scanning period to a digital value stored in the first line buffer (21). The frequency of the start clock S_CK as a transfer clock for transferring the video signal DATA to the display unit 10 is set to be 1 / n (n> 1). As a result, the same digital video signal DATA is transferred to the display unit 10 continuously n times, and the image can be enlarged n times in the horizontal direction (horizontal direction).
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital image display device that inputs a digital signal as a video signal and displays an image.
[0002]
[Prior art]
Conventionally, enlarged display in a digital image display device is not performed on the image display device side, but is performed by a graphics controller or CPU in an external signal source (for example, a personal computer) by program processing.
[0003]
For example, in a personal computer, as shown in FIG. 10, when (1) an enlargement command is input to a graphics controller or CPU, (2) data in VRAM is enlarged, and (3) data after the enlargement processing is Enlarged display was performed by outputting to an image display device.
[0004]
Japanese Patent Application Laid-Open No. Hei 6-259219 discloses a technique of adding hardware for performing reduced display, panning display, enlarged display, mixed display, and the like between a host CPU and a panel display, so that the image display device can perform enlarged display. A technique for performing the display processing of (1) is disclosed.
[0005]
[Problems to be solved by the invention]
However, in the technique shown in FIG. 10, since the enlargement processing is performed by the graphics controller or the CPU by the program processing, there is a problem that it takes time to display the enlarged image on the image display device.
[0006]
In addition, since the graphics controller and the CPU continue to be driven while the program processing is being performed, there is a problem that the longer the processing time, the higher the power consumption.
[0007]
Therefore, in order to reduce the program processing time, it is conceivable to improve the performance of the graphics controller and the CPU, but it is not possible to improve the performance to justify the price.
[0008]
As described above, even if the performance of the graphics controller and CPU is improved, as long as the enlarged display is performed by the program processing, only the price rises, and the time required for display is greatly reduced, and the power consumption is significantly reduced. Can not be planned.
[0009]
On the other hand, in the technique disclosed in Japanese Patent Application Laid-Open No. 6-259219, processing such as enlarged display is performed on the image display device side, but the image display device has a large scale having a frame memory in the image display device. Therefore, there arises a problem that it is not suitable for mobile applications in recent years such as simplicity, high-speed response, and low power consumption, that is, it is not suitable for mounting on small devices.
[0010]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an image display device that can realize enlarged display quickly and with low power consumption and can be mounted on a small device. is there.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, an image display device according to the present invention includes an image display unit that performs image display by inputting a digital video signal as display data, and an external digital video signal source for one horizontal scanning period. Storage means for storing display data of n (n> 1) of the display data; and n (n> 1) of display data for each horizontal scanning period of the digital video signal source. And control means for reading the display data stored in the other storage means and transferring the display data to the image display unit, wherein the control means stores the display data in the storage means in the storage means. The read clock frequency of the stored display data is set to be 1 / n (n> 1) of the transfer clock frequency of the display data stored in the storage means to the image display unit. That.
[0012]
According to the above configuration, the read clock frequency of the display data stored in the storage means is set to 1 / n (n> 1) of the transfer clock frequency of the display data stored in the storage means to the image display unit. By setting such that, the display data of 1 / n of the display data in one horizontal scanning period of the external digital video signal source stored in the storage means is continuously sent to the image display unit n times. Will be transferred. As a result, the image can be enlarged n times in the horizontal direction (lateral direction). Hereinafter, the horizontal direction of the image will be described as the horizontal direction, and the vertical direction will be described as the vertical direction.
[0013]
In this way, simply changing the read clock frequency of the display data stored in the storage means with respect to the transfer clock frequency to the image display unit can easily display an enlarged image, here, an enlarged image in the horizontal direction. It can be performed.
[0014]
Therefore, unlike the related art, it is not necessary to perform the enlarged display by the program processing, so that the enlarged image can be displayed at high speed and with low power consumption without burdening the external signal source (a personal computer or the like).
[0015]
Further, since the storage means stores only 1 / n of the display data in one horizontal scanning period, the storage capacity of the storage means may be small. In other words, a small storage unit such as a line buffer capable of storing display data for one horizontal scanning period, that is, one line of display data is sufficient.
[0016]
Therefore, unlike the related art, a large memory such as a frame memory for storing display data of the entire display screen is not required, so that the size of the image display device can be reduced. It can be mounted.
[0017]
Further, the image display unit includes a plurality of signal lines, a plurality of scanning lines arranged orthogonal to the signal lines, and a data signal for generating a drive signal to be applied to each signal line based on input display data. A line driving circuit and a scanning signal line driving circuit for generating a driving signal for selecting each scanning line, wherein the scanning signal line driving circuit can simultaneously select n (n> 1) scanning lines A drive signal may be generated.
[0018]
In this case, the scanning signal line driving circuit generates a driving signal capable of simultaneously selecting n (n> 1) scanning lines, so that the scanning lines can be selected n rows at a time, and the image is displayed in the vertical direction. Can be magnified n times.
[0019]
Therefore, in the configuration of claim 1, since the image is enlarged n times in the horizontal direction, a display image enlarged twice in the vertical and horizontal directions can be obtained.
[0020]
Further, in an image display device including an image display unit that performs image display by inputting a digital video signal as display data, the image display unit includes a plurality of signal lines and a plurality of signal lines orthogonal to the signal lines. Signal line drive circuit for generating a drive signal to be applied to each signal line based on input scan data, and a scan signal line drive circuit for generating a drive signal for selecting each scan line And the scanning signal line driving circuit may generate a driving signal capable of simultaneously selecting n (n> 1) scanning lines.
[0021]
In this case, the scanning signal line driving circuit generates a driving signal capable of simultaneously selecting n (n> 1) scanning lines, so that the scanning lines can be selected n rows at a time, and the image is displayed in the vertical direction. Can be magnified n times.
[0022]
Moreover, the image can be enlarged n times in the vertical direction by simply selecting n scanning lines at the same time by the scanning line driving circuit, so that it is not necessary to perform the enlarged display by the program processing as in the related art. . Therefore, it is possible to enlarge and display an image at high speed and with low power consumption without burdening an external signal source (a personal computer or the like).
[0023]
Furthermore, the data signal line driving circuit may be stopped for a period of (n-1) for n of one vertical / horizontal period.
[0024]
In this case, the data signal line drive circuit is stopped for n (n-1) periods of one vertical scanning period, so that power consumption can be reduced accordingly.
[0025]
Note that the scanning signal line driving circuit can finish updating the entire screen in one-nth of one vertical scanning period, so that the (n-1) th of one vertical scanning period, Even if the data signal line drive circuit stops, no problem occurs in image display.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below. In this embodiment, a liquid crystal display device that inputs digital video signals and performs image display will be described as an example of an image display device. It doesn't matter. For example, the same applies to a display device using a display element such as an organic EL (Electro Luminescence).
[0027]
As shown in FIG. 1, the liquid crystal display device according to the present embodiment has a configuration including a display unit 10 for displaying an image and a signal processing unit 20 for processing a signal supplied to the display unit 10. I have.
[0028]
The display unit 10 is formed of an active matrix type liquid crystal panel using a TFT (Thin Film Transistor) as a switching element of pixels arranged in a matrix, and a source driver (data signal line driving) for driving the liquid crystal panel. A circuit) 11 and a gate driver (scanning signal line driving circuit) 12, and a signal processed by the signal processing unit 20 is input to each of these drivers.
[0029]
The digital video signal DATA, start signal S_SP, clock signal S_CK, and POWER_SAVE signal transmitted from the signal processing unit 20 are input to the source driver 11.
[0030]
The source driver 11 stores the digital video signal DATA for one horizontal scanning period, converts the digital video signal DATA into an analog signal, and converts the digital video signal DATA into an analog signal by a voltage follower to each data signal line SLi (not shown) in the display unit 10. ).
[0031]
On the other hand, the start signal G_SP and the clock signal G_CK sent from the signal processing unit 20 are input to the gate driver 12.
[0032]
The gate driver 12 sequentially selects a scanning signal line GLi (not shown) in the display unit 10 in synchronization with a timing signal such as a clock signal G_CK and controls opening and closing of a switching element in a pixel. As a result, the video signal written to each data signal line SLi is written to each pixel and is held by each pixel.
[0033]
The gate driver 12 can select n (n> 1) scanning signal lines GL simultaneously. For example, when the image is enlarged twice in the vertical direction of the image, the gate driver 12 simultaneously selects two scanning signal lines GL. When the image is enlarged n times in the vertical direction of the image, the gate driver 12 simultaneously selects n scanning signal lines GL. The simultaneous selection control of the scanning signal lines of the gate driver 12 is performed by a control circuit (not shown).
[0034]
The signal processing unit 20 includes two line buffers (a first line buffer 21 and a second line buffer 22) for storing digital video signals DATA as video signals from an external signal source 30 as line data, and each line buffer. And a switch circuit (a first switch circuit 24 and a second switch circuit 25).
[0035]
Each of the first line buffer 21 and the second line buffer 22 is configured to store one (n> 1) digital video signal DATA in one horizontal scanning period.
[0036]
Then, the dot clock WCK1, the write enable signal WE1, the read enable signal RE1, and the line buffer read clock RCK1 sent from the control circuit 23 are input to the first line buffer 21, and stored based on each signal. The read digital video signal DATA is read.
[0037]
On the other hand, the dot clock WCK2, the write enable signal WE2, the read enable signal RE2, and the line buffer read clock RCK2 sent from the control circuit 23 are input to the second line buffer 22, and stored based on each signal. The read digital video signal DATA is read.
[0038]
The first line buffer 21 and the second line buffer 22 are connected to one another while storing the digital video signal DATA, that is, while receiving the digital video signal DATA, while the other is storing the digital video signal DATA. Is transmitted (transmitted) to the display unit 10.
[0039]
For example, while the digital video signal DATA transmitted from the external signal source 30 is stored in the first line buffer 21, the digital video signal DATA stored in the second line buffer 22 is transmitted to the display unit 10. Has become.
[0040]
At this time, the switching of the path through which the digital video signal DATA flows is performed by the first switch circuit 24 and the second switch circuit 25.
[0041]
The first switch circuit 24 is a switch circuit for switching the transfer of the digital video signal DATA from the external signal source 30 to the first line buffer 21 or the second line buffer 22. The circuit 25 is a switch circuit that switches which of the first line buffer 21 and the first switch circuit 24 sends the DATA signal stored therein.
[0042]
The first switch circuit 24 is controlled by a read switch control signal RSW sent from the control circuit 23, and the second switch circuit 25 is controlled by a write switch control signal WSW sent from the control circuit 23. Is done.
[0043]
The control circuit 23 receives the dot clock WCK, the horizontal synchronizing signal HSYN, and the vertical synchronizing signal VSYN sent from the external signal source 30, and generates the control signals described above.
[0044]
In the liquid crystal display device having the above-described configuration, enlargement can be performed n times (n> 1) in each of the vertical and horizontal directions, and the area to be enlarged can be obtained from an arbitrary position. In the present embodiment, a case will be described in which n = 2, that is, the area of the upper left quarter of the image is enlarged and displayed at twice the vertical and horizontal directions. The enlargement of n ≧ 3 or an arbitrary area can be realized by changing the length and start position of data to be written in the first line buffer 21 and the second line buffer 22 and delaying the read clock.
[0045]
Here, a write operation and a read operation of the digital video signal DATA of the first line buffer 21 at the time of enlarged display will be described below with reference to FIGS.
[0046]
The switching of the first switch circuit 24 and the second switch circuit 25 is controlled based on the timing chart shown in FIG. For example, when the read switch control signal RSW for controlling the switching of the first switch circuit 24 is at a high level, switching is performed so that the digital video signal DATA can be stored in the first line buffer 21, and when the read switch control signal RSW is at a low level. , So that the digital video signal DATA is stored in the second line buffer 22, and when the write switch control signal WSW for controlling the switching of the second switch circuit 25 is at a high level, the data is stored in the second line buffer 22. When the write switch control signal WSW is at a low level, the digital video signal DATA stored in the first line buffer 21 is switched to be read.
[0047]
It should be noted that the polarity of the read switch control signal RSW and the polarity of the write switch control signal WSW are inverted every horizontal scanning period. That is, the writing and reading of the digital video signal DATA in each line buffer are switched every one horizontal period.
[0048]
From the above, in one horizontal scanning period, the first line buffer 21 performs the writing operation of the digital video signal DATA, and the second line buffer 22 performs the reading operation of the digital video signal DATA. In the next one horizontal scanning period, the first line buffer 21 performs the reading operation of the digital video signal DATA. The one line buffer 21 performs a read operation of the digital video signal DATA, and the second line buffer 22 performs a write operation of the digital video signal DATA.
[0049]
Next, a write operation and a read operation of the digital video signal DATA of the first line buffer 21 will be described with reference to timing charts shown in FIGS.
[0050]
FIG. 2 is a timing chart showing the operation of writing the digital video signal DATA to the first line buffer 21 during one horizontal scanning period. In this timing chart, one horizontal scanning period is n periods of the dot clock WCK1 sent from the control circuit 23.
[0051]
As shown in the timing chart of FIG. 2, by setting the write enable signal WE1 sent from the control circuit 23 to the first line buffer 21 to a high level during the first half of one horizontal scanning period, the first The line buffer 21 is controlled so that only the first half of the digital video signal DATA is written.
[0052]
FIG. 3 is a timing chart showing a read operation of the digital video signal DATA from the first line buffer 21 in one horizontal scanning period following one horizontal scanning period shown in FIG. In this timing chart, one horizontal scanning period is n cycles of the transfer clock OUTCK transferred from the control circuit 23 to the display unit 10 as the clock signal S_CK. The transfer clock OUTCK is controlled so that the clock frequency from the external signal source 30 remains unchanged.
[0053]
As shown in the timing chart of FIG. 3, the control circuit 23 controls the line buffer read clock RCK1 so as to be a half cycle of the transfer clock OUTCK. Therefore, the same digital video signal DATA is continuously transmitted twice to the source driver 11 of the display unit 10, and the image is enlarged twice in the horizontal direction.
[0054]
In parallel with the transmission processing of the digital video signal DATA to the source driver 11, the gate driver 12 selects two scanning signal lines GLi at a time, as shown in FIG. Thus, by selecting two scanning signal lines GLi at a time, the image is enlarged twice in the vertical direction of the image.
[0055]
According to the timing chart shown in FIG. 5, since two i = V scanning signal lines GL are selected, updating of one screen is completed in half of one vertical scanning period (V period of the clock signal G_CK). Will do.
[0056]
Therefore, during the other half of one vertical search period, by setting the POWER_SAVE signal sent to the source driver 11 to a high level, the source driver 11 can be stopped and power consumption can be reduced. it can.
[0057]
Note that the operation of writing and reading the digital video signal DATA in the second line buffer 22 is performed only at a timing opposite to the operation of writing and reading the digital video signal DATA in the first line buffer 21 described above. This is the same as the first line buffer 21.
[0058]
Here, a write operation and a read operation of the digital video signal DATA of the first line buffer 21 at the time of the normal display will be described below with reference to FIGS.
[0059]
The switching of the first switch circuit 24 and the second switch circuit 25 is controlled based on the timing chart shown in FIG. This is the same as the timing chart shown in FIG. 4 for the above-described enlarged display processing. For example, when the read switch control signal RSW for controlling the switching of the first switch circuit 24 is at a high level, switching is performed so that the digital video signal DATA can be stored in the first line buffer 21, and when the read switch control signal RSW is at a low level. , So that the digital video signal DATA is stored in the second line buffer 22, and when the write switch control signal WSW for controlling the switching of the second switch circuit 25 is at a high level, the data is stored in the second line buffer 22. When the write switch control signal WSW is at a low level, the digital video signal DATA stored in the first line buffer 21 is switched to be read.
[0060]
It should be noted that the polarity of the read switch control signal RSW and the polarity of the write switch control signal WSW are inverted every horizontal scanning period. That is, the writing and reading of the digital video signal DATA in each line buffer are switched every one horizontal period.
[0061]
From the above, in one horizontal scanning period, the first line buffer 21 performs the writing operation of the digital video signal DATA, and the second line buffer 22 performs the reading operation of the digital video signal DATA. The one line buffer 21 performs a read operation of the digital video signal DATA, and the second line buffer 22 performs a write operation of the digital video signal DATA.
[0062]
Next, a write operation and a read operation of the digital video signal DATA of the first line buffer 21 will be described with reference to timing charts shown in FIGS.
[0063]
FIG. 6 is a timing chart showing the operation of writing the digital video signal DATA to the first line buffer 21 during one horizontal scanning period. In this timing chart, one horizontal scanning period is n periods of the dot clock WCK1 sent from the control circuit 23.
[0064]
As shown in the timing chart of FIG. 6, by setting the write enable signal WE1 sent from the control circuit 23 to the first line buffer 21 to the high level during one horizontal scanning period, the digital video is stored in the first line buffer 21. Control is performed so that one line of the signal DATA is written.
[0065]
FIG. 7 is a timing chart showing a read operation of the digital video signal DATA from the first line buffer 21 in one horizontal scanning period following one horizontal scanning period shown in FIG. In this timing chart, one horizontal scanning period is n cycles of the transfer clock OUTCK transferred from the control circuit 23 to the display unit 10 as the clock signal S_CK. The transfer clock OUTCK is controlled so that the clock frequency from the external signal source 30 remains unchanged.
[0066]
As shown in the timing chart of FIG. 7, the control circuit 23 controls the line buffer read clock RCK1 to have the same cycle as the transfer clock OUTCK. Therefore, since the same digital video signal DATA is sent only once to the source driver 11 of the display unit 10, the image is not enlarged in the horizontal direction.
[0067]
In parallel with the process of sending the digital video signal DATA to the source driver 11, the gate driver 12 selects one scanning signal line GLi as shown in FIG. As described above, by selecting the scanning signal lines GLi one by one, the image is not enlarged in the vertical direction of the image.
[0068]
Therefore, as in the case of the above-described enlarged display processing, scanning by the gate driver 12 is performed not for a half period of one vertical scanning period but for the entire period, so that the POWER_SAVE signal to the source driver 11 remains at a low level. It becomes.
[0069]
Note that the operation of writing and reading the digital video signal DATA in the second line buffer 22 is performed only at a timing opposite to the operation of writing and reading the digital video signal DATA in the first line buffer 21 described above. This is the same as the first line buffer 21.
[0070]
As described above, the image display device of the present invention includes the display unit 10 that is an image display unit that performs image display by inputting a digital video signal as display data (digital video signal DATA), and an external digital video signal. A first line buffer 21 and a second line buffer, which are two storage units, for storing display data of one-nth (n> 1) of display data of one horizontal scanning period of the external signal source 30 as a source. 22 and one display data of n (n> 1) of the display data is stored in one line buffer and stored in the other line buffer every one horizontal scanning period of the external signal source 30. And a control circuit 23 for reading the displayed display data and transferring the display data to the image display unit. The frequency of the line buffer read clock RCK, which is the read clock frequency of the display data, is set to n (n> 1) of the frequency of the transfer clock OUTCK of the display data stored in the line buffer to the display unit 10. It is set to be 1.
[0071]
Therefore, the frequency of the line buffer read clock RCK of the display data stored in each line buffer is set to n (n> 1) of the frequency of the transfer clock OUTCK of the display data stored in the line buffer to the display unit 10. By setting the display data to be 1/1, the display data of 1 / n of the display data of the external signal source 30 stored in the line buffer during one horizontal scanning period is sent to the display unit 10 n times. It will be transferred continuously. Thereby, the image can be enlarged n times in the horizontal direction.
[0072]
As described above, by simply changing the frequency of the line buffer read clock RCK of the display data stored in the line buffer with respect to the frequency of the transfer clock OUTCK to the display unit 10, enlarged display of an image can be easily performed. Here, a horizontal enlarged display can be performed.
[0073]
Therefore, unlike the related art, it is not necessary to perform the program processing for the enlarged display, so that the enlarged display of the image can be performed at high speed and with low power consumption without burdening the external signal source (a personal computer or the like).
[0074]
Further, since the line buffer stores only 1 / n of the display data in one horizontal scanning period, the storage capacity of the line buffer may be small. In other words, a line buffer capable of storing display data for one horizontal scanning period, that is, display data for one line is sufficient.
[0075]
Therefore, unlike the related art, a large memory such as a frame memory for storing display data of the entire display screen is not required, so that the size of the image display device can be reduced. It can be mounted.
[0076]
Further, the gate driver 12, which is a scanning signal line driving circuit in the display section 10, generates a driving signal capable of simultaneously selecting n (n> 1) scanning signal lines GL. The signal lines can be selected n rows at a time, and the image can be enlarged n times in the vertical direction.
[0077]
Therefore, as described above, since the image is enlarged n times in the horizontal direction, a display image enlarged twice in the vertical and horizontal directions can be obtained.
[0078]
Moreover, the number of scanning signal lines GL that can be simultaneously selected by the gate driver 12 may be set regardless of the horizontal magnification of the image.
[0079]
For example, even if the frequency of the read clock (line buffer read clock RCK) of the digital video signal DATA from the line buffer is the same as the frequency of the transfer clock OUTCK to the display unit 10, that is, even if the image is not enlarged in the horizontal direction, The image may be enlarged only in the vertical direction.
[0080]
As described above, if the horizontal and vertical magnifications of an image are individually set, the image can be displayed with different horizontal and vertical magnifications, and the degree of freedom in enlarged display of the image is increased.
[0081]
Further, the image display device of the present invention may be configured as follows.
[0082]
That is, the image display device of the present invention is a digital image display device that receives a digital video signal as an input, and stores a line for storing 1 / n of data in one horizontal scanning period of an external digital video signal source. A display data processing circuit comprising two buffers, two switch circuits for switching the two line buffers between reception and transmission, and a control circuit for controlling the two line buffers and the two switches And a configuration having a scanning signal line driving circuit capable of simultaneously selecting up to n scanning signal lines.
[0083]
In this case, a line buffer that stores 1 / n of data in one horizontal scanning period stores 1 / n of data from a desired position in one horizontal scanning period from an external digital video signal source. The line buffer is switched for data output to the source driver in the next one horizontal scanning period by the switch circuit, and the other line buffer 2 is switched for data reception from the external digital video signal source by the switch circuit. . The line buffer 1 switched for output is controlled by the control circuit so that the read clock frequency from the buffer is 1 / n and the transfer clock frequency to the source driver remains the same as the clock frequency from the external signal source. Is passed to the source driver n times successively, whereby the image is enlarged n times in the horizontal direction.
[0084]
In addition, the gate driver opens the gates of the pixel TFTs simultaneously by n rows, whereby the image is magnified n times in the vertical direction.
[0085]
Further, the rewriting time of the entire screen may be reduced to 1 / n by simultaneously writing pixels in n rows, and the power consumption may be reduced by setting the source driver in a rest state for the remaining time.
[0086]
As described above, by using the image display device according to the present invention, it is possible to realize an image display device capable of high-speed n-times enlarged display with low power consumption without imposing a load on an external signal source.
[0087]
In addition, the signal processing unit 20 necessary for enlarged display includes only the first line buffer 21, the second line buffer 22, the control circuit 23, the first switch circuit 24, and the second switch circuit 25. The image display device can be easily mounted on the unit 10 and has a small-sized enlarged display function.
[0088]
Therefore, the image display device can be suitably used for a small device, for example, an image display device such as a mobile phone, a portable personal computer, and an electronic organizer.
[0089]
【The invention's effect】
As described above, the image display device of the present invention includes an image display unit that performs image display by inputting a digital video signal as display data, and an external digital video signal source, which includes display data of one horizontal scanning period. , N (n> 1) of display data, and display data of n (n> 1) of display data for each horizontal scanning period of the digital video signal source. And control means for reading the display data stored in the other storage means and transferring the display data to the image display unit, wherein the control means stores the display data stored in the storage means. The data read clock frequency is set so as to be 1 / n (n> 1) of the transfer clock frequency of the display data stored in the storage means to the image display unit.
[0090]
Therefore, by simply changing the read clock frequency of the display data stored in the storage means with respect to the transfer clock frequency to the image display unit, the enlarged display of the image, in this case, the enlarged display in the horizontal direction can be easily performed. It can be carried out.
[0091]
Therefore, unlike the related art, it is not necessary to perform the enlarged display by the program processing, so that the enlarged image can be displayed at high speed and with low power consumption without burdening the external signal source (a personal computer or the like).
[0092]
Further, since the storage means stores only 1 / n of the display data in one horizontal scanning period, the storage capacity of the storage means may be small. In other words, a small storage unit such as a line buffer capable of storing display data for one horizontal scanning period, that is, one line of display data is sufficient.
[0093]
Therefore, unlike the related art, a large memory such as a frame memory for storing display data of the entire display screen is not required, so that the size of the image display device can be reduced. It has the effect that it can be mounted.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically illustrating an image display device according to an embodiment of the present invention.
FIG. 2 is a timing chart showing a digital video signal writing operation during enlarged display in a first line buffer of the image display device shown in FIG. 1;
3 is a timing chart showing a read operation of a digital video signal at the time of enlarged display in a first line buffer of the image display device shown in FIG. 1;
FIG. 4 is a timing chart showing a switching operation between a first switch circuit and a second switch circuit of the image display device shown in FIG.
FIG. 5 is a timing chart of input / output signals during enlarged display in the gate driver shown in FIG. 1;
FIG. 6 is a timing chart showing a digital video signal writing operation during normal display in a first line buffer of the image display device shown in FIG. 1;
FIG. 7 is a timing chart showing a read operation of a digital video signal during normal display in a first line buffer of the image display device shown in FIG. 1;
8 is a timing chart showing a switching operation between a first switch circuit and a second switch circuit of the image display device shown in FIG.
FIG. 9 is a timing chart of input / output signals during normal display in the gate driver shown in FIG. 1;
FIG. 10 is a schematic block diagram showing a flow of an enlargement process of a conventional image display device.
[Explanation of symbols]
10. Display unit (image display unit)
11 Source driver (data signal line drive circuit)
12 gate driver (scanning signal line drive circuit)
20 signal processing unit
21 1st line buffer (storage means)
22 Second line buffer (storage means)
23 control circuit (control means)
24 1st switch circuit
25 Second switch circuit
30 signal source (digital video signal source)
DATA Digital video signal
G_CK clock signal
G_SP start signal
GL scanning signal line
HSYN horizontal sync signal
OUTCK transfer clock
RCK Line buffer read clock
RE read enable signal
RSW Reed switch control signal
S_CK clock signal
S_SP start signal
SL data signal line
TFT pixel
VSYN vertical sync signal
WCK dot clock
WE light enable signal
WSW light switch control signal

Claims (5)

An image display unit that performs image display by inputting a digital video signal as display data,
Storage means for storing 1 / n (n> 1) of display data of one horizontal scanning period of an external digital video signal source;
For each horizontal scanning period of the digital video signal source, one of n (n> 1) display data out of the display data is stored in one storage means, and the display data stored in the other storage means is stored. Control means for reading and transferring to the image display unit,
The control means sets the read clock frequency of the display data stored in the storage means to 1 / n (n> 1) of the transfer clock frequency of the display data stored in the storage means to the image display unit. An image display device, wherein the setting is made to be as follows. The image display unit includes a plurality of signal lines, a plurality of scanning lines orthogonal to the plurality of signal lines, and a data signal line driving unit that generates a driving signal to be applied to each signal line based on input display data. Circuit, and a scanning signal line driving circuit for generating a driving signal for selecting each scanning line,
2. The image display device according to claim 1, wherein the scanning signal line driving circuit generates a driving signal capable of simultaneously selecting n (n> 1) scanning lines. In an image display device including an image display unit that performs image display by inputting a digital video signal as display data,
The image display unit includes a plurality of signal lines, a plurality of scanning lines orthogonal to the signal lines, and a data signal line driving unit that generates a driving signal to be applied to each signal line based on input display data. A circuit, and a scanning signal line driving circuit that generates a driving signal for selecting each scanning line,
The image display device, wherein the scanning signal line driving circuit generates a driving signal capable of simultaneously selecting n (n> 1) scanning lines. 4. The image display device according to claim 2, wherein the data signal line driving circuit stops for n (n−1) of one vertical / horizontal period. 5. 5. The image display device according to claim 1, wherein a line buffer is used for the storage unit.

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