JP2004120366A - Image processing apparatus and image processing method - Google Patents

Abstract

An image processing apparatus and an image processing method capable of performing correction without increasing a circuit scale.
A first bit to be corrected, which is obtained by extracting an upper bit of a predetermined bit width based on an input image signal, includes a second bit to be corrected that is larger by a predetermined bit corresponding to the predetermined bit width. An addition and overflow processing unit 421 for generating and outputting, a memory 423 for storing a look-up table (LUT), a FF 422 for timing adjustment, a bit to be corrected as a lower bit of the input signal output from the FF 422, An interpolation calculation unit 424 for performing an interpolation process based on the two correction value data output from the 423 is provided.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, an image processing apparatus that performs an image signal correction process, and an image processing method.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for example, in an image processing apparatus, as a circuit for performing correction of an image signal, for example, gamma correction, a correction circuit that performs correction based on a look-up table (hereinafter referred to as an LUT) or a break point correction using a digital circuit is known. (See, for example, Patent Document 1).
[0003]
In recent years, the LUT-type digital correction circuit is becoming mainstream in recent years because of its high correction accuracy.
[0004]
[Patent Document 1]
JP 2001-320607 A
[0005]
[Problems to be solved by the invention]
In the above-described conventional LUT type digital correction circuit, a memory having 2 ＾ n memory addresses is used as the LUT, where n is the number of quantization bits of the input signal. Gamma correction value data corresponding to the input signal level is stored in the LUT, and gamma correction is performed in consideration of the transmittance characteristic (VT characteristic) with respect to the applied voltage of the image display device.
[0006]
However, as the resolution for quantizing the input signal level increases, the size of the memory used for this LUT increases.
For example, when the number of quantization bits at the input signal level is 10 bits, the capacity required for the memory used for the LUT is 1024 words, and when the number of quantization bits at the input level is 12 bits, 4096 words is required.
[0007]
As described above, when the 1-bit resolution increases, the memory capacity increases twice. Accordingly, there has been a problem that the circuit scale increases, the power consumption increases, and the update time of the gamma correction value data stored in the memory increases.
[0008]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an image processing apparatus and an image processing method capable of performing correction without increasing the circuit scale.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, an image processing apparatus according to a first aspect of the present invention is an image processing apparatus for performing a correction process on an image signal composed of a plurality of bits, and performs table conversion of bits to be corrected in the image signal. Storage means for storing correction value data, and first correction value data table-converted by the storage means based on the first bit to be corrected in the input image signal; and the first bit to be corrected. The second correction value data table-converted by the storage unit based on the second bit to be corrected which is larger than the second bit to be corrected, and the remaining bits to be interpolated by removing the bit to be corrected from the input image signal. Interpolating means for performing interpolation processing to generate third correction value data for the input image signal.
[0010]
According to the image processing apparatus of the first invention, a correction process of an image signal including a plurality of bits is performed.
The storage unit stores correction value data for converting a bit to be corrected in the image signal into a table.
In the interpolation means, the first correction value data table-converted by the storage means based on the first bit to be corrected in the input image signal, the second correction value larger than the first bit to be corrected. The second correction value data table-converted by the storage means on the basis of the input bits, and the remaining interpolated bits obtained by removing the bits to be corrected from the input image signal, perform interpolation processing on the input image signal. 3 is generated.
[0011]
Further, in order to achieve the above object, the image processing method according to the second aspect of the present invention converts a bit to be corrected in an image signal composed of a plurality of bits into a table based on preset correction value data, and An image processing method for an image processing apparatus that performs signal correction processing, wherein the table conversion is performed based on a first bit to be corrected in an input image signal to generate first correction value data, and the first correction value data is generated. Converts the table based on a second bit to be corrected larger than one bit to be corrected to generate second correction value data, and generates the first and second correction value data and the input image signal. Then, based on the remaining bits to be interpolated except for the bits to be corrected, interpolation processing is performed to generate third correction value data for the input image signal.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
An image processing apparatus according to the present invention generates a correction value based on a look-up table for correcting an image signal, and further performs an interpolation process on the correction value to generate a correction value of the image signal.
Hereinafter, an embodiment of an image processing apparatus according to the present invention will be described with reference to the drawings.
First embodiment
An image processing apparatus according to a first embodiment of the present invention is an image processing apparatus using a display device such as a liquid crystal which makes a nonlinear optical response to an input signal level of an image signal. The correction value generated based on the up table and the input image signal and the lookup table is interpolated by a linear correction function.
More specifically, in order to match the image signal with the characteristics of the output device, gamma correction is performed using a lookup table smaller than the required amount and an interpolation function for interpolating the data lacking the required amount.
[0013]
Hereinafter, a front / rear projector system using an LCD panel employing the correction circuit of the image processing apparatus according to the present embodiment will be described.
FIG. 1 is a functional block diagram of an embodiment of an image processing apparatus according to the present invention. As shown in FIG. 1, the image processing apparatus 1 includes an A / DPLL 2, a scan converter (Scan @ Converter) 3, a signal processing unit 4, a sample / hold driver (S / H @ Driver) 5, an LCD panel 6, and a reference clock ( (Crystal: XTL) 7.
[0014]
In the image processing apparatus 1, for example, the input / output of the signal processing unit 4 is 12 bits, the input of the S / H driver 5 is 12 bits, the output is 6 bits, and the input of the LCD panel 6 is 12 bits.
[0015]
The A / DPLL 2 performs, for example, A / D conversion processing on the input analog video signal to generate a digital signal, and outputs the digital signal to the scan converter 3.
[0016]
The A / DPLL 2 performs A / D conversion based on, for example, an analog video signal R (Red （) signal, G (Green) signal, B (Blue) signal, horizontal synchronization signal (HSYNC), and vertical synchronization signal (VSYNC). After processing, for example, an 8-bit R signal, G signal, and B signal are output to the scan converter 3 as digital signals.
Further, the A / DPLL 2 outputs a horizontal synchronization signal (HSYNC #) and a vertical synchronization signal (VSYNC #) to the scan converter 3.
[0017]
The scan converter 3 performs a scaling and dithering process based on the digital signal output from the A / DPLL 2 to generate a 12-bit digital signal, and outputs the digital signal to the signal processing unit 4.
[0018]
The scan converter 3 outputs an output from the A / DPLL 2 based on, for example, a reference clock signal output from the reference clock (XTL) 7, a horizontal synchronization signal (HSYNC #) output from the A / DPLL 2, and a vertical synchronization signal (VSYNC #). The 8-bit R signal, G signal, and B signal of the obtained digital signal are subjected to scaling, dithering processing, and the like. 4 is output.
The scan converter 3 outputs a synchronization signal to the signal processing unit 4.
[0019]
The signal processing unit 4 performs predetermined processing based on the digital input signal output from the scan converter 3 and outputs a processing result to the S / H driver 5.
[0020]
The signal processing unit 4, for example, synchronizes with the reference clock output from the reference clock (XTL) 7 and the synchronization signal output from the scan converter 3, and outputs a 12-bit R signal output from the scan converter 3. Based on the G signal and the B signal, a predetermined process including, for example, a gamma correction process described later is performed, and a 12-bit R signal, a G signal, and a B signal are output to the S / H driver 5.
[0021]
The signal processing section 4 outputs a synchronization signal to the S / H driver 5.
The signal processing unit 4 outputs a predetermined signal, for example, a setting signal or the like to the LCD panel 6.
[0022]
The sample / hold (S / H) driver 5 samples / holds the image signal output from the signal processing unit 4 in synchronization with the synchronization signal output from the signal processing unit 4, for example. 6 is output.
[0023]
The S / H driver 5 includes, for example, a plurality of S / H drivers 5-1 to 6, specifically, S / H drivers 5-1 to 5-2 corresponding to the vertical and horizontal directions of the R signal, and the vertical and horizontal directions of the G signal. It has S / H drivers 5-3 to 5-4 corresponding to horizontal and S / H drivers 5-5 to 6 corresponding to vertical and horizontal of the B signal, respectively.
[0024]
The LCD panel 6 displays an image according to the signal output from the S / H driver 5.
The LCD panel 6 has, for example, a plurality of LCD panels 6-1 to 6-1.
[0025]
For example, the LCD panel 6-1 displays an image corresponding to a 6-bit R signal output from the S / H drivers 5-1 and 5-2 and a predetermined signal output from the signal processing unit 4.
[0026]
For example, the LCD panel 6-2 displays an image corresponding to a 6-bit G signal output from the S / H drivers 5-3 and 4 and a predetermined signal output from the signal processing unit 4.
For example, the LCD panel 6-3 displays an image corresponding to a 6-bit B signal output from the S / H drivers 5-5 and 6 and a predetermined signal output from the signal processing unit 4.
[0027]
The operation of the image processing apparatus 1 having the above configuration will be briefly described.
The analog video signal is A / D-converted by an A / DPLL (converter) 2, subjected to scaling and dithering processing by a scan converter 3, and output as 12-bit digital data.
[0028]
The digital data is input to the signal processing unit 4, and is subjected to gamma correction processing in accordance with the VT characteristic of the LCD panel 6 by an internal gamma correction circuit (block) to be described later and output.
The output image signal is sampled / held by a sample / hold driver 5 and then output to an LCD panel 6, where a predetermined image is displayed.
[0029]
FIG. 2 is a diagram showing characteristics of transmittance (VT characteristics) with respect to an applied voltage of an LCD (liquid crystal) panel.
In the LCD (liquid crystal) panel 6, the characteristics of the transmittance with respect to the applied voltage (hereinafter referred to as VT characteristics) have nonlinear characteristics as shown in FIG. For example, FIG. 2 shows VT characteristics of a normally white transmission type liquid crystal.
[0030]
FIG. 3 is a diagram showing ideal transmittance characteristics with respect to an input signal level. FIG. 4 is a diagram showing a gamma correction curve.
For the display luminance in the image processing apparatus 1, it is desired that the characteristic of the transmittance with respect to the input signal level has an exponential function characteristic, for example, as shown in FIG.
Due to the requirement of the conditions of these two characteristics, the output signal level (liquid crystal applied voltage) with respect to the input signal level needs to be nonlinearly corrected as shown in FIG. 4, and this correction is called gamma correction.
[0031]
For example, an image displayed by the image processing apparatus 1 is captured by a camera or the like, and gamma correction value data is calculated based on the output signal level of the image processing apparatus 1 and the signal level of the signal processing unit 4. At this time, the image processing apparatus 1 according to the present embodiment does not store the gamma correction value data of all the input signal levels as a look-up table, but stores the gamma correction value data of a predetermined quantization bit in the input signal. I do.
[0032]
When performing the correction based on the input signal, the image processing apparatus including the correction circuit according to the present embodiment outputs the gamma correction value data corresponding to the input signal with reference to the look-up table. When the level of the input signal is between predetermined quantization bit intervals in the look-up table, interpolation processing is performed based on the input signal and the look-up table to output gamma correction value data.
[0033]
FIG. 5 is a functional block diagram illustrating a configuration of a signal processing unit of the image processing apparatus illustrated in FIG.
The signal processing unit 4 includes a first signal processing unit 41, a gamma correction circuit (block) 42, a second signal processing unit 43, and a timing generation unit 44.
[0034]
The first signal processing unit 41 performs predetermined processing, for example, processing such as gain adjustment and limit, and outputs the processing result to the gamma correction circuit 42.
For example, the first signal processing unit 41 includes a first signal processing unit 41-1 for processing an R signal, a first signal processing unit 41-2 for processing a G signal, and a first signal processing unit 41-2 for processing a B signal. A signal processing unit 41-3.
[0035]
The gamma correction circuit 42 performs a gamma correction process described below in accordance with the signal output from the first signal processing unit 41, and outputs a result of the correction process to the second signal processing unit 43.
For example, the gamma correction circuit 42 includes a gamma correction circuit 42-1 for processing an R signal, a gamma correction circuit 42-2 for processing a G signal, and a gamma correction circuit 42-3 for processing a B signal.
[0036]
The second signal processing unit 43 performs a predetermined process, for example, a process such as gain adjustment or limit, according to the signal output from the gamma correction circuit 42, and outputs a processing result to the S / H driver 5.
For example, the second signal processing unit 43 includes a second signal processing unit 43-1 for processing an R signal, a second signal processing unit 43-2 for processing a G signal, and a second signal processing unit 43-2 for processing a B signal. It has a signal processing unit 43-3.
[0037]
The timing generation unit 44 includes a horizontal synchronization signal (HSYNC), a vertical synchronization signal (VSYNC), an R signal Rout # processed by the first signal processing unit 41, a gamma correction circuit 42, and a G signal. A control signal is output to LCD panel 6 at a predetermined timing based on Gout # and B signal Bout #. For example, this control signal controls the setting of the LCD panel 6.
[0038]
In the signal processing unit 4 having the above-described configuration, the R signal Rin is processed by the first signal processing unit 41-1, processed by the gamma correction circuit 42-1 and processed by the second signal processing unit 43-1. , R signal Rout # is output as the processing result.
[0039]
The G signal Gin is processed by the first signal processing unit 41-2, processed by the gamma correction circuit 42-2, processed by the second signal processing unit 43-2, and a G signal Gout # is output as a processing result. You.
[0040]
The B signal Bin is processed by the first signal processing unit 41-3, processed by the gamma correction circuit 42-3, processed by the second signal processing unit 43-3, and a B signal Bout # is output as a processing result. You.
[0041]
FIG. 6 is a diagram illustrating a specific example of a functional block of the signal processing unit illustrated in FIG. For example, in more detail, as shown in FIG. 6, the signal processing unit 4 includes a user gain 411, a user bright 412, a sub gain 413, a sub bright 414, a black frame 415, a first mute 416, a pattern generator 417, an OSD 418, and a gamma. It has functional blocks such as a correction circuit 42, a gamma gain 431, a gamma bright 432, a color unevenness correction 433, a dot line inversion 434, a second mute 435, a limiter 436, a ghost cancel 437, and a vertical stripe cancel 438.
[0042]
Each functional block will be briefly described. Note that parameters such as coefficients used in each functional block are set from, for example, a host device (not shown) via a host I / F (not shown).
[0043]
The user gain 411 performs a multiplication process for adjusting a user control gain, for example. In the calculation of the user gain 411, multiplication is performed using a 12-bit input signal and an 8-bit coefficient, rounding is performed with predetermined bits, and 12-bit data is output to the user bright 412.
[0044]
The user bright 412 performs addition and subtraction processing as brightness adjustment for user control.
The user bright 412 calculates a 12-bit input signal output from the user gain 411 and a 13-bit coefficient (MSB is a sign bit), and outputs the 12-bit data of the calculation result to the sub-gain 413.
[0045]
The sub gain 413 performs a multiplication process as gain adjustment for white balance.
The calculation of the sub gain 413 is performed based on the 12-bit input signal output from the user bright 412 and the 8-bit coefficient, rounded to a predetermined bit, clipped, and converted to 12-bit data. Output to the sub-bright 414.
[0046]
The sub-bright 414 performs addition and subtraction processing as bright adjustment for white balance.
The operation of the sub-bright 414 is performed, for example, by performing addition and subtraction processing on the basis of a 12-bit input signal output from the sub-gain 413 and a predetermined coefficient (MSB is a sign bit) to convert the 12-bit data into a black frame (block). ) 415.
[0047]
A black frame (block) 415 performs processing for fixing the blanking period of the image signal to an arbitrary level regardless of the result of the preceding signal processing.
[0048]
A black frame (block) 415 indicates that when the number of pixels determined from the effective period of the image signal to be displayed is less than the number of pixels of the LCD panel 6 to be displayed, a blanking period of the video signal is displayed in the remaining pixels. Is done. At this time, the black frame block 415 fixes the blanking period to be displayed at an arbitrary level regardless of the result of image quality adjustment such as gain and brightness adjustment.
Here, an arbitrary range of the image signal is replaced with 12-bit data by switching the image signal and the coefficient by using a pulse output from a pulse decoder (not shown), and the 12-bit data is converted to the first mute 416. Output.
[0049]
The first mute 416 replaces a 12-bit input signal with data of an arbitrary level to perform a mute process, and outputs the processed 12-bit data to a pattern generator 417.
[0050]
The pattern generator 417 generates a fixed pattern independent of the input signal, for example, a fixed pattern such as a vertical stripe, a diagonal stripe, a horizontal stripe, a cross hatch, a dot, a horizontal ramp, a horizontal steer, a vertical ramp, and a vertical steer as required. Process and output to OSD 418.
[0051]
The OSD 418 inputs a 2-bit OSD signal and YS and YM signals for each color to perform halftone processing on the video signal and OSD_MIX processing, and outputs the processing result to the gamma correction circuit 42.
[0052]
The gamma correction circuit 42 performs a gamma correction process described later based on the 12-bit data output from the OSD 418, and outputs 12-bit data to the gamma gain 431.
[0053]
The gamma gain 431 performs a multiplication process as a gain adjustment based on the 12-bit input signal output from the gamma correction circuit 42 in order to correct the variation in the VT characteristic of the LCD panel 6, and obtains a 12-bit processing result. The data is output to gamma bright 432.
[0054]
The gamma bright 432 performs addition and subtraction processing as bright adjustment for correcting variations in the VT characteristics of the LCD panel 6 based on the gamma-corrected 12-bit signal output from the gamma gain 431, The 12-bit data resulting from the processing is output to color shading correction 433.
[0055]
The color shading correction 433 performs a color shading correction process by adding a correction signal to the image signal. For example, correction points are set at regular intervals in the horizontal, vertical, and gradation directions of a video signal, correction data of the correction points is written in a RAM (not shown), and the data is read out and interpolated. By performing the calculation, a correction curve is generated, color unevenness correction processing is performed based on the correction curve, and the resulting 12-bit data is output to the dot line inversion 434.
[0056]
The dot line inversion 434 performs signal processing at the time of dot line inversion driving based on the 12-bit data output from the color shading correction 433, and outputs the signal to the second mute 435.
[0057]
The second mute 435 replaces the video signal output from the dot line inversion 434 with data of an arbitrary level, performs mute processing, and outputs the processing result to the limiter 436.
[0058]
The limiter 436 performs limiter processing based on the 12-bit signal output from the second mute 435 so that the output signal does not exceed a certain range, and outputs 12-bit data to the ghost cancel 437.
[0059]
The ghost cancel 437 corrects, for example, a ghost generated inside the LCD panel 6 by signal processing based on the 12-bit data output from the limiter 436, and outputs the corrected ghost to the vertical stripe cancel 438.
The vertical stripe cancel 438 performs a correction process for reducing vertical stripes generated in the LCD panel 6, and outputs a 12-bit length output signal.
[0060]
For example, each functional block of the signal processing unit 4 processes each of the R signal, the G signal, and the B signal.
[0061]
FIG. 7 is a functional block diagram of the first embodiment according to the gamma correction circuit shown in FIG.
As shown in FIG. 7, the gamma correction circuit 42 includes a bit generation unit for correction 420 including an addition and overflow processing unit 421, a flip-flop (FF) 422, and a gamma correction look-up table memory (simply referred to as a memory) 423. , And an interpolation operation unit 424.
[0062]
The memory 423 corresponds to a storage unit according to the present invention, and the interpolation calculation unit 424 corresponds to an interpolation unit according to the present invention.
[0063]
The to-be-corrected bit generation unit 420 extracts a higher-order bit of a predetermined bit width from the input image signal to generate a to-be-corrected bit, and corrects the corrected bit by a predetermined bit corresponding to the predetermined bit width. A bit to be corrected that is larger than the bit to be used is generated and output.
For example, the bit generation unit for correction 420 includes an addition and overflow processing unit 421.
[0064]
The addition and overflow processing unit 421 adds a predetermined bit corresponding to the predetermined bit width to the bit to be corrected (point A) extracted from the upper bit of the predetermined bit width based on the input image signal. A correction bit (point B) larger than the bit (point A) is generated and output.
Two points near the input signal are generated according to the quantization bits of the look-up table.
[0065]
The addition and overflow processing unit 421 interpolates between two points by a linear interpolation function, for example, when two points near the input signal are point A and point B with predetermined quantization bits of a memory 423 described later in detail. In order to do so, a bit to be corrected (point B) is generated by adding 1 to the tenth bit of the bit to be corrected (point A) of the upper 10 bits of the 12-bit input signal and output to the memory 423.
Specifically, the addition and overflow processing unit 421 inputs a signal obtained by adding 1 to the 10th bit of the upper 10 bits of the input signal to each address port of the memory 423.
[0066]
The flip-flop (FF) 422 adjusts the timing at which an input signal is input to the interpolation calculation unit 424.
The FF 422 holds the remaining bits to be interpolated except for the bits to be corrected from the input signal, more specifically, the lower two bits to be interpolated of the input signal, and corrects the bits from the memory 423 at a predetermined timing. The value is output to the interpolation calculation unit 432 so as to coincide with the timing at which the value data is output.
[0067]
The gamma correction look-up table memory (memory) 423 is a gamma correction look-up table that associates higher-order bits to be interpolated with a predetermined bit width of an input signal of a predetermined gradation with gamma correction value data. (LUT) is stored.
For example, when the upper 10 bits to be corrected are input as an input signal, the memory 423 is configured as a dual port memory having two read ports having a memory capacity of 2 ＾ 10 = 1024 words, and a gamma correction. Stores value data.
[0068]
FIG. 8 is a diagram for explaining a look-up table (LUT) of the memory of the gamma correction circuit shown in FIG. FIG. 8A shows bits to be corrected of predetermined upper bits of the input signal, which correspond to addresses in the memory 423. FIG. 8B shows gamma correction value data corresponding to the bit to be corrected of the input signal shown in FIG.
[0069]
The gamma correction value data is, for example, gamma correction value data that associates an input signal level with an output signal level as shown in FIG.
For example, the gamma correction value data is generated based on a result of comparing a display image displayed according to an input signal with a signal captured by an imaging device such as a camera and the input signal.
[0070]
For example, as shown in FIG. 8, the memory 423 stores correction value data corresponding to a predetermined higher-order bit of the input signal at an address corresponding to a predetermined higher-order bit of the input signal. I do.
[0071]
For example, the memory 423 is a dual-port memory 423. When each of the bits to be corrected corresponding to the points A and B is input, the memory 423 converts the table and interpolates the correction value data corresponding to the bits to be corrected. Output to the arithmetic unit 424.
[0072]
In the memory 423, for example, when a look-up table is written, when a memory control signal including a write instruction is input, correction value data is stored at a predetermined address. When reading the lookup table for confirmation or the like, when a memory control signal including a read instruction is input, correction value data at a predetermined address is output.
[0073]
The interpolation calculation unit 424 determines the correction value data at the points A and B output from the memory 423 and the interpolated bits of the remaining lower bits obtained by removing the upper bits from the input signal output from the FF422. , Perform a linear interpolation process.
[0074]
FIG. 9 is a diagram for explaining the operation of the interpolation calculation unit of the correction circuit shown in FIG. FIG. 10 is a diagram for explaining the association between the lower bits of the input signal of the interpolation operation unit of the correction circuit shown in FIG. 7 and gamma correction value data.
[0075]
Specifically, for example, assuming that the number of quantized bits of the bit to be interpolated is 2, the interpolation calculation unit 424 divides the interpolated value data of the points A and B into four, and , 、 ３, and 点 points).
[0076]
Further, for example, when the number of quantized bits of the bit to be interpolated is 3, the interpolated value data at the points A and B is divided into eight, and when the number of quantized bits of the bit to be interpolated is n, Divides the interpolated value data at points A and B into 2 n powers to generate interpolated value data.
By setting the quantization bit of the bit to be interpolated to an arbitrary value, it is possible to cope with a required memory capacity and correction accuracy.
[0077]
The interpolation calculation unit 424 selects the generated interpolation value data and correction value data based on the input lower two bits to be interpolated.
Specifically, for example, as shown in FIG. 10, when the lower 2 bits of the input signal to be interpolated are 00, the interpolation calculator 424 outputs the gamma correction value at point A.
[0078]
When the lower 2 bits of the input signal to be interpolated are 01, the interpolation calculator 424 determines that {(gamma correction value at point B−gamma correction value at point A) / 2} × (｝) + A Output the gamma correction value of the point.
[0079]
When the lower 2 bits of the input signal to be interpolated are 10, the interpolation calculation unit 424 determines that {(gamma correction value at point B−gamma correction value at point A) / 2} × (1/2) + A Output the gamma correction value of the point.
[0080]
When the lower 2 bits of the input signal to be interpolated are 11, the interpolation calculator 424 determines that {(gamma correction value at point B−gamma correction value at point A) / 2} × (3/4) + A Output the gamma correction value of the point.
[0081]
At this time, since the gamma characteristic of the LCD panel 6 is represented by an increasing non-linear function with respect to the input signal with respect to the input signal, the value of the point A having a small signal level and the interpolation value data obtained earlier are added to obtain the input signal to be obtained. The correction value data of the signal can be obtained.
[0082]
Further, the interpolation processing of the interpolation calculation unit 424 generates interpolation value data corresponding to the lower bit to be interpolated based on the correction value data of the points A and B, and performs interpolation of the lower bit of the input signal. Although the correction value data corresponding to the use bit is selected, the present invention is not limited to such a form.
For example, without calculating the interpolation value data between the points A and B, the interpolation calculation unit 424 calculates the interpolation value data at the points A and B and the interpolation target bit of the lower bit of the input signal based on the correction value data at the points A and B. Only the correction value data corresponding to the interpolation bit may be generated.
[0083]
FIG. 11 is a diagram for explaining the operation of the correction circuit shown in FIG. The operation of the correction circuit 42 having the above configuration will be described with reference to FIG.
[0084]
The gamma correction value data is stored in the memory 423 in advance using a gamma correction value data and a dual port memory having two read ports with a memory capacity of 2 ＾ 10 = 1024 words.
[0085]
In step ST1, in addition and overflow 421, when the upper 10 bits to be corrected of the input signal are input based on the input signal, a corrected bit is generated by adding 1 to the 10th bit, and 423. The upper 10 bits to be corrected of the input signal are input to the memory 423.
[0086]
In step ST2, the memory 423 adds 1 to the upper 10 bits of the input signal to be corrected (point A) and the 10 bits of the upper 10 bits of the input signal output from the addition and overflow processing unit 421. The corrected bit (point B) is input to a predetermined address port, and the correction value data stored at the address corresponding to each of the corrected bits is output to the interpolation calculator 424. Specifically, correction value data corresponding to each of the bits A and B for correction is output to the interpolation calculation unit 424.
[0087]
In step ST3, the FF 422 holds the lower two bits of the input signal to be interpolated, and outputs the interpolated bit to the interpolation calculator 424 at a predetermined timing.
The interpolation operation unit 424 performs an interpolation process based on the correction value data of the points A and B output from the memory 423 and the lower two bits of the input signal output from the FF 422 for interpolation.
[0088]
Specifically, for example, in the interpolation operation unit 424, the number of bits to be interpolated is two, and therefore, as shown in FIG. (4, 1/2, 3/4 points) interpolation value data is obtained, and interpolation corresponding to the input signal is performed from the generated interpolation value data and the correction value data at point A based on the lower 2 bits to be interpolated. Select the value data. At this time, since the gamma characteristic of the LCD is represented by a non-linear function in which the output signal always increases with respect to the input signal, the value of point A having a small signal level and the interpolation value data obtained earlier are added, and the input signal level to be obtained is obtained. Gamma correction value data can be obtained.
The interpolation operation unit 424 outputs the image signal that has been subjected to the interpolation processing to predetermined constituent elements at the next stage.
[0089]
As described above, for example, a conventional gamma correction look-up memory uses a memory having a memory capacity of 2 ＾ 12 = 4096 words in the case of an input signal having a 12-bit width gradation. By storing the value data, table conversion is performed as an LUT. In contrast, in the present embodiment, a memory having a smaller storage capacity and a memory capacity of 1024 words may be used.
[0090]
As described above, based on the input image signal, the bits to be corrected (points A) obtained by extracting the upper bits of a predetermined bit width are added to the bits to be corrected (A) by a predetermined bit corresponding to the predetermined bit width. ), An addition and overflow processing unit 421 that generates and outputs a bit to be corrected (point B) larger than the point), a memory 423 that stores a look-up table (LUT), an FF 422 for timing adjustment, and an output from the FF 422. Since an interpolation operation unit 424 for performing an interpolation process is provided based on the bits to be corrected of the lower bits of the input signal and the two correction value data output from the memory 423, a lookup table smaller than in the related art is provided. To generate correction value data corresponding to the input image signal.
Further, the storage capacity of the memory 423 that stores the look-up table (LUT) can be reduced.
[0091]
Further, since the size of the memory required for performing the table conversion by the LUT on the input signal is reduced, it is possible to suppress the memory capacity and the power consumption.
[0092]
In addition, since the memory scale used for the LUT is smaller than that of a correction circuit using a conventional LUT, the transfer time of gamma correction value data to be stored in the LUT can be reduced. Occupied time can be shortened, and during the vacant time, power consumption can be suppressed.
[0093]
In addition, it is not necessary to perform the arithmetic processing of the gamma correction value data conventionally obtained by software by software, and the software only needs to prepare gamma correction value data of a specific level. For this reason, it is possible to reduce the processing time of software and the amount of source code.
[0094]
Second embodiment
FIG. 12 is a functional block diagram of a second embodiment of the correction circuit according to the present invention.
As shown in FIG. 11, the correction circuit 42a according to the present embodiment includes an address selector 4211, a selector 4212, an FF 422a, a first gamma correction look-up table memory (first memory) 4231, and a second gamma correction A memory 423a including a lookup table memory (second memory) 4232 for use, a data selector 4233, and an interpolation operation unit 424a.
[0095]
A major difference between the correction circuit 42a and the correction circuit 42 according to the first embodiment is that two memories for storing a look-up table are provided.
[0096]
The address selector 4211 generates correction target bits at points A and B at two points near the input signal based on the input image signal, and outputs the bits to the memory 423a.
Based on the input image signal, the address selector 4211 generates a first bit to be corrected in the input image signal and a second bit larger than the first bit to be corrected by a predetermined bit corresponding to a predetermined bit width. A bit to be corrected is generated, and the first and second bits to be corrected are output to a memory 423a, which will be described later, according to whether the bit is an even number or an odd number.
[0097]
For example, when a 12-bit width image signal is input, the address selector 4211 assigns 1 to the upper 9 bits to be corrected (point A) and, if necessary, the upper 9 bits to be corrected. Is added to obtain a bit to be corrected (point B).
[0098]
FIG. 13 is a diagram for explaining signals input to the correction circuit shown in FIG.
For example, when the input signal is 12 bits, the address selector 4221 uses the upper 9 bits as the address of the memory 423a as shown in FIG.
The address selector 4221 generates bits to be corrected for generating correction values corresponding to points A and B near the input signal based on, for example, the upper 9 bits of the input signal.
[0099]
FIG. 14 is a diagram for explaining the operation of the address selector of the correction circuit shown in FIG.
As shown in FIG. 14, when the input signal is 0 in the third bit from the LSB, the address selector 4221 sets the point A in the first memory 4231 (even memory), which will be described later, 9 bits to be corrected are input as an address.
In addition, the address selector 4221 inputs, to the second memory 4232 (odd number memory), the upper 9 bits to be corrected of the input signal as the point B as an address.
[0100]
When the third bit from the LSB of the input signal is 1, the address selector 4221 sets the point A to the second memory (odd-numbered memory) 4232 as the point A using the upper 9 bits of the input signal as the address to be corrected. input.
In addition, the address selector 4221 uses the first memory (even memory) 4231 as an address with the corrected bit obtained by adding the first 9 bits from the MSB to the 9 higher-order bits of the input signal as a point B. input.
[0101]
The address selector 4211 stores one of the first memory 4231 and the second memory 4232 of the memory 423a according to whether the value of the tenth bit from the MSB of the bit to be corrected is an even number or an odd number, as described later. To generate correction value data.
The lower 2 bits to be interpolated of the input signal are used by the interpolation calculator 424a as interpolation calculation parameters.
[0102]
The selector 4212, for example, extracts the lower two bits from the input signal and outputs the lower two bits to the FF 422a as bits to be interpolated.
The selector 4212, for example, extracts the lower two bits from the address selector 4211 based on the remaining bits to be interpolated from the input signal, excluding the bits to be corrected, and outputs the lower two bits to the FF 422a as the bits to be interpolated.
The selector 4212 is not limited to this mode. For example, it suffices if the lower two bits of the input signal can be extracted and output to the FF 422a as bits to be interpolated.
[0103]
The FF 422a holds the lower bit to be interpolated of the input signal output from the selector 4212, and outputs the lower bit to the interpolation calculator 424a at a predetermined timing.
The FF 422a performs, for example, the interpolation processing based on the correction value data at the points A and B output from the data selector 4223 and the lower bits of the input signal output from the FF 422a by the interpolation calculation unit 424a. Is performed, the lower-order bits of the input signal to be interpolated are output to the interpolation calculator 424a at a timing appropriate for the processing, for example, at the same time as the correction value data output from the data selector 4233. .
[0104]
The memory 423a includes a plurality of memories, for example, a first memory 4231 and a second memory 4232.
For example, each of the first memory and the second memory is a single-port memory having one read port having a memory capacity of 2 ＾ 9 = 512 words, and stores a look-up table including gamma correction value data.
[0105]
FIG. 15 is a diagram schematically showing a lookup table stored in the first memory and the second memory of the correction circuit shown in FIG.
FIG. 15A shows the upper 9 bits to be corrected of the input signal and the address of the first memory, and FIG. 15B shows the input of FIG. 15A stored in the first memory. FIG. 7 is a diagram illustrating a specific example of gamma correction value data corresponding to a signal.
FIG. 15C shows the upper 9 bits to be corrected of the input signal and the address of the second memory, and FIG. 15D shows the input of FIG. 15C stored in the second memory. FIG. 7 is a diagram illustrating a specific example of gamma correction value data corresponding to a signal.
[0106]
In the first memory 4231, for example, as shown in FIGS. 15A and 15B, the third bit data of the input signal corresponds to an even number in accordance with the third bit data from the LSB of the input signal. Stores gamma correction value data. The first look-up table stored in the first memory 4231 is stored, for example, as shown in FIGS.
[0107]
In the second memory 4232, for example, as shown in FIGS. 15C and 15D, the third bit data of the input signal corresponds to the odd number in accordance with the third bit data from the LSB of the input signal. Stores gamma correction value data. The second lookup table stored in the second memory 4232 is stored, for example, as shown in FIGS.
[0108]
The data selector 4233, based on the correction value data output from the first memory 4231 and the correction value data output from the second memory 4232, for example, as shown in FIG. And the larger data is output to the interpolation calculator 424a as the correction value data of the point B.
[0109]
The interpolation operation unit 424a converts the gamma correction value data at two points (points A and B) in the vicinity of the input signal output from the data selector 4233 and the interpolated bits of the lower bits of the input signal output from the FF 422a. Based on this, linear interpolation processing is performed to generate and output gamma correction value data of the input signal.
The function of the interpolation calculation unit 424a is the same as that of the interpolation calculation unit 424 of the correction circuit according to the first embodiment, and thus detailed description is omitted.
[0110]
The operation of the above configuration will be briefly described.
The first memory 4231 and the second memory 4232 each use the gamma correction value data and the above-described gamma correction value data using a single-port memory having a read port of 2 ＾ 9 = 512 words and one read port. Stores a lookup table.
[0111]
In the address selector 4211, as shown in FIG. 14, for example, as shown in FIG. 14, bits A and B to be corrected at two points near the input signal are generated and input to a predetermined memory 423a.
Specifically, in the address selector 4211, based on the input signal, only the first bit to be corrected in the input signal and a predetermined bit corresponding to the predetermined bit width are larger than the first bit to be corrected. A second bit to be corrected is generated and output to the first memory 4231 and the second memory 4232 according to whether the first and second bits to be corrected are even or odd.
[0112]
In each of the first memory 4231 and the second memory 4232 of the memory 423a, the correction value data corresponding to the input first and second bits to be corrected is output to the data selector 4233.
In the data selector 4233, based on the correction value data output from the first memory 4231 and the correction value data output from the second memory 4232, the smaller data is used as the correction value data at the point A, The data is output to the interpolation calculator 424a as the correction data of the point B.
[0113]
In the interpolation calculation unit 424a, gamma correction value data at two points (points A and B) in the vicinity of the input signal output from the data selector 4233, and interpolation of lower bits of the input signal output from the selector 4212 and the FF 422a are performed. Linear interpolation processing is performed based on the use bits, and gamma correction value data of the input signal is generated and output.
[0114]
As described above, in the present embodiment, a predetermined higher-order bit is extracted based on an input signal, and two points near the input signal are generated as bits to be corrected at points A and B, and the bits are corrected to a predetermined 423a. An address selector 4211 for outputting, a selector 4212 for outputting a predetermined lower-order bit to be interpolated of the input signal, a FF 422a for timing adjustment, and gamma correction value data in which the third bit data of the input signal corresponds to an even number , A second memory 4232 for storing gamma correction value data in which the third bit data of the input signal corresponds to an odd number, and a correction value data output from the memory 423a. A data selector that outputs the smaller data as the correction value data at point A and the larger data as the correction value data at point B to the interpolation calculator 424a. 233, the gamma correction value data at two points (points A and B) in the vicinity of the input signal output from the data selector 4233, and the interpolated data of the lower bits of the input signal output from the FF 422a. Since the interpolation calculation unit 424a that performs linear interpolation processing and generates and outputs gamma correction value data of the input signal is provided, correction value data corresponding to the input signal can be generated using a small lookup table.
[0115]
Further, the storage capacity of the memory 423a that stores the look-up table (LUT) can be reduced.
Further, since the two memories are provided, for example, the correction value data of the points A and B can be simultaneously generated at a high speed, so that the interpolation calculation unit 424a can perform the interpolation calculation at an earlier timing. As a result, the correction value data can be generated more quickly.
[0116]
Third embodiment
As a method of generating gamma correction value data used for a look-up table (LUT), an image displayed by an image processing device is captured by a camera or the like, and gamma correction is performed based on an output signal level of the image display device and an input signal level of a digital circuit. Calculate the value data.
[0117]
The gamma correction value data calculated at this time is not created for all input signal levels of the quantization bit number n, but is created with the quantization bit number (nm). Here, the relationship between m and n is 1 <m <n.
[0118]
FIG. 16 is a functional block diagram of the third embodiment of the image processing apparatus according to the present invention.
The correction circuit 42b of the image processing device according to the third embodiment includes, for example, as shown in FIG. 16, an addition and overflow processing unit 421b, a flip-flop (FF) 422b, a memory 423b, and an interpolation calculation unit 424b.
[0119]
The correction circuit 42b has substantially the same configuration as the correction circuit 42 according to the first embodiment. The difference is that the memory 423b stores only the gamma correction value data created with the above-mentioned quantization bit number (nm) as a look-up table.
The interpolation calculation unit 424b performs an interpolation process on the gamma correction value data for the input signal having the quantization bit number n based on the data output from the memory 423 and the input signal, and corrects the correction value corresponding to the input signal. Output data.
[0120]
As described above, the correction circuit 42b having the above-described configuration performs the correction process based on the gamma correction value data corresponding to the level of the input signal having the number of quantization bits (nm), and thus has a desired correction accuracy. It is possible to store correction data of a predetermined quantization bit (nm) in consideration of data, memory capacity, and the like.
As a result, the gamma correction value data obtained by performing the interpolation calculation using the conventional software is not required.
[0121]
Note that the present invention is not limited to the present embodiment, and various suitable modifications are possible.
For example, the number of input bits is 12 bits, the number of input bits of the LUT is 10 bits in the embodiment, 9 bits in the second embodiment, the number of bits of the area to be interpolated is 2 bits, and the number of output bits of the system is Although the number is described as being 12 bits, the present invention is not limited to this form. It does not limit the value of each bit number.
[0122]
Also, the VT characteristic of a normally white transmission type liquid crystal has been described as an example of a display device, but it is also effective in digital gamma correction of a normally black liquid crystal and a reflection type liquid crystal. Further, the present invention is similarly effective in digital gamma correction in a display device that responds similarly in a non-linear manner, such as a CRT, other than liquid crystal.
[0123]
Also, by performing gamma correction using a look-up table that is smaller than the required amount to match the image signal to the characteristics of the output device and an interpolation function to interpolate the data that is insufficient, the memory required for table conversion is obtained. Can be reduced in size.
[0124]
【The invention's effect】
According to the present invention, it is possible to provide an image processing apparatus and an image processing method that can perform correction without increasing the circuit scale.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of an embodiment of an image processing apparatus according to the present invention.
FIG. 2 is a diagram illustrating characteristics of transmittance (VT characteristics) with respect to an applied voltage of an LCD (liquid crystal) panel.
FIG. 3 is a diagram illustrating ideal transmittance characteristics with respect to an input signal level;
FIG. 4 is a diagram showing a gamma correction curve.
FIG. 5 is a functional block diagram illustrating a configuration of a signal processing unit of the image processing apparatus illustrated in FIG. 1;
FIG. 6 is a diagram illustrating a specific example of a functional block of a signal processing unit illustrated in FIG. 5;
FIG. 7 is a functional block diagram of a first embodiment of the gamma correction circuit shown in FIG.
8 is a diagram for explaining a look-up table (LUT) of a memory of the gamma correction circuit shown in FIG. 7;
FIG. 9 is a diagram for explaining an operation of an interpolation operation unit of the correction circuit shown in FIG. 7;
FIG. 10 is a diagram for explaining correspondence between lower-order bits of an input signal of an interpolation operation unit of the correction circuit shown in FIG. 7 and gamma correction value data.
11 is a diagram for explaining the operation of the gamma correction circuit shown in FIG.
FIG. 12 is a functional block diagram of a correction circuit of the image processing apparatus according to the second embodiment of the present invention.
FIG. 13 is a diagram for explaining signals input to the correction circuit shown in FIG. 11;
14 is a diagram for explaining an operation of the address selector of the correction circuit shown in FIG.
15 is a diagram schematically illustrating a lookup table stored in a first memory and a second memory of the correction circuit illustrated in FIG. 12;
FIG. 16 is a functional block diagram of a correction circuit of an image processing apparatus according to a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 2 ... A / DPLL, 3 ... Scan converter, 4 ... Signal processing part, 5 ... S / H driver, 6 ... LCD panel, 7 ... XTL, 41 ... First signal processing part, 42 ... Correction circuit, 43 second signal processing unit, 44 timing generation unit, 411 user gain, 412 user brightness, 413 sub gain, 414 sub bright, 415 black frame, 416 first mute, 417 Pattern generator, 418 OSD, 420 signal generation unit for correction, 421 addition and overflow processing unit, 422 FF, 423 interpolation processing unit, 424 memory, 424a interpolation processing unit, 424b interpolation processing unit 431: Gamma gain, 432: Gamma bright, 432: Interpolation calculation unit, 433: Color unevenness correction, 434: Dot line inversion, 435 ... 2, mute 2, 436 ... limiter, 437 ... ghost cancel, 438 ... vertical streak cancel, 4211 ... address selector, 4212 ... selector, 4221 ... address selector, 4223 ... data selector, 4231 ... first memory, 4232 ... second Memory, 4233... Data selector.

Claims (10)

An image processing device that performs a correction process on an image signal including a plurality of bits,
Storage means for storing correction value data for converting a bit to be corrected in the image signal into a table,
The first correction value data table-converted by the storage unit based on the first bit to be corrected in the input image signal, and the second bit to be corrected that is larger than the first bit to be corrected. Based on the second correction value data table-converted by the storage means based on the input image signal and the remaining bits to be interpolated except the bits to be corrected from the input image signal, an interpolation process is performed on the input image signal. An image processing apparatus having interpolation means for generating third correction value data. 2. The image processing apparatus according to claim 1, wherein the interpolation unit performs a linear interpolation process based on the first and second correction value data and the bit to be interpolated to generate the third correction value data. 3. . The interpolation means generates interpolation value data between the first and second correction value data based on the first and second correction value data and the number of quantization bits of the bit to be interpolated. 2. The data according to claim 1, wherein data corresponding to the bit to be interpolated is extracted from the interpolation value data and the first correction value data, and the extracted data is used as the third correction value data. Image processing device. The storage means, even-number correction value data storage means for storing correction value data for table conversion of the even-number of bits to be corrected,
An odd-number correction value data storage unit that stores correction value data for converting the odd-number of bits to be corrected into a table.
Generating a second to-be-corrected bit larger than the first to-be-corrected bit based on the first to-be-corrected bit of the input image signal; A bit generation unit for outputting to the even-number correction value data storage unit or the odd-number correction value data storage unit according to whether each bit is even or odd,
2. The interpolator according to claim 1, wherein the interpolator performs an interpolation process based on the first and second correction value data table-converted by the storage unit and the bit to be interpolated to generate the third correction value data. 3. The image processing apparatus according to claim 1. The image processing apparatus according to claim 1, further comprising a display unit configured to perform a display according to the third correction value data. An image processing method of an image processing apparatus that performs a table conversion of bits to be corrected in an image signal composed of a plurality of bits based on correction value data set in advance, and performs a correction process on the image signal.
Converting the table based on a first bit to be corrected in the input image signal to generate first correction value data;
Converting the table based on a second bit to be corrected larger than the first bit to be corrected to generate second correction value data;
Interpolation processing is performed based on the first and second correction value data and the remaining bits to be interpolated from the input image signal excluding the bits to be corrected, and third correction value data for the input image signal An image processing method for generating an image. When generating the third correction value data, the third correction value data is generated by performing linear interpolation processing based on the first and second correction value data and the bit to be interpolated. The image processing method according to claim 6. When generating the third correction value data, the first and second correction value data are generated based on the first and second correction value data and the number of quantization bits of the bit to be interpolated. Generate interpolated value data between
The image according to claim 6, wherein data corresponding to the bit to be interpolated is extracted from the interpolation value data and the first correction value data, and the extracted data is used as the third correction value data. Processing method. The correction value data for converting the even-numbered bits for corrected values into a table and the correction value data for converting the odd-numbered bits for corrected values into a table are stored, and the third correction value data is generated. In this case, based on the first bit to be corrected in the input image signal, a second bit to be corrected that is larger than the first bit to be corrected is generated,
The first and second correction value data table-converted by the stored correction value data according to whether the first and second correction target bits are even or odd, respectively, and the interpolation target bit The image processing method according to claim 6, wherein the third correction value data is generated by performing an interpolation process based on the third correction value data. The image processing method according to claim 6, wherein display is performed according to the third correction value data.

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