JP2004235637A - エッチストップ層の2段階形成方法 - Google Patents
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Abstract
【解決手段】Cu層が形成されるべき半導体基板上にCu層と接触する膜を形成するための方法は、(i)シリコン、炭素及び水素を含む蒸着ガス及び不活性ガスから成る第1反応ガスを基板が載置されるところの反応空間内に導入する工程と、(ii)第1反応ガスをプラズマへ励起することにより基板上にシリコンカーバイド膜を蒸着する工程と、(iii)シリコン、炭素及び水素を含む蒸着ガス、酸化ガス及び不活性ガスから成る第2反応ガスを反応空間内に導入する工程と、(iv)第2反応ガスをプラズマへ励起することによりシリコンカーバイド膜の頂面に炭素含有シリコン酸化膜を蒸着する工程を含む。
【選択図】図2
Description
具体例
具体例
図1に示される装置を使って、以下の実施例及び比較例が実行された。
膜形成条件は以下の通りである。
蒸着温度:380℃
TMS流量:300sccm
He流量:2500sccm
反応チャンバ圧力:533Pa
高周波電力 27.12MHz:450W
400kHz:100W
第1工程は実行されなかった。第2工程は図5に示されるシーケンスに従って実行された。
CO2流量:1900sccm
第1工程及び第2工程の膜形成は図2に示されるシーケンスに従い、以下に示す条件で実行された。
第1工程
蒸着温度:380℃
TMS流量:300sccm
He流量:2500sccm
反応チャンバ圧力:533Pa
高周波電力 27.12MHz:450W
400kHz:100W
第2工程(TMS流量及びHe流量は第1工程と同じ値)
CO2流量:1900sccm
第1工程及び第2工程の膜形成は図3に示されるシーケンスに従い、以下に示す条件で実行された。
第1工程
蒸着温度:380℃
TMS流量:300sccm
He流量:2500sccm
反応チャンバ圧力:533Pa
高周波電力 27.12MHz:450W
400kHz:100W
第2工程(TMS流量及びHe流量は第1工程と同じ値)
CO2流量:1900sccm
生成された膜特性が以下の表に示されている。
本発明に従う炭素含有シリコン酸化膜の比誘電率は4.0から4.5の限度内にあり、リーク電流値@2MV/cmは約5〜6×10−8A/cm2であった。比較のために、シリコンカーバイド膜が第1工程を省略して形成され、当該膜の特性が測定された。比誘電率4.4及びリーク電流値@2MV/cmは5.7×10−8A/cm2を有するほぼ等しい膜が得られた。
32 第2工程
33 プラズマ放電
34 ガス導入
35 TMS導入
36 パージ
41 TMS流量
42 He流量
43 反応チャンバ圧力
44 CO2流量
45 プラズマ放電
46 CO2安定化
Claims (24)
- Cu層が形成されるべき半導体基板上にCu層と接触する膜を形成するための方法であって、
シリコン、炭素及び酸素を含む蒸着ガス及び不活性ガスから成る第1反応ガスを基板が載置される反応空間内へ導入する工程と、
第1反応ガスをプラズマへ励起することにより基板上にシリコンカーバイド膜を蒸着する工程と、
シリコン、炭素及び水素を含む蒸着ガス、酸化ガス及び不活性ガスから成る第2反応ガスを反応空間内へ導入する工程と、
第2反応ガスをプラズマへ励起することによりシリコンカーバイド膜の頂面に炭素含有シリコン酸化膜を蒸着する工程と、
から成る方法。 - 請求項1に記載の方法であって、シリコンカーバイド膜は酸素を含まない、ところの方法。
- 請求項1に記載の方法であって、シリコンカーバイド膜はCu配線が形成されるべきところでCu配線と接触して形成される、ところの方法。
- 請求項1に記載の方法であって、第1及び第2反応ガスの励起は高周波(RF)電力を反応ガスに印加することにより実行される、ところの方法。
- 請求項4に記載の方法であって、シリコンカーバイド膜を蒸着する工程及び炭素含有シリコン酸化膜を蒸着する工程はRF電力供給を中断することなく連続的に実行される、ところの方法。
- 請求項4に記載の方法であって、RF電力供給はシリコンカーバイド膜を蒸着する工程と炭素含有シリコン酸化膜を蒸着する工程との間で中断される、ところの方法。
- 請求項6に記載の方法であって、RF電力供給は第2反応ガスを導入し圧力を安定化した後に再開される、ところの方法。
- 請求項1に記載の方法であって、蒸着ガスはテトラメチルシランまたはトリメチルシランである、ところの方法。
- 請求項1に記載の方法であって、不活性ガスは、アルゴン、ヘリウム、ネオン、キセノンまたはクリプトンである、ところの方法。
- 請求項1に記載の方法であって、シリコンカーバイド膜は、シリコン、炭素、窒素及び水素から成る、ところの方法。
- 請求項1に記載の方法であって、炭素含有シリコン酸化膜は、シリコン、炭素、酸素及び水素から成る、ところの方法。
- 請求項1に記載の方法であって、炭素含有シリコン酸化膜は、300℃から400℃の基板温度で形成される、ところの方法。
- 請求項1に記載の方法であって、シリコンカーバイド膜は300℃から400℃の基板温度で形成される、ところの方法。
- 請求項1に記載の方法であって、シリコンカーバイド膜の厚さが3nmから10nmに達したとき、シリコンカーバイド膜の蒸着が停止される、ところの方法。
- 請求項1に記載の方法であって、炭素含有シリコン酸化膜の厚さが30nmから70nmに達したとき、炭素含有シリコン酸化膜の蒸着が停止される、ところの方法。
- 請求項1に記載の方法であって、シリコンカーバイド膜を蒸着する工程及び炭素含有シリコン酸化膜を蒸着する工程は、低比誘電率層が基板上に形成されるところの反応チャンバ内で実行される、ところの方法。
- 請求項1に記載の方法であって、シリコンカーバイド膜を蒸着する工程及び炭素含有シリコン酸化膜を蒸着する工程は、低比誘電率層が基板上に形成されるところの反応チャンバに近接した反応チャンバ内で実行される、ところの方法。
- 請求項1に記載の方法であって、膜はエッチストップ層である、ところの方法。
- 請求項1に記載の方法であって、膜はハードマスクである、ところの方法。
- Cu層と接触する膜を含む層間構造を半導体基板上に製造するための方法であって、
(i)複数の層を半導体基板上に形成する工程と、
(ii)エッチングにより複数の層を層間結合するための孔を形成する工程と、
(iii)孔の中にCuを蒸着する工程と、
(iv)複数の層の頂面から余分のCuを除去する工程と、
(v)プラズマ反応により複数の層の頂面にシリコンカーバイド膜を蒸着する工程であって、Cuが当該シリコンカーバイド膜によって覆われるところの工程と、
(vi)プラズマ反応によりシリコンカーバイド膜の頂面に炭素含有シリコン酸化膜を蒸着する工程と、
から成る方法。 - 請求項20に記載の方法であって、複数の層は、基板上に連続して形成された下部エッチストップ層、低比誘電率層及び上部エッチストップ層から成り、工程(ii)において上部エッチストップ層の頂面にレジストを形成し該レジストを使って複数の層をエッチングすることでビアホールを形成することにより孔が生成され、工程(iv)においてレジスト及び上部エッチストップ層は余分のCuを除去する際に除去される、ところの方法。
- 請求項20に記載の方法であって、複数の層は、基板上に連続して形成された下部エッチストップ層、下部低比誘電率層、中間エッチストップ層、上部低比誘電率層及び上部エッチストップ層から成り、工程(ii)において上部エッチストップ層の頂面にレジストを形成し該レジストを使って複数の層をエッチングすることでビアホール及びトレンチを形成することにより孔が生成され、工程(iv)においてレジスト及び上部エッチストップ層は余分のCuを除去する際に除去される、ところの方法。
- 請求項20に記載の方法であって、工程(i)の前に基板上に低比誘電率層が形成され、複数の層が当該低比誘電率層の頂面に形成される、ところの方法。
- 請求項20に記載の方法であって、工程(i)から(iv)は少なくとも1回繰り返される、ところの方法。
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| US352357 | 1994-12-09 | ||
| US10/352,357 US7091133B2 (en) | 2003-01-27 | 2003-01-27 | Two-step formation of etch stop layer |
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| JP2004235637A true JP2004235637A (ja) | 2004-08-19 |
| JP4743470B2 JP4743470B2 (ja) | 2011-08-10 |
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| JP2021002556A (ja) * | 2019-06-20 | 2021-01-07 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、およびプログラム |
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| US6940173B2 (en) * | 2003-01-29 | 2005-09-06 | International Business Machines Corporation | Interconnect structures incorporating low-k dielectric barrier films |
| US7067437B2 (en) * | 2003-09-12 | 2006-06-27 | International Business Machines Corporation | Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same |
| US20050100682A1 (en) * | 2003-11-06 | 2005-05-12 | Tokyo Electron Limited | Method for depositing materials on a substrate |
| US7892972B2 (en) * | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
| US7956465B2 (en) * | 2006-05-08 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistivity in interconnect structures of integrated circuits |
| US7919862B2 (en) | 2006-05-08 | 2011-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistivity in interconnect structures of integrated circuits |
| US8292698B1 (en) * | 2007-03-30 | 2012-10-23 | Lam Research Corporation | On-line chamber cleaning using dry ice blasting |
| US8242016B2 (en) * | 2007-05-14 | 2012-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for reducing copper line resistivity |
| US7833893B2 (en) * | 2007-07-10 | 2010-11-16 | International Business Machines Corporation | Method for forming conductive structures |
| EP2277194A1 (en) * | 2008-05-08 | 2011-01-26 | Basf Se | Layered structures comprising silicon carbide layers, a process for their manufacture and their use |
| US20100104770A1 (en) * | 2008-10-27 | 2010-04-29 | Asm Japan K.K. | Two-step formation of hydrocarbon-based polymer film |
| US20100252930A1 (en) * | 2009-04-01 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Improving Performance of Etch Stop Layer |
| US8889235B2 (en) * | 2009-05-13 | 2014-11-18 | Air Products And Chemicals, Inc. | Dielectric barrier deposition using nitrogen containing precursor |
| US10319872B2 (en) * | 2012-05-10 | 2019-06-11 | International Business Machines Corporation | Cost-efficient high power PECVD deposition for solar cells |
| US9425093B2 (en) * | 2014-12-05 | 2016-08-23 | Tokyo Electron Limited | Copper wiring forming method, film forming system, and storage medium |
| US10032674B2 (en) * | 2015-12-07 | 2018-07-24 | International Business Machines Corporation | Middle of the line subtractive self-aligned contacts |
| KR20230100631A (ko) | 2021-12-28 | 2023-07-05 | 에이에스엠 아이피 홀딩 비.브이. | 고주파 전력을 갖는 저 유전율 재료 층을 형성하는 방법, 상기 층을 포함하는 구조, 및 이를 형성하기 위한 시스템 |
| WO2025170783A1 (en) * | 2024-02-07 | 2025-08-14 | Applied Materials, Inc. | Control of topology at trench bottom or selective removal of deposited film from top of fin |
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| US20040147115A1 (en) | 2004-07-29 |
| US7091133B2 (en) | 2006-08-15 |
| JP4743470B2 (ja) | 2011-08-10 |
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