JP2006114709A - ESD protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protection device for a semiconductor device having a protection function for protecting a gate insulating film from ESD (surge).
A protection transistor is connected between an electrode on the VCC terminal 13 side or a GND terminal 12 side and a gate electrode of an output transistor (6a, 6b) in an ESD protection circuit having a divided GND line and power supply line. Furthermore, by providing a delay circuit (31a, 31b) and a resistor (32a, 32b) on the gate electrode side of the protection transistor (30a, 30b), a negative voltage is applied to the output transistor (6a, 6b). Even in such a case, voltage can be applied to the gate electrodes of the output transistors (6a, 6b), the drain current can be discharged, and the gate insulating film can be prevented from being broken.
[Selection] Figure 1

Description

  The present invention relates to a protection device for a semiconductor device having a protection function for protecting a gate insulating film from a surge of the semiconductor device.

  In the conventional semiconductor device, the gate insulating film may be electrostatically broken due to ESD (surge) from the outside. In order to prevent electrostatic breakdown, a protection transistor is provided in the external output terminal or the cell of the external input terminal of the semiconductor device. However, with the miniaturization of semiconductor devices, the resistance to electrostatic breakdown of external input / output terminals has been reduced, which has become a serious problem.

  In general, a MOS transistor is used as a protection transistor, and current is concentrated on the MOS transistor, thereby causing breakdown and preventing electrostatic breakdown of the date insulating film due to surge.

  FIG. 3 shows a circuit diagram of a conventional ESD protection circuit. The internal circuit 5 is composed of a plurality of FETs, and gate electrodes G of an output transistor (P-channel transistor) 6a and an output transistor (N-channel transistor) 6b are connected to the output side thereof. The internal circuit 5 is connected to the GND terminal 12 through the internal circuit GND line 9b, and is connected to the power supply terminal 13 for applying the power supply voltage VDD through the internal circuit power supply line 8b. The drain electrode D of the output transistor 6 b is connected to the external output terminal 7, the source electrode S is connected to the peripheral GND line 9 a, and the peripheral GND line 9 a is connected to the GND terminal 12. The drain electrode D of the output transistor 6 a is connected to the external output terminal 7, its source electrode S is connected to the peripheral power supply line 8 a, and the peripheral power supply line 8 a is connected to the power supply terminal 13.

  The internal circuit 5 is connected to the GND terminal 12 via the internal circuit GND line 9b, and the internal circuit 5 is further connected to the power supply terminal 13 via the internal circuit power line 8b. The output transistors 6a and 6b are gate-controlled by the output of the internal circuit 5.

In Patent Document 1, in a semiconductor integrated circuit where an internal circuit power line and / or an internal circuit GND line and / or a peripheral power line and / or a peripheral GND line are divided on a chip wiring pattern, an external GND terminal or There has been proposed a semiconductor integrated circuit capable of preventing the occurrence of a breakdown phenomenon of a gate insulating film of an output transistor connected thereto when an electrostatic surge flows into an external output terminal or an external input / output terminal with respect to an external power supply terminal.
Japanese Patent Laid-Open No. 5-291511

  However, the above invention has the following problems.

  Since breakdown does not occur unless the voltage of the protection transistor to which the negative voltage is applied reaches the breakdown voltage, the gate insulating film is destroyed by stress due to the voltage applied until the breakdown voltage is reached. Although the breakdown voltage can be lowered by shortening the gate length of the protection transistor, it is difficult in terms of circuit design to change the gate length.

  Specifically, in FIG. 3, the ESD protection circuit includes four applied patterns, when the voltage of VCC13 is increased in the positive direction (hereinafter referred to as VCC +), and when the voltage of VCC13 is increased in the negative direction (hereinafter, referred to as VCC). VCC−), when GND12 voltage is increased in the positive direction (hereinafter referred to as GND +), and GND12 voltage is increased in the negative direction (hereinafter referred to as GND−). When VCC + and GND− are applied, since a positive voltage is applied to each output transistor, a breakdown in which the drain current increases rapidly does not occur, and thus the resistance against breakdown of the gate insulating film is high.

  However, when VCC− and GND + are applied, a negative voltage is applied to each output transistor, the drain current does not flow, and when the breakdown voltage is reached, the current increases rapidly, and the gate insulating film Low resistance to destruction. When this negative voltage reaches about ± 10 V (breakdown voltage), breakdown occurs. That is, when the drain-source potential and the potential between the drain and the gate until breakdown occurs reach about ± 10 V, the gate insulating film is broken.

  Further, when VCC− is applied, the output transistor 6a becomes a negative voltage, a breakdown in which the current rapidly increases occurs, and the resistance to the breakdown of the gate insulating film is lowered. On the other hand, a positive voltage is applied to the output transistor 6b, and a breakdown in which the current increases rapidly does not occur. Therefore, the output transistor 6b has high resistance to the breakdown of the gate insulating film.

  In addition, when GND + is applied, the output transistor 6b becomes a negative voltage, a breakdown in which the current rapidly increases occurs, and resistance to breakdown of the gate insulating film is lowered. On the other hand, a positive voltage is applied to the output transistor 6a, and a breakdown in which the current increases rapidly does not occur. Therefore, the output transistor 6a is highly resistant to the breakdown of the gate insulating film.

  In the semiconductor integrated circuit described in Patent Document 1, a protection circuit is provided between the gate electrode and the peripheral power supply line side or peripheral GND line side electrode of the output transistor in the semiconductor integrated circuit having the divided GND line and power supply line. By connecting, when an electrostatic surge flows into the external output terminal or the external input / output terminal and the output transistor generates a breakdown, the protection circuit is activated and the output transistor is connected to the peripheral power supply line side or the peripheral GND line side. The potential difference between the electrode and the gate electrode is reduced. However, the gate insulating film may be destroyed by a surge until the output transistor breaks down.

  Therefore, the present invention connects a protection transistor between the VCC terminal side or GND terminal side electrode of the output transistor and the gate electrode in the ESD protection circuit having the divided GND line and power supply line, and By providing a delay circuit and a resistor on the gate electrode side of the protection transistor, even when a negative voltage is applied to the output transistor, a voltage is applied to the gate electrode of the output transistor, and the drain current is discharged. An object of the present invention is to provide an ESD protection circuit capable of preventing the gate insulating film from being broken.

  The invention according to claim 1 is gate-controlled by an internal circuit composed of a plurality of FETs, an internal circuit power supply line for supplying a power supply voltage to the internal circuit and an internal circuit ground line, and an output of the internal circuit. An output transistor that outputs a signal corresponding to the output of the internal circuit to an external output terminal or an external input / output terminal; a peripheral power supply line that is connected to the output transistor and applies a power supply voltage to the output transistor; and a peripheral ground line In the ESD protection circuit in which the internal circuit power line and the internal circuit ground line and / or the peripheral power line and / or the peripheral ground line are divided on the chip wiring, the gate electrode of the output transistor, The output transistor is connected between the peripheral power supply line or the peripheral ground line. A protection circuit for reducing a potential difference between the two electrodes before the breakdown; and the protection circuit includes a protection transistor connected between the gate electrode of the output transistor and the peripheral power supply line or the peripheral ground line. A delay circuit and a resistor are provided between the gate electrode of the protection transistor and the peripheral power supply line or the peripheral ground line.

  According to a second aspect of the present invention, in the ESD protection circuit according to the first aspect, the resistor is connected between the delay circuit and the peripheral power supply line or the peripheral ground line.

  According to a third aspect of the present invention, in the ESD protection circuit according to the first aspect, the resistor is connected between a gate electrode of the protection transistor and the delay circuit.

  According to a fourth aspect of the present invention, a plurality of first resistors, a resistor power supply line for supplying a power supply voltage to the resistors, a resistor ground line, and gates are controlled by the outputs of the resistors in accordance with the outputs of the resistors. An output transistor that outputs a signal to an external output terminal or an external input / output terminal; and a peripheral power supply line and a peripheral ground line that are connected to the output transistor and apply a power supply voltage to the output transistor; In the ESD protection circuit in which the ground line and / or the peripheral power line and / or the peripheral ground line are divided on the chip wiring, the gate electrode of the output transistor, the peripheral power line, or the peripheral ground line Before the output transistor breaks down. A protection circuit to be reduced, the protection circuit including the protection transistor connected between the gate electrode of the output transistor and the peripheral power supply line or the peripheral ground line, and the gate electrode of the protection transistor and the peripheral power supply line. Alternatively, a delay circuit and a second resistor are provided between the peripheral ground line and the peripheral ground line.

  The invention according to claim 5 is the ESD protection circuit according to claim 4, wherein the second resistor is connected between the delay circuit and the peripheral power supply line or the peripheral ground line. .

  According to a sixth aspect of the invention, in the ESD protection circuit according to the fourth aspect, the second resistor is connected between the gate electrode of the protection transistor and the delay circuit.

  According to a seventh aspect of the present invention, in the ESD protection circuit according to any one of the first to sixth aspects, the delay circuit is a CR delay circuit.

  According to the present invention, a protection transistor is connected between the VCC terminal side or GND terminal side electrode of an output transistor and a gate electrode in an ESD protection circuit having a divided GND line and power supply line, and the protection transistor By providing a delay circuit and a resistor on the gate electrode side, even if a negative voltage is applied to the output transistor, a voltage is applied to the gate electrode of the output transistor, the drain current is discharged, and the gate insulation The film can be prevented from being broken.

  FIG. 1 is a circuit diagram of an ESD protection circuit according to an embodiment of the present invention.

  The ESD protection circuit according to the embodiment of the present invention includes an internal circuit 5 composed of a plurality of FETs, and an output transistor (P channel transistor) 6a and an output transistor (N channel transistor) are provided on the output side. 6b gate electrodes G are connected to each other. The internal circuit 5 is connected to the GND terminal 12 through the internal circuit GND line 9b, and is connected to the power supply terminal 13 for applying the power supply voltage VDD through the internal circuit power supply line 8b. The drain electrode D of the output transistor 6 b is connected to the external output terminal 7, the source electrode S is connected to the peripheral GND line 9 a, and the peripheral GND line 9 a is connected to the GND terminal 12. The drain electrode D of the output transistor 6 a is connected to the external output terminal 7, its source electrode S is connected to the peripheral power supply line 8 a, and the peripheral power supply line 8 a is connected to the power supply terminal 13.

  This ESD protection circuit is different from the conventional circuit in that protection is provided between each gate electrode G of the output transistor (N-channel type transistor) 6a and output transistor (P-channel type transistor) 6b, the peripheral GND line, and the peripheral power supply line. Transistors 30a and 30b (P-channel type transistors and N-channel type transistors), a delay circuit, and resistors (32a and 32b) are connected.

  First, the operation when VCC- is applied will be described. When VCC− is applied, a negative voltage is applied to the output transistor 6a. Therefore, no current flows through the output transistor 6a until breakdown occurs. On the other hand, a positive voltage is applied to the output transistor 6b, and the drain current flows from the drain electrode D through the source electrode S to the GND 12.

  In the protection transistor (N-channel transistor) 30a, the source electrode S is connected to the GND terminal 12, the gate electrode G is connected to the GND terminal 12 through the delay circuit 31a and the resistor 32a, and the drain electrode D is connected to the gate electrode G of the output transistor 6a. Connected. Here, the current that flows from the output transistor 6b to the GND terminal 12 flows to the gate electrode G and the source electrode S of the protection transistor 30a. However, a resistor 32a and a delay circuit 31a (for example, a CR delay circuit) exist between the GND terminal 12 and the gate electrode G of the protection transistor 30a. Therefore, a low current flows to the gate electrode G later than the source electrode S.

  Therefore, the protection transistor 30a causes a current to flow temporarily, and VCC− is applied to the gate electrode G of the output transistor 6a. As a result, the output transistor 6a starts to flow current before breakdown.

  By adding the protection transistor 30a (N-channel transistor) described above, it is possible to prevent the gate insulating film of the output transistor 6a from being broken.

  The operation when GND + is applied will be described. When GND + is applied, a negative voltage is applied to the output transistor 6b. Therefore, no current flows through the output transistor 6b until breakdown occurs. On the other hand, a positive voltage is applied to the output transistor 6a, and the drain current flows from the drain electrode D through the source electrode S to the VCC terminal 13.

  In the protection transistor (P-channel transistor) 30b, the source electrode S is connected to the VCC terminal 13, the gate electrode G is connected to the VCC terminal 13 via the delay circuit 31b and the resistor 32b, and the drain electrode D is connected to the gate electrode G of the output transistor 6b. Connected. Here, the current that flows from the output transistor 6a to the VCC terminal 13 flows to the gate electrode G and the source electrode S of the protection transistor 30b. However, a resistor 32b and a delay circuit 31b (for example, a CR delay circuit) exist between the VCC terminal 13 and the gate electrode G of the protection transistor 30b. Therefore, a low current flows to the gate electrode G later than the source electrode S.

  For this reason, the protection transistor 30b temporarily passes a current, and GND + is applied to the gate electrode G of the output transistor 6b. As a result, the output transistor 6b applies a voltage to the gate electrode and starts flowing a current before breakdown.

  The protection transistors 30a and 30b do not always adversely affect the function of the ESD protection circuit because current does not always flow when current flows through the output transistors 6a and 6b.

  FIG. 2 shows a circuit configuration when there is no internal circuit 5 for controlling the gate electrode G of the output transistors (6a, 6b). When the internal circuit 5 does not exist, the gate electrode G of the output transistor (6a, 6b) is not directly attached to the VCC terminal 13 or the GND terminal 12, but via a resistor like the resistor (33a, 33b) in the figure. Connecting. At this time, the resistance connected to the output transistor 6a is made larger than the resistances (32a, 32b) connected to the protection transistor 6b. Thereby, a difference arises in the voltage applied to the gate electrode G of the output transistor (6a, 6b) from the protection transistor (30a, 30b), and the protection transistor (30a, 30b) can be driven more efficiently.

It is a circuit diagram of an ESD protection circuit according to an embodiment of the present invention. It is a circuit diagram of an ESD protection circuit according to an embodiment of the present invention. It is a circuit diagram of the conventional ESD protection circuit.

Explanation of symbols

5 Internal circuit 6a, 6b Output transistor 7 External output terminal 8a, 8b Peripheral power supply line 9a, 9b Peripheral GND line 12 GND terminal 13 VCC terminal 30a, 30b Protection transistor 31a, 31b Delay circuit

Claims (7)

An internal circuit composed of a plurality of FETs, an internal circuit power supply line for supplying a power supply voltage to the internal circuit and an internal circuit ground line, and gate-controlled by the output of the internal circuit in accordance with the output of the internal circuit An output transistor that outputs a signal to an external output terminal or an external input / output terminal; and a peripheral power supply line and a peripheral ground line that are connected to the output transistor and apply a power supply voltage to the output transistor; In the ESD protection circuit in which the internal circuit ground line and / or the peripheral power supply line and / or the peripheral ground line are divided on the chip wiring,
A protection circuit for reducing a potential difference between the two electrodes before the output transistor breaks down between the gate electrode of the output transistor and the peripheral power supply line or the peripheral ground line;
The protection circuit is
The protection transistor connected between the gate electrode of the output transistor and the peripheral power supply line or the peripheral ground line;
An ESD protection circuit comprising a delay circuit and a resistor between a gate electrode of the protection transistor and the peripheral power supply line or the peripheral ground line.   2. The ESD protection circuit according to claim 1, wherein the resistor is connected between the delay circuit and the peripheral power supply line or the peripheral ground line.   2. The ESD protection circuit according to claim 1, wherein the resistor is connected between a gate electrode of the protection transistor and the delay circuit. A plurality of first resistors, a resistor power supply line and a resistor ground line for supplying a power supply voltage to the resistors, and a signal that is gate-controlled by the outputs of the resistors and that corresponds to the outputs of the resistors are input to an external output terminal or an external input. An output transistor that outputs to an output terminal; and a peripheral power supply line and a peripheral ground line that are connected to the output transistor and apply a power supply voltage to the output transistor, the resistor power supply line, the resistor ground line, and the peripheral power supply line In the ESD protection circuit in which both and / or the peripheral ground line are divided on the chip wiring,
A protection circuit for reducing a potential difference between the two electrodes before the output transistor breaks down between the gate electrode of the output transistor and the peripheral power supply line or the peripheral ground line;
The protection circuit is
The protection transistor connected between the gate electrode of the output transistor and the peripheral power supply line or the peripheral ground line;
An ESD protection circuit comprising a delay circuit and a second resistor between a gate electrode of the protection transistor and the peripheral power supply line or the peripheral ground line.   5. The ESD protection circuit according to claim 4, wherein the second resistor is connected between the delay circuit and the peripheral power supply line or the peripheral ground line.   The ESD protection circuit according to claim 4, wherein the second resistor is connected between a gate electrode of the protection transistor and the delay circuit.   7. The ESD protection circuit according to claim 1, wherein the delay circuit is a CR delay circuit.

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