JP2006190868A - Semiconductor memory device - Google Patents

Abstract

To provide a semiconductor memory device capable of miniaturization (high integration) of an element, a stable and high-speed memory operation with high reliability, and capable of storing and storing 2 bits or more.
First and second diffusion layer regions 17 and 18 are formed on a semiconductor substrate 10 and a channel formation region 31 is formed so as to connect the first and second diffusion layer regions 17 and 18. . A gate insulating film 12 is formed on the channel formation region 31, and a gate electrode 13 is formed on the gate insulating film 12. Further, charge holding bodies 61 and 62 are formed on the side walls on both sides of the gate insulating film 12 and the gate electrode 13. Carbon nanotubes are used for the channel formation region 31.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a field effect transistor having a function of converting a change in charge amount into a current amount.

  Conventionally, as a semiconductor memory device, there is a non-volatile memory capable of storing 2 bits with one field effect transistor, and this non-volatile memory has been developed by Cyphan Semiconductors Ltd. Table 2001-512290 publication (patent document 1) reference). The structure of the above prior art memory and the write operation principle will be described below.

  As shown in FIG. 9, the semiconductor memory device includes a gate electrode 909 formed on a P-type well region 901 via a gate insulating film, and a first N-type diffusion layer formed on the surface of the P-type well region 901. A region 902 and a second N-type diffusion layer region 903 are formed. The gate insulating film is an ONO (Oxide Nitride Oxide) film in which a silicon nitride film 906 is sandwiched between silicon oxide films 904 and 905. In the silicon nitride film 906, memory holding portions 907 and 908 are formed near the ends of the first and second N-type diffusion layer regions 902 and 903, respectively.

  By reading the amount of charge at each of the storage holding portions 907 and 908 as the drain current of the transistor, 2-bit information can be stored in one transistor.

  Next, a write operation method in this semiconductor memory device will be described. Here, writing refers to injecting electrons into the memory holding units 907 and 908. Japanese Patent Application Publication No. 2001-512290 discloses a method of applying 5.5 V to the second diffusion layer region 903 and 10 V to the gate electrode 909 in order to emit electrons accumulated in the right memory holding portion 908. Has been. Thereby, it is possible to write on a specific side of the two storage holding units 907 and 908. A method for performing erasing and reading on a specific side is also disclosed, and these methods can be combined to perform a 2-bit operation.

  However, like the above-mentioned semiconductor memory devices, memory devices based on MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) generally perform repeated read / write and erase memory operations many times. If this is done, the mobility of the channel deteriorates, the read current required for the memory operation cannot be maintained, and a reliable and stable memory operation cannot be obtained. In addition, since the gate insulating film has a three-layer structure of an ONO film in order to have both a function for operating the transistor and a function as a memory film for accumulating charges, the gate insulating film is thinned. It was difficult.

In addition, as the channel length becomes shorter, two portions of the memory holding portions 907 and 908 of one transistor interfere with each other and 2-bit operation is difficult, and further element miniaturization cannot be achieved.
JP-T-2001-512290

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of miniaturization (high integration) of an element, a highly reliable and stable high-speed memory operation, and capable of storing and storing 2 bits or more.

  In order to solve the above problems, a semiconductor memory device according to the present invention includes a multi-value memory having a plurality of charge carriers, a diffusion layer region corresponding to each of the charge carriers of the multi-value memory, and the multi-values. And a channel forming region that is connected to the diffusion layer region, and the channel forming region includes carbon nanotubes. Here, “multi-value” means a logical value of four or more values.

  According to the semiconductor memory device having the above configuration, the use of carbon nanotubes having a semiconductor property with high electrical conductivity and thermal conductivity in the channel formation region enables miniaturization of elements (high integration) and high reliability. A stable high-speed memory operation can be obtained. Since the current flowing through the carbon nanotube flows almost without resistance due to the tunnel effect, it is possible to speed up the memory operation of reading / writing and erasing of the semiconductor memory device, and by repeating the memory operation many times, Even when mobility deterioration occurs, a read current necessary for the memory operation can be maintained, and a stable memory operation with a long lifetime and high reliability can be obtained. In addition, the current flowing in the carbon nanotube is the same as or lower than the conventional channel resistance, and represents the influence of the charge held in the charge holding body, and can easily determine the presence or absence of charge, Suitable for multi-value nonvolatile memory.

  Further, according to the semiconductor memory device having the above structure, by providing the channel formation region on the insulator or the insulator film, the leakage current can be suppressed as compared with the case where the channel formation region is formed on the semiconductor substrate. The power saving effect can be obtained. Further, since complete element isolation can be performed and the capacitance of the diffusion layer region can be reduced, integration density and operation speed can be improved.

  In one embodiment, the multilevel memory includes a gate insulating film formed on a substrate and a gate electrode formed on the gate insulating film, and a sidewall of the gate electrode. Two charge holding bodies of the multi-value storage body are formed on both sides of the two, and the two diffusion layer regions correspond to the two charge holding bodies, respectively.

  The semiconductor memory device of the above embodiment has almost the same structure as a conventional sidewall type transistor, and can be manufactured by a conventional manufacturing method. In addition, the two diffusion layer regions that are structurally separated by the gate electrode are separated by the gate electrode, so miniaturization is possible, the gap between the gate and the channel can be shortened, and a high electric field can be applied to the channel at a low voltage. It is.

  In one embodiment of the semiconductor memory device, the charge holding body includes a first insulator having a function of accumulating charges, and a second insulator disposed so as to sandwich the first insulator from both sides. And a third insulator, wherein the first insulator is silicon nitride or aluminum oxide, and the second and third insulators are silicon oxide.

  According to the semiconductor memory device of the above embodiment, the silicon nitride (or aluminum oxide) used for the first insulator having the function of accumulating charges has a level for trapping charges (electrons and holes). Since there are many, a large hysteresis characteristic can be obtained, and it is a substance often used in the manufacturing process of semiconductor devices. Further, by using silicon oxide for the second and third insulators, leakage of charges accumulated in silicon nitride (or aluminum oxide) is prevented, and the charge holding body has a sandwich structure. Therefore, the charge injection efficiency is increased, and the rewriting operation can be speeded up.

  As can be seen from the above, according to the semiconductor memory device of the present invention, the use of carbon nanotubes with high electrical conductivity and high thermal conductivity in the channel formation region enables miniaturization (high integration) and reliability of the device. High and stable high-speed memory operation can be obtained.

  In addition, since the current flowing through the carbon nanotube flows almost without resistance due to the tunnel effect, it is possible to speed up the memory operation of reading / writing and erasing of the semiconductor memory device, and by repeating the memory operation many times. Even when channel mobility is deteriorated, a read current necessary for memory operation can be maintained, and a stable memory operation with a long lifetime and high reliability can be obtained.

  In addition, the current flowing in the carbon nanotube represents the influence of the charge held in the charge holding body, so that the presence / absence of charge can be easily determined, which is suitable for a multi-value nonvolatile memory.

  In addition, by using a semiconductor whose electron mobility is higher than that of silicon in the channel formation region, channel mobility is deteriorated due to repeated read / write and erase memory operations. However, the read current necessary for the memory operation can be maintained, and a reliable and long-life and stable memory operation can be obtained.

  Further, in the semiconductor memory device of the present invention, the current difference (current difference between the read current after writing and the read current after erasing) as much as possible can be easily maintained so that it can be easily discriminated after writing or after erasing. Therefore, when a memory is manufactured on a large area substrate, manufacturing variations occur in the plane, and even if there is a variation in memory performance of read current values after writing and erasing, even after writing and erasing necessary for memory operation Since the read current difference can be obtained, the yield can be improved and the productivity can be improved. Further, by providing the channel region over the insulator substrate, complete element isolation can be performed and the capacity of the diffusion layer region can be reduced, so that the integration density and the operation speed can be improved.

  In addition, a semiconductor device manufactured on an insulator substrate such as a conventional thin film transistor (TFT) has a problem of low mobility because amorphous silicon or polysilicon is used for a channel formation region. A semiconductor device capable of high-speed operation can be manufactured over an insulator substrate by using carbon nanotubes (or a semiconductor whose electron mobility is higher than that of silicon electrons) in the channel formation region. .

  In addition, the semiconductor memory device of the present invention can be easily manufactured because a conventional semiconductor process can be used.

  The semiconductor memory device of the present invention will be described in detail below with reference to the illustrated embodiments. 1, FIG. 2, FIG. 4 and FIG. 5 are schematic cross-sectional views showing the structure of a semiconductor memory device according to an embodiment of the present invention. The first embodiment shown in FIG. 1 and the second embodiment shown in FIG. On the semiconductor substrate, the third embodiment shown in FIG. 4 and the fourth embodiment shown in FIG. 5 are configured on an insulator substrate. FIGS. 1 and 2, FIG. 4 and FIG. The structure of the charge holding body formed on both sides is different.

(First embodiment)
The semiconductor memory device shown in FIG. 1 according to the first embodiment of the present invention is a non-volatile memory cell capable of storing 2 bits, as shown in FIG. A source / drain region) 17 and a second diffusion layer region (source / drain region) 18 are formed. A channel forming region 31 is formed so as to connect the first diffusion layer region 17 and the second diffusion layer region 18. A gate insulating film 12 is formed on the channel formation region 31, and a gate electrode 13 having a gate length comparable to that of a normal transistor is formed on the gate insulating film 12. Further, charge holding bodies 61 and 62 are formed on the side walls on both sides of the gate insulating film 12 and the gate electrode 13. Further, the first and second diffusion layer regions (source / drain regions) 17 and 18 are offset from the end of the gate electrode 13 (from the region 41 where the gate electrode 13 is formed).

  The charge holding bodies 61 and 62, the gate insulating film 12 and the gate electrode 13 constitute a multi-value storage body.

  As described above, the charge holding bodies 61 and 62 of the semiconductor memory device are formed independently of the gate insulating film 12. Therefore, the memory function performed by the charge holding bodies 61 and 62 and the transistor operation function performed by the gate insulating film 12 are separated. Further, since the two charge holding bodies 61 and 62 formed on both sides of the gate electrode 13 are separated by the gate electrode 13, interference during rewriting is effectively suppressed. Therefore, this semiconductor memory device can store 2 bits and can be easily miniaturized.

  In addition, since the first and second diffusion layer regions (source / drain regions) 17 and 18 are offset from the gate electrode 13, they are under the charge holding bodies 61 and 62 when a voltage is applied to the gate electrode 13. The ease of inversion of the offset region 42 can be greatly changed by the amount of charges accumulated in the charge holding bodies 61 and 62, and the memory effect can be increased. Further, compared with a normal logic transistor, the short channel effect can be strongly prevented, and the gate length can be further miniaturized. In addition, since it is structurally suitable for suppressing the short channel effect, it is possible to employ a gate insulating film that is thicker than a logic transistor, and it is possible to improve reliability.

  In addition, by using carbon nanotubes (or a semiconductor in which the mobility of electrons with respect to carbon nanotubes is higher than that of silicon electrons) in the channel formation region 31, high-speed operation of the memory becomes possible, and read / write and erase operations are possible. Even when channel mobility is deteriorated due to repeated operations, the read current necessary for the memory operation can be maintained, and a stable and reliable memory operation with a long lifetime can be obtained.

  In a conventional semiconductor memory device, when read / write and erase memory operations are repeated 100,000 times or more, the read current is not maintained, and the read current value after erase and the current value after write are discriminated. There was a phenomenon that became difficult. On the other hand, carbon nanotubes with semiconductor characteristics, and silicon germanium (SiGe), indium phosphide (InP), gallium arsenide (GaAs), gallium antimony (GaSb), indium whose electron mobility is higher than that of silicon. By using a semiconductor film in which a semiconductor such as antimony (InSb) is combined in the channel formation region, the read current necessary for the memory operation is maintained even after the memory operation is repeated 100,000 times or more. It is possible to easily determine whether it has been erased.

  Further, in the semiconductor memory device of the present invention, the current difference (current difference between the read current after writing and the read current after erasing) that can easily determine whether it is after writing or after erasing is sufficiently retained. When memory is fabricated on a large-area chip, fabrication variations occur in-plane, and even if there is a variation in memory performance of read current values after writing and erasing, reading after writing and erasing necessary for memory operation Since a current difference can be obtained, yield is improved and productivity can be improved. In addition, the use of carbon nanotubes (or a semiconductor in which the mobility of carbon nanotubes and electrons is higher than that of silicon electrons) in the channel formation region enables high-speed operation of the memory, which is lower than conventional semiconductor memory devices. Since the read / write and erase memory operations equivalent to those of a conventional semiconductor memory device can be performed with a voltage, power consumption can be reduced.

  In the method of manufacturing a semiconductor memory device of the present invention, carbon nanotubes are arranged on the entire surface of a substrate, and the carbon nanotube is covered with an oxide film, and then manufactured by the same method as that of a normal sidewall type transistor. Further, when the carbon nanotube itself has an insulating layer as the outermost layer, it is not necessary to cover it with an oxide film. As a method for arranging the carbon nanotubes, there is a method in which the produced carbon nanotubes are purified, mixed in a liquid such as acetone, and then applied onto a substrate.

  Further, the side wall spacer-shaped charge carriers 61 and 62 have a structure including a silicon nitride film (or aluminum oxide film) 21 having a side wall shape and a silicon oxide film 14 as shown in FIG. Yes. The silicon nitride film (or aluminum oxide film) 21 is separated from the gate electrode 13, the channel formation region 31 and the first and second diffusion layer regions (source / drain regions) 17 and 18 by the silicon oxide film 14. . It is the silicon nitride film (or aluminum oxide film) 21 that has a function of accumulating charges (electrons or holes) in the charge holding bodies 61 and 62, and the silicon nitride film (or aluminum oxide film) stores charges. Since there are many trapping levels, a large hysteresis characteristic can be obtained. The silicon oxide film 14 prevents leakage of charges accumulated in the silicon nitride film (or aluminum oxide film) 21. It is a portion of the silicon nitride film (or aluminum oxide film) 21 that exists on the offset region 42 that mainly accumulates charges.

(Second Embodiment)
The semiconductor memory device shown in FIG. 2 of the second embodiment of the present invention has the same configuration as that of the semiconductor memory device of the first embodiment except for the charge holding body, and the same components are denoted by the same reference numerals. The description is omitted.

  As shown in FIG. 2, the side wall spacer-shaped charge carriers 71 and 72 have a structure in which a silicon nitride film (or aluminum oxide film) 21 is sandwiched between silicon oxide films 14 and 16. As described above, since the charge holding bodies 71 and 72 are sandwiched between the silicon oxide films 14 and 16 because the silicon nitride film (or aluminum oxide film) 21 is sandwiched between the charge holding bodies 71 and 72, Blocked by the oxide film 16, the charge injection efficiency into the silicon nitride film (or aluminum oxide film) 21 is increased, the rewriting operation (writing and erasing operation) is speeded up, the reliability is improved, and the sufficient holding time is obtained. Securement is possible. Since silicon nitride, aluminum oxide, and silicon oxide are used as materials for semiconductor devices, they can be manufactured using conventional semiconductor processes.

  3 is a perspective view of the semiconductor memory device. In FIG. 3, reference numeral 31 schematically shows a channel formation region made of carbon nanotubes.

(Third embodiment)
The semiconductor memory device shown in FIG. 4 according to the third embodiment of the present invention has a first diffusion layer on the insulator substrate 11 as a nonvolatile memory cell capable of storing 2 bits, as shown in FIG. A region 17 (source / drain region), a second diffusion layer region 18 (source / drain region), and a channel formation region 31 are formed. A gate insulating film 12 is formed on the channel formation region 31, and a gate electrode 13 having a gate length similar to that of a normal transistor is formed on the gate insulating film 12. In addition, charge holding bodies 61 and 62 are formed on the side walls on both sides of the gate insulating film 12 and the gate electrode 13. The first and second diffusion layer regions (source / drain regions) 17 and 18 are offset from the end of the gate electrode 13 (from the region 41 where the gate electrode 13 is formed). That is, what is configured on the semiconductor substrate 10 as shown in FIGS. 1 and 2 of the first and second embodiments is configured on the insulator substrate 11 in FIG.

  Thus, by providing the channel formation region 31 on the insulator substrate 11, complete element isolation can be performed and the capacitance of the diffusion layer region can be reduced, so that the integration density and the operation speed can be improved. In addition, leakage current can be suppressed and power consumption can be reduced as compared with the case where a channel formation region is formed over a semiconductor substrate. In addition, since a semiconductor device manufactured on an insulator substrate like a conventional TFT (Thin Film Transistor) uses amorphous silicon or polysilicon for a channel formation region, there is a problem that mobility is low. , A semiconductor device capable of high-speed operation is manufactured over a large-area insulator substrate by using carbon nanotubes (or a semiconductor in which the mobility of electrons with carbon nanotubes is higher than that of silicon electrons) in the channel formation region It is possible.

(Fourth embodiment)
The semiconductor memory device shown in FIG. 5 of the fourth embodiment of the present invention has the same configuration as that of the semiconductor memory device of the third embodiment except for the charge holding body, and the same components are denoted by the same reference numerals. The description is omitted.

  As shown in FIG. 5, the side wall spacer-shaped charge carriers 71 and 72 have a structure in which a silicon nitride film (or aluminum oxide film) 21 is sandwiched between silicon oxide films 14 and 16.

  The operation principle of the semiconductor memory device having the above structure will be described with reference to FIGS. 6A to 8B. 6A to 8B show the case of the semiconductor memory device having the charge holding body shown in FIG. 5, but the present invention can also be applied to a semiconductor memory device having charge carriers of other shapes.

  When the semiconductor memory device is an N-channel type, the channel formation region 31 has a P-type, and the diffusion layer regions 17 and 18 have an N-type conductivity type. Is the opposite. In the following description (including a description of a reading method and an erasing method), the case where the semiconductor memory device is an N-channel type will be described. However, in the case of a P-channel type, the roles of electrons and holes may be reversed. In the case of the P-channel type, all the signs of the voltages applied to the nodes may be reversed.

  First, a first writing method of the semiconductor memory device will be described with reference to FIGS. 6A and 6B. Note that writing refers to injecting electrons into the charge holding body when the semiconductor memory device is an N-channel type, and injecting holes into the charge holding body when the semiconductor memory device is a P-channel type. I will do it.

  The first writing method of this semiconductor memory device is performed by injecting electrons accelerated by the drain electric field into the charge holding bodies 71 and 72.

  In order to inject (write) electrons into the second charge holding body 72, as shown in FIG. 6A, the first diffusion layer region 17 is used as a source electrode, and the second diffusion layer region 18 is used as a drain electrode. To do. For example, 0 V may be applied to the first diffusion layer region 17, +5 V may be applied to the second diffusion layer region 18, and +5 V may be applied to the gate electrode 13. Under such a voltage condition, the inversion layer 32 extends from the first diffusion layer region 17 (source electrode), but a pinch-off point is generated without reaching the second diffusion layer region 18 (drain electrode). . The electrons are accelerated by the drain electric field from the pinch-off point to the second diffusion layer region 18 (drain electrode), and the second charge holding body 72 (or more precisely, the silicon nitride film (or the second charge holding body 72 in the second charge holding body 72). The aluminum oxide film 21) is injected and writing is performed. In the vicinity of the first charge holding body 71, electrons accelerated by the drain electric field are not generated, and thus writing is not performed. Note that the voltage for the write operation is not limited to the above. For example, even when 0 V is applied to the first diffusion layer region 17, +10 V is applied to the second diffusion layer region 18, and +5 V is applied to the gate electrode 13, Writing was performed by injecting hot electrons (thermoelectrons) into the charge holding body 72.

  In this way, writing can be performed by injecting electrons into the second charge holding body 72.

  On the other hand, in order to inject (write) electrons into the first charge carrier 71, as shown in FIG. 6B, the second diffusion layer region 18 is used as the source electrode, and the first diffusion layer region 17 is used as the drain. The electrode. For example, 0 V may be applied to the second diffusion layer region 18, +5 V to the first diffusion layer region 17, and +5 V to the gate electrode 13. As described above, when electrons are injected into the second charge holding body 72, the first charge holding body 71 is replaced by replacing the first and second diffusion layer regions (source / drain regions) 17 and 18. Writing can be performed by injecting electrons.

  Next, a second writing method of the semiconductor memory device will be described with reference to FIGS. 7A and 7B.

  In order to inject (write) electrons into the second charge holding body 72 by the second writing method, as shown in FIG. 7A, the first diffusion layer region 17 is used as the source electrode, and the second The diffusion layer region 18 is used as a drain electrode. A characteristic point of the second writing method is that the potential of the channel formation region 31 is made lower than the potential of the first diffusion layer region 17. For example, 2 V may be applied to the first diffusion layer region 17, +5 V to the second diffusion layer region 18, and +5 V to the gate electrode 13. That is, one N-type diffusion layer region (first diffusion layer region 17) is set to a reference voltage, the other N-type diffusion layer region (second diffusion layer region 18) is set to a voltage higher than the reference voltage, and the gate electrode 13 Is higher than the reference voltage, and the P-type channel formation region (channel formation region 11) is lower than the reference voltage. Note that the potential applied to each node is not limited to the above, and the optimum value depends on the structure of the semiconductor memory device and the like. In addition, the potentials of the gate electrode 13 and the second diffusion layer region 18 must be higher than the potentials of the first diffusion layer region 17, respectively, but the potentials of the gate electrode 13 and the second diffusion layer region 18. The size relationship with is not questioned.

  In the second writing method, writing is performed with a very small current compared to the first writing method. In other words, the charge injection efficiency in the second writing method is much higher than that in the first writing method.

  On the other hand, in order to inject (write) electrons into the first charge holding body 71, as shown in FIG. 7B, the second diffusion layer region 18 is used as the source electrode, and the first diffusion layer region 17 is used as the drain. The electrode. For example, 2 V may be applied to the second diffusion layer region 18, +5 V to the first diffusion layer region 17, and +5 V to the gate electrode 13. As described above, when electrons are injected into the second charge holding body 72, the first charge holding body 71 is replaced by replacing the first and second diffusion layer regions (source / drain regions) 17 and 18. It is possible to write by injecting electrons into.

  According to the second writing method, electrons can be selectively injected into a desired charge holding body with very high efficiency. Therefore, the write current value can be significantly reduced, and the power consumption of the semiconductor memory device can be reduced.

  Next, the principle of read operation of the semiconductor memory device will be described (not shown).

  When reading the information stored in the first charge holding body 71, the first diffusion layer region 17 is used as a source electrode, the second diffusion layer region 18 is a drain electrode, and the transistor is operated in a saturation region. For example, 0 V may be applied to the first diffusion layer region 17, +2 V to the second diffusion layer region 18, and +3 V to the gate electrode 13. At this time, if electrons are not accumulated in the first charge holding body 71, a drain current tends to flow. On the other hand, when electrons are accumulated in the first charge holding body 71, the inversion layer is hardly formed in the vicinity of the first charge holding body 71, so that the drain current hardly flows. Therefore, the storage information of the first charge holding body 71 can be read by detecting the drain current. At this time, the presence or absence of charge accumulation in the second charge holding body 72 does not affect the drain current because the vicinity of the drain is pinched off.

  On the other hand, when information stored in the second charge holding body 72 is read, the second diffusion layer region 18 is used as a source electrode, the first diffusion layer region 17 is a drain electrode, and the transistor is operated in a saturation region. For example, 0 V may be applied to the second diffusion layer region 18, +2 V to the first diffusion layer region 17, and +3 V to the gate electrode 13. As described above, when the information stored in the first charge holding body 71 is read, the second charge holding is achieved by replacing the first and second diffusion layer regions (source / drain regions) 17 and 18. Information stored in the body 72 can be read.

  In the channel formation region (offset region 42) that is not covered by the gate electrode 13, the inversion layer disappears or is formed depending on the presence or absence of surplus electrons in the charge holding bodies 71 and 72, and as a result, a large hysteresis (change in threshold value). Is obtained. However, if the width of the offset region 42 is too large, the drain current is greatly reduced, and the reading speed is greatly reduced. Therefore, it is preferable to determine the width of the offset region 42 so that sufficient hysteresis and reading speed can be obtained.

  Further, when the first and second diffusion layer regions 17 and 18 reach the end of the gate electrode 13, that is, the first and second diffusion layer regions 17 and 18 and the gate electrode 13 overlap. Even in the case where the threshold voltage of the transistor was changed by the write operation, the parasitic resistance at the source / drain end changed greatly, and the drain current decreased greatly (one digit or more). Therefore, reading can be performed by detecting the drain current, and a function as a memory can be obtained.

  Next, an erasing method of the semiconductor memory device will be described with reference to FIGS. 8A and 8B.

  First, when erasing information stored in the second charge holding body 72, a positive voltage (for example, +5 V) is applied to the second diffusion layer region 18 as shown in FIG. A reverse bias may be applied to the PN junction between the region 18 and the channel formation region 31, and a negative voltage (for example, −5 V) may be applied to the gate electrode 13. At this time, in the vicinity of the gate electrode 13 in the PN junction, the potential gradient is particularly steep due to the influence of the gate electrode 13 to which a negative voltage is applied. Therefore, a hole (hole) is generated on the channel formation region 31 side of the PN junction due to the band-to-band tunnel. This hole is drawn toward the gate electrode 13 having a negative potential, and as a result, the hole is injected into the second charge holding body 72. In this manner, the second charge holding body 72 is erased. At this time, 0 V may be applied to the first diffusion layer region 17.

  In the first erasing method, when the information stored in the first charge holding body 71 is erased, the potentials of the first diffusion layer region 17 and the second diffusion layer region 18 may be switched in the above ( FIG. 8B).

  In the above operation method, writing and erasing of 2 bits per transistor are performed by switching the source electrode and the drain electrode. However, the source electrode and the drain electrode may be fixed and operated as a 1-bit memory. In this case, one of the first and second diffusion layer regions (source / drain regions) can be set to a common fixed voltage, and is connected to the first and second diffusion layer regions (source / drain regions). The number of bit lines can be halved.

  According to the semiconductor memory devices of the first to fourth embodiments, the charge holding body is formed on both sides of the gate electrode independently of the gate insulating film, and a 2-bit operation is possible. Furthermore, since each charge holding body is separated by the gate electrode, interference during rewriting is effectively suppressed. In addition, since the memory function of the charge holding body and the transistor operation function of the gate insulating film are separated, the gate insulating film can be thinned to suppress the short channel effect. Therefore, the element can be easily miniaturized.

  Further, according to the second writing method of the semiconductor memory device, electrons can be injected into the charge holding body with high efficiency. Therefore, the write current value can be significantly reduced, and the power consumption of the semiconductor memory device can be reduced.

  The semiconductor memory device according to the present invention mainly includes a multi-value memory having a plurality of charge carriers, a diffusion layer region corresponding to each of the charge carriers of the multi-value memory, and a lower side of the multi-value memory. And a channel forming region connecting the diffusion layer regions. This semiconductor memory device functions as a memory element for storing quaternary or higher information by storing binary or higher information in one charge holding body.

  The channel formation region is a film containing carbon nanotubes or a film containing a semiconductor in which the mobility of carbon nanotubes and electrons is higher than the mobility of electrons of silicon. Examples of semiconductors having higher electron mobility than silicon electron mobility include silicon germanium (SiGe), indium phosphide (InP), gallium arsenide (GaAs), gallium antimony (GaSb), and indium antimony (InSb). There is.

  A carbon nanotube is an allotrope of carbon, and has a shape in which a sheet of graphene formed by arranging and bonding each carbon atom at each vertex of a hexagon is rounded with a nano-sized diameter. Carbon nanotubes have high electrical and thermal conductivity, are physically and chemically tough, and carbon nanotubes exhibit metal or semiconductor characteristics depending on the angle and structure of graphene. Carbon nanotubes are divided into two types of carbon nanotubes that differ from each other depending on their electrical properties. That is, metallic carbon nanotubes whose current-voltage characteristics are linearly related regardless of the gate voltage, and semiconductor characteristics whose current-voltage characteristics are non-linearly influenced greatly by the gate voltage (those with a large band gap approximate to an insulator) ) Carbon nanotubes.

  The carbon nanotube used in the semiconductor memory device according to the embodiment of the present invention is a carbon nanotube having semiconductor characteristics, and the flow of electrons moving through the carbon nanotube, that is, the current is controlled by the voltage applied to the gate electrode. Such carbon nanotubes can be produced using an electric discharge method, a laser vapor deposition method, a plasma chemical vapor deposition method, a thermal chemical vapor deposition method, a vapor phase synthesis method, or the like.

Further, by using a semiconductor whose electron mobility is higher than the electron mobility 1880 [cm ² / V · s] of silicon for the channel formation region, the memory operation for reading / writing and erasing of the semiconductor memory device can be accelerated. In addition, it is possible to maintain the read current necessary for memory operation even when channel mobility is deteriorated by repeatedly performing memory operations many times. Can be obtained.

  Thus, by using carbon nanotubes with high electrical conductivity and thermal conductivity in the channel formation region, there is no increase in resistance due to downsizing of the semiconductor memory device, and heat loss, power consumption, electrical characteristic fluctuations, and charge leakage are eliminated. Thus, the device can be miniaturized (highly integrated), and a highly reliable and stable memory operation can be obtained.

  In addition, since the current flowing through the carbon nanotube flows almost without resistance, the influence of the charge held in the charge holding body is strongly expressed, and the presence / absence of the charge can be easily determined. Suitable for non-volatile memory.

  In addition, since the current difference (difference between read current after write and erase) is sufficiently retained to easily determine whether it is after writing or after erasing, when creating a memory on a large area chip, Even if manufacturing variations occur in-plane and memory performance varies after reading and erasing, the difference in reading current after writing and erasing necessary for memory operation can be obtained, so the yield is improved. Productivity can be improved.

  The semiconductor memory device of the present invention is on a semiconductor substrate as in the first and second embodiments, preferably on a first conductivity type well region formed in the semiconductor substrate, or as in the third and fourth embodiments. It is preferably formed on an insulator substrate.

  The semiconductor substrate is not particularly limited as long as it is used in a semiconductor device. For example, an elemental semiconductor such as silicon or germanium, a compound semiconductor such as GaAs, InGaAs, or ZnSe, an SOI substrate, or a multilayer SOI. Various substrates such as a substrate can be used. Among these, a silicon substrate or an SOI substrate on which a silicon layer is formed as a surface semiconductor layer is preferable. An element isolation region is preferably formed on this semiconductor substrate, and further, elements such as transistors, capacitors, resistors, etc., circuits using these elements, semiconductor devices, and interlayer insulating films are combined to form a single or multi-layer structure. It may be formed. The element isolation region can be formed by various element isolation films such as a LOCOS (Local Oxidation Of Silicon) film, a trench oxide film, and an STI (Shallow Trench Isolation) film. Furthermore, the semiconductor substrate may have a P-type or N-type conductivity type, and at least one first conductivity type (P-type or N-type) well region is formed in the semiconductor substrate. Is preferred. The impurity concentration in the semiconductor substrate and the well region can be within the range known in the art. When an SOI (Silicon on Insulator) substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, but a body region is provided under the channel formation region. You may do it.

  The insulator or oxide film is not particularly limited as long as it is usually used in a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film: an aluminum oxide film, a titanium oxide film, or the like. A single-layer film or a laminated film of a high dielectric film such as a tantalum oxide film or a hafnium oxide film, a carbon nanotube insulating layer, or the like can be used. Of these, a silicon oxide film is preferable.

  In addition, the gate electrode of the semiconductor memory device of the present invention is formed on the gate insulating film in a shape normally used for a semiconductor device. The gate electrode is not particularly limited unless otherwise specified in the embodiment, and a conductive film, for example, a metal such as polysilicon, copper or aluminum, or a refractory metal such as tungsten, titanium or tantalum. In addition, a single layer film or a laminated film such as silicide with a refractory metal can be used. The gate electrode is suitably formed to a thickness of about 10 nm to 400 nm, for example.

  The channel formation region of the semiconductor memory device of the present invention is formed under the gate electrode, but not only under the gate electrode but also under the region including the gate electrode and the outside of the gate end in the gate length direction. Yes. As described above, when there is a channel formation region that is not covered with the gate electrode, the channel formation region is preferably covered with a gate insulating film or a charge holding body described later.

  Further, the charge holding body of the semiconductor memory device of the present invention is formed on both sides of the gate electrode directly or via an insulating film, and directly on the substrate (channel forming region, via the gate insulating film or insulating film). First and second diffusion layer regions (source / drain regions)). The charge holding bodies on both sides of the gate electrode may be formed so as to cover all of the side walls of the gate electrode directly or via an insulating film, or may be formed so as to cover a part thereof. When a conductive film is used as the charge holding body, an insulating film is used so that the charge holding body does not come into direct contact with the substrate (channel formation region, first and second diffusion layer regions (source / drain region)) or the gate electrode. It is preferable to arrange via. For example, a laminated structure of a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape or the like in the insulating film, a structure in which the conductive film is disposed in a part of the side wall insulating film formed on the side wall of the gate, etc. .

  The charge holding body preferably has a sandwich structure in which a film made of a first insulator for accumulating charges is sandwiched between a film made of a second insulator and a film made of a third insulator. Since the first insulator for accumulating charges is in the form of a film, the charge density in the first insulator can be increased and the charge density can be made uniform in a short time by the injection of charges. If the charge distribution in the first insulator that accumulates the charge is non-uniform, the charge may move through the first insulator during holding, and reliability may be reduced. Further, since the first insulator for accumulating charges is separated from the conductor portion (gate electrode, diffusion layer region, channel formation region) by another insulating film, leakage of charges is suppressed and sufficient. Retention time can be obtained. Therefore, in the case of having the sandwich structure, it is possible to rewrite the semiconductor memory device at high speed, improve reliability, and ensure a sufficient holding time. As the charge holding body satisfying the above conditions, it is particularly preferable that the first insulator is a silicon nitride film (or aluminum oxide film) and the second and third insulators are silicon oxide films. Since the silicon nitride film (or aluminum oxide film) has many levels for trapping charges, a large hysteresis characteristic can be obtained. In addition, both the silicon oxide film and the silicon nitride film are preferable because they are materials that are extremely used in a semiconductor process. The second and third insulators may be different materials or the same material.

  In addition, the first and second diffusion layer regions (source / drain regions) of the semiconductor memory device of the present invention serve as diffusion layer regions having a conductivity type opposite to that of the semiconductor substrate (or well region). Located on each side. The junction between the first and second diffusion layer regions (source / drain regions) and the semiconductor substrate (or well region) preferably has a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and a high-speed operation can be performed at a lower voltage. The junction depths of the first and second diffusion layer regions (source / drain regions) are not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. . When an SOI substrate is used as the semiconductor substrate, the first and second diffusion layer regions (source / drain regions) may have a junction depth smaller than the film thickness of the surface semiconductor layer. It is preferable that the junction depth is approximately the same as the film thickness of the surface semiconductor layer.

  The first and second diffusion layer regions (source / drain regions) may be disposed so as to overlap the gate electrode end, may be disposed so as to coincide with the gate electrode end, It may be arranged offset with respect to the gate electrode end. In particular, when offset is applied, when a voltage is applied to the gate electrode, the ease of inversion of the offset region under the charge holding body greatly varies depending on the amount of charge accumulated in the charge holding body, and the memory effect is improved. This is preferred because it increases and leads to a reduction in the short channel effect. However, if the offset is too much, the drive current between the source and the drain becomes extremely small. Therefore, the offset amount is larger than the thickness of the charge holding member in the direction parallel to the gate length direction, that is, one gate electrode end in the gate length direction. It is preferable that the distance from the source to the nearer source / drain region is shorter. Of particular importance is that at least a portion of the charge storage region in the charge carrier is a portion of the first and second diffusion layer regions (source / drain regions) that are the first and second diffusion layer regions. It is overlapping. The essence of the semiconductor memory device of the present invention is that an electric field across the charge holding body is caused by a voltage difference between the gate electrode existing only on the side wall portion of the charge holding body and the first and second diffusion layer regions (source / drain regions). This is because the memory is rewritten.

  In addition, a part of the first and second diffusion layer regions (source / drain regions) may be extended to a position higher than the lower surface of the gate insulating film. In this case, the conductive film integrated with the first and second diffusion layer regions is laminated on the first and second diffusion layer regions formed in the semiconductor substrate. Is appropriate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-described metals, refractory metals, and the like. Of these, polysilicon is preferable. Since polysilicon has a very high impurity diffusion rate compared to a semiconductor substrate, it is easy to reduce the junction depth of the first and second diffusion layer regions in the semiconductor substrate and suppress the short channel effect. It is because it is easy to do. In this case, it is preferable that a part of the first and second diffusion layer regions is arranged so as to sandwich at least a part of the charge holding body together with the gate electrode.

  The semiconductor memory device of the present invention uses a single gate electrode, a source region, a drain region, and a semiconductor substrate formed on a gate insulating film as four terminals, and applies a predetermined potential to each of the four terminals. Thus, write, erase, and read operations are performed. Therefore, when the memory cell array is configured by arranging the semiconductor memory devices of the present invention in an array, each memory cell can be controlled by a single control gate, so that the number of word lines can be reduced.

  In the semiconductor memory device of the present invention, the use of carbon nanotubes having semiconductor characteristics in the channel formation region enables high-speed operation of the memory, and by repeatedly performing read / write and erase memory operations many times. Even when channel mobility is deteriorated, a read current necessary for memory operation can be maintained, and a stable memory operation with a long lifetime and high reliability can be obtained. For example, even if the read / write and erase memory operations are repeated 100,000 times or more, the read current is maintained, so that it is possible to easily determine whether the data has been written or erased.

  The semiconductor memory device of the present invention can be used for a battery-driven portable electronic device, particularly a portable information terminal. Examples of the portable electronic device include a portable information terminal, a mobile phone, and a game device.

  The structure of the charge holding body is not limited to the semiconductor memory devices of the first to fourth embodiments, and may include, for example, quantum dots having a function of accumulating charges in the charge holding body. Further, the shape of the charge holding body does not need to have a sidewall shape, and is located on both sides of the gate electrode, and a part thereof is a semiconductor substrate and first and second diffusion layer regions (source / drain regions). As long as it touches.

FIG. 1 is a schematic cross-sectional view of a main part showing a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a schematic sectional view of a main part showing a semiconductor memory device according to the second embodiment of the present invention. FIG. 3 is a perspective view of the semiconductor memory device. FIG. 4 is a schematic sectional view of an essential part showing a semiconductor memory device according to a third embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a main part showing a semiconductor memory device according to the fourth embodiment of the present invention. FIG. 6A is a schematic cross-sectional view of the main part for explaining the first writing method (injecting electrons into the second charge holding body) of the semiconductor memory device. FIG. 6B is a schematic cross-sectional view of the main part for explaining the first writing method (injecting electrons into the first charge holding body) of the semiconductor memory device. FIG. 7A is a schematic cross-sectional view of the main part for explaining a second writing method (injecting electrons into the second charge holding body) of the semiconductor memory device. FIG. 7B is a schematic cross-sectional view of an essential part for explaining a second writing method (injecting electrons into the first charge holding body) of the semiconductor memory device. FIG. 8A is a schematic cross-sectional view of the main part for explaining the erasing method (erasing information stored in the second charge holding body) of the semiconductor memory device. FIG. 8B is a schematic cross-sectional view of the main part for explaining the erasing method (erasing information stored in the first charge holding body) of the semiconductor memory device. FIG. 9 is a schematic cross-sectional view of a main part showing a conventional semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 11 ... Insulator substrate 12 ... Gate insulating film 13 ... Gate electrode 14, 16 ... Silicon oxide film 17 ... 1st diffused layer area | region 18 ... 2nd diffused layer area | region 21 ... Silicon nitride film (or aluminum oxide) film)
DESCRIPTION OF SYMBOLS 31 ... Channel formation area 32 ... Inversion layer 41 ... Area | region in which the gate electrode was formed 42 ... Offset area 61, 71 ... 1st charge holding body 62, 72 ... 2nd charge holding body

Claims (3)

A multi-value storage body having a plurality of charge holding bodies;
Diffusion layer regions respectively corresponding to the charge holding bodies of the multilevel memory;
A channel forming region disposed below the multilevel memory and connecting the diffusion layer regions;
The semiconductor memory device, wherein the channel formation region includes carbon nanotubes. The semiconductor memory device according to claim 1,
The multilevel memory includes a gate insulating film formed on a substrate, and a gate electrode formed on the gate insulating film,
Two charge holding bodies of the multilevel memory are formed on both sides of the side wall of the gate electrode,
2. The semiconductor memory device according to claim 2, wherein the two diffusion layer regions correspond to the two charge carriers. The semiconductor memory device according to claim 1 or 2,
The charge holding body includes a first insulator having a function of accumulating charges, a second insulator and a third insulator arranged so as to sandwich the first insulator from both sides. ,
The first insulator is silicon nitride or aluminum oxide;
A semiconductor memory device wherein the second and third insulators are silicon oxide.

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