JP2006209651A - Graphics hardware - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up graphics hardware drawing processing.
A graphics engine 10 that performs rendering processing using pixel data, a frame buffer 14 that stores pixel data to be supplied to the graphics engine 10 and is capable of burst transfer of the pixel data, and a frame buffer 14 A pixel cache 11 that inputs and outputs pixel data in units of tile areas whose dimensions can be changed by dividing the storage area of the frame buffer 14 into tiles, and supplies the acquired pixel data to the graphics engine 10; 11 includes a memory control device 12 that converts an address output when accessing the frame buffer 14 into a physical address of the frame buffer 14 and mediates the access. buffer Address conversion is performed so as to be within the range of 14 identical page areas.
[Selection] Figure 1

Description

  The present invention relates to graphics hardware.

In graphics hardware that performs drawing processing, when pixel data is input / output from a graphics engine to a drawing memory (hereinafter referred to as a frame buffer) at a low speed, this becomes a bottleneck for speeding up drawing.
In a memory capable of burst transfer, such as SDRAM (Synchronous Dynamic Random Access Memory), continuous data can be input / output using burst transfer. Whether the data is input / output or the continuous data is input / output by burst transfer, the waiting time until the data transfer is the same, so it is more efficient to input / output data continuously using burst transfer. Is.
For this reason, there is a case where a memory capable of burst transfer is used as a frame buffer of the graphics hardware. In that case, a system in which a memory device for pixel data (hereinafter referred to as a pixel cache) is mounted inside the graphics hardware is realized. Has been. In the pixel cache, several pieces of pixel data that are continuously input / output from / to the frame buffer are stored. The graphics engine inputs / outputs pixel data to / from the pixel cache, and the pixel cache inputs / outputs pixel data to / from the frame buffer by burst transfer.
When the pixel cache is mounted on the graphics hardware, the memory bandwidth is improved as compared with the case where the graphics engine sequentially inputs and outputs pixel data to the frame buffer.
However, when the pixel cache inputs / outputs pixel data to / from the frame buffer by burst transfer, there are not a few cases where unnecessary pixel data is transferred for graphics hardware drawing processing. There is a problem that processing is wasted.
Therefore, for example, as in the technique disclosed in Patent Document 1, a system for reducing input / output of useless pixel data between the pixel cache and the frame buffer has been proposed. Specifically, the pixel cache and the frame buffer input and output pixel data in units of areas (tile areas) obtained by dividing the screen into tiles.
In general, pixel data accessed by a graphics engine has spatial locality, and therefore, when a part of a tile area is accessed, there is a high possibility that access to the same tile will occur soon. Therefore, if the method disclosed in Patent Document 1 is used, it is possible to reduce input / output of useless pixel data.

JP 2001-249843 A

However, in the method disclosed in Patent Document 1, a tile area of pixel data is secured along a scan line (frame buffer lateral continuous access) from the upper left of the frame buffer. For this reason, when one tile area spans different pages, access to the non-contiguous space of the frame buffer occurs during pixel data input / output of that tile area, and data input / output between the pixel cache and the frame buffer occurs. There may be a delay.
In the method described in Patent Document 1, the tile area size can be dynamically changed. This change is performed based on the type of the graphics engine. However, not all graphics drawn by one type of graphics engine have the same characteristics. Therefore, it is better to determine the size of the tile area not only from the graphics engine type but also from the figure to be drawn.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to speed up graphics hardware drawing processing.

  The graphics hardware according to the present invention stores a graphics engine that performs rendering processing using pixel data, a pixel memory that stores pixel data to be supplied to the graphics engine, and capable of burst transfer of the pixel data, A pixel cache that inputs and outputs pixel data to and from the memory in units of tile areas whose dimensions can be changed by dividing the storage area of the drawing memory into tiles, and supplies the acquired pixel data to the graphics engine, and pixels A memory control device that converts an address output when the cache accesses the drawing memory into a physical address of the drawing memory and mediates the access, and the pixel data in the tile area is stored in the drawing memory. Add to fit within the same page area It is intended to be converted.

  According to the present invention, even if the size of the tile area of the drawing memory is changed, the pixel data of one tile area is stored in the range of the same page area of the drawing memory by the address conversion function of the memory control device. Thus, a delay in access to the drawing memory can be avoided, and the graphics hardware drawing process can be speeded up.

Embodiments of the present invention will be described below.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of graphics hardware 100 according to Embodiment 1 of the present invention. As shown in the figure, the graphics hardware 100 includes a graphics engine 10, a pixel cache 11, a memory control device 12, a memory (drawing memory) 13, a display device 15, and a CPU 16.
The graphics engine 10 is an engine that performs drawing processing such as output of a graphic image to a screen and input / output of pixel data. For example, the graphics engine 10 generates a two-dimensional graphic image or a three-dimensional image. There are MPEG engines that generate moving images such as a three-dimensional graphics engine and MPEG (Moving Picture Experts Group). A plurality of graphics engines 10 may be installed.
The pixel cache 11 is a high-speed memory such as an SRAM.
The memory 13 is a DRAM memory such as SDRAM or DDR-SDRAM capable of burst transfer, and includes a frame buffer (drawing memory) 14.

Next, the operation will be described.
First, an outline of the operation of the graphics hardware 100 will be described.
A part or the whole area of the memory 13 is used as a frame buffer 14, and all the pixel data used by the graphics engine 10 for drawing processing are stored in the frame buffer 14. The storage area of the frame buffer 14 is divided into a plurality of tile areas, and pixel data is stored in each tile area. This tile area can be dynamically resized.
Input / output of pixel data between the frame buffer 14 and the graphics engine 10 is performed via the pixel cache 11. The pixel cache 11 is a memory for temporarily storing pixel data, and inputs and outputs pixel data to and from the frame buffer 14 by burst transfer via the memory control device 12.
A display device 15 such as a CRT or a liquid crystal display is connected to the memory control device 12, and the memory control device 12 has a function of reading out pixel data from the frame buffer 14 and displaying it on the display device 15. Further, a device that can access the memory 13 such as a CPU 16 is connected to the memory control device 12. When a device connected to the memory control device 12 accesses the memory 13, the memory control device 12 has an address conversion function for converting addresses output from these devices into physical addresses of the memory 13. With the function of the memory control device 12, the memory 13 can perform high-speed input / output of data by burst transfer.

Next, a data input / output operation between the pixel cache 11 and the frame buffer 14 will be described.
FIG. 2 is a diagram illustrating a configuration of the pixel cache 11. The pixel cache 11 has a plurality of entries corresponding to the tile areas of the frame buffer 14. Each entry includes a control flag 21, a tile size 22 representing the size of the tile area, a tag address 23 representing the screen position (XY coordinate) of the first pixel in the tile area of the frame buffer 14, and pixel data 24 in the tile area. Consists of The control flag 21 includes a dirty flag indicating that the pixel data has been changed and an enable flag indicating that the cache entry is valid. The dirty flag is a flag managed for each block obtained by dividing the pixel data 24 in one entry. The amount of pixel data 24 that can be stored is the same for all entries, but the tile size 22 may vary between entries.

FIG. 3 is a diagram showing the correspondence between the pixel data 24 of each entry of the pixel cache 11 and the frame buffer 14. The pixel data 24 of an entry corresponding to a tile area of a certain frame buffer 14 is pixel data included in an area of which the tag address 23 is the upper left of the area on the frame buffer 14 and the size is the tile size 22.
Further, the pixel data in the tile area may be stored redundantly, for example, as a tile area 33 corresponding to entry 3 and a tile area 34 corresponding to entry X shown in FIG.

  Since there is a limit to the amount of pixel data 24 that can be stored in the pixel cache 11, pixel data that is no longer needed in the processing of the graphics engine 10 is transferred from the pixel cache 11 to the frame buffer 14 and newly required pixel data. Is transferred from the frame buffer 14 to the pixel cache 11. At this time, pixel data is input and output in units of tile areas.

Here, the size of the tile area of the frame buffer 14 can be changed, and the number of pixel data input / output between the pixel cache 11 and the frame buffer 14 can be reduced by changing the size.
FIG. 4 is a diagram illustrating an example of division of the tile area of the frame buffer 14. In the case where the frame buffer 14 is divided into a plurality of tile areas 41 as shown in FIG. 6A, in order to write a triangle as shown in FIG. A total of six write accesses from 11 to the frame buffer 14 are required. This is because when the graphics engine 10 outputs triangular pixel data to the pixel cache 11, the pixel cache 11 inputs and outputs pixel data to and from the frame buffer 14 in units of tile areas. This is because data input / output occurs between the pixel cache 11 and the frame buffer 14 by the number.
On the other hand, when the frame buffer 14 is divided into a plurality of tile areas 42 as shown in FIG. 5B, the number of write accesses from the pixel cache 11 to the frame buffer 14 required to write the same triangle is three. Good. Note that the number of pixels in one tile area is the same for both a and b. When the figure to be drawn is a rectangular fill, conversely, the number of accesses may be reduced by dividing as shown in FIG.
As described above, if the size of the tile area of the frame buffer 14 is changed depending on the figure to be drawn, the number of times of data input / output between the pixel cache 11 and the frame buffer 14 can be reduced, so that the drawing speed can be increased.

Here, a method for changing the size of the tile area will be described. The following three examples can be given as examples of the tile area size changing method.
Dimension changing method 1: The graphics engine 10 designates a tile size.
Dimension changing method 2: A program for controlling the graphics hardware 100 designates a tile dimension.
Size changing method 3: The pixel cache 11 determines the tile size.

In the dimension changing method 1, tile dimensions are determined in advance for each graphics engine 10, and the tile dimensions are determined based on the type of the graphics engine 10 that has been accessed.
In the dimension changing method 2, tile dimensions are designated on the drawing program side that controls the graphics engine 10. Since the drawing program grasps the figure to be drawn, the tile size of the pixel cache 11 is changed to a tile size suitable for the figure.
In the dimension changing method 3, the pixel cache 11 determines a tile dimension based on the pixels accessed by the graphics engine 10.

Hereinafter, a method (size changing method 3) by which the pixel cache 11 determines the tile size will be described. As described above, the pixel cache 11 has the control flag 21 and includes a dirty flag indicating that the pixel data has been changed. The pixel cache 11 can know which pixel in the tile area has been accessed based on the dirty flag. At the same time, an unused area that has not been accessed can be detected, and the unused area can be used to determine the size of the tile.
The pixel cache 11 determines the tile size based on the dirty flag of the entry accessed most recently in the entry of the pixel cache 11. Specifically, the dimension of the tile area that can be changed is determined in advance, and the dimension that minimizes the unused portion is selected from among the dimensions. For example, when the pixel data 24 of the most recently accessed pixel cache 11 corresponds to the tile area 50 of 8 × 8 pixels shown in FIG. 5, the upper left corner of the tile area is fixed and the tile area size is set. The tile area size is determined so that the unused portion becomes the smallest when changed. Although the tile area 51 in FIG. 5 includes an unused part, the tile area 52 has no unused part at all, so the tile area size is changed to the size of the tile area 52. In this example, the upper left corner of the tile area is fixed, but one pixel such as the lower right corner and the center may be fixed. The pixels to be fixed may be selected so that the unused portion is minimized.
Alternatively, the size of the tile area and the change history of the unused part may be stored, and the combination with the least unused part may be selected after the tile area is changed.

  Further, when an unused portion is detected and the size of the tile area is changed, it is possible to prefetch (prefetch) adjacent tile areas. For example, as shown in FIG. 6, when the lower half of the tile area 600 is unused, the top, right, and left tile areas 602, 603, and 604 are likely to be accessed next. Prefetching the tile area to be accessed into the pixel cache 11 is effective in improving the drawing performance.

FIG. 7 is a flowchart of the operation of the pixel cache 11 according to the first embodiment.
First, in step ST61, an address representing a screen position of a pixel accessed from the graphics engine 10 is acquired.
In step ST <b> 62, it is determined whether the pixel corresponding to the acquired address is stored in the tile area stored in the pixel cache 11.
If it is determined that it is stored, the process proceeds to step ST63, and it is determined whether the access from the graphics engine 10 is a read request or a write request. In the case of a read request, the process proceeds to step ST64, and the corresponding pixel data in the pixel cache 11 is transferred to the graphics engine 10. In the case of a write request, the process proceeds to step ST65, and the pixel data 24 in the pixel cache 11 is updated with the data transferred from the graphics engine 10. At this time, if there is a write access to a pixel in a portion where a plurality of tile areas overlap, all entries corresponding to the tile area including the pixel are updated. For example, when there is a write access to the overlapping area of the tile area 33 and the tile area 34 shown in FIG. 3, the pixel data 24 of both entry 3 and entry X is updated.

If it is determined in step ST62 that the pixel accessed by the graphics engine 10 is not in the tile area stored in the pixel cache 11, the process proceeds to step ST66.
In step ST66, the tile area dimensions are determined by the above-described dimension changing method. Next, in step ST67, an entry of the pixel cache 11 to be saved in the frame buffer 14 is determined. That is, in order to read out pixel data of the tile area that is newly required from the frame buffer 14 and store it in the pixel cache 11, it is necessary to save data for one entry from the pixel cache 11 to the frame buffer 14. Therefore, the entry to be saved is determined. As a method for determining the entry to be saved, an entry having the longest elapsed time after being accessed may be saved using a general LRU (least recently used) method. The entry corresponding to the tile area farthest from the pixel may be selected as the entry to be saved. Since the pixels accessed by the graphics engine 10 have spatial locality, the probability of accessing a distant tile area again is low. Therefore, it is considered that the entry corresponding to the farthest tile area may be saved in the frame buffer 14.
Next, in step ST68, the newly determined tile area is read from the frame buffer 14. Here, the process of saving the entry determined in step ST67 to the frame buffer 14 (step ST69) is suspended, and the pixel data of the new tile area to be replaced is read first. This is because the access from the graphics engine 10 to the pixel cache 11 is in a waiting state until step ST68 is completed. Therefore, step ST68 is delayed and step ST68 is performed first so that this waiting time is reduced. . After step ST68 is completed, the process proceeds to step ST63, and at the same time as responding to the access of the graphics engine 10, step ST69 is executed, and the entry to be saved is written back to the frame buffer 14. If the above-described prefetching (prefetch) is performed, the process proceeds to step ST67.

Next, an address conversion method of the memory control device 12 will be described. In the following description, an SDRAM that is a typical memory capable of burst transfer is used.
FIG. 8 shows the structure of the SDRAM. In the SDRAM, an address is specified by a row address and a column address. Memory areas with the same row address are called pages. If consecutive accesses are made to the same page, Read / Write can be executed at high speed while specifying a column address using the high-speed page mode. If the pages are different, there will be a delay between accesses.

  FIG. 9 is a diagram showing an example in which SDRAM pages are associated with the frame buffer 14. As shown in the figure, pages (page tile areas) are allocated in a tile shape from the upper left of the screen. Each tile area is included in this page tile area. Here, even if the size of the tile area corresponding to the entry in the pixel cache 11 is changed, the memory control device 12 converts the physical address of the pixel data on the frame buffer 14 so that the pixel data is not out of the page tile area. Do not. For this purpose, the common multiple of the dimensions that can be taken by the tile area corresponding to the entry in the pixel cache 11 may be set as the dimension of the page tile area. For example, as shown in FIG. 10, when the vertical dimension of the tile area corresponding to the entry of the pixel cache 11 can be changed to any one of 1, 4, 8, and 16, the vertical dimension of the page tile area is set to a multiple of 16. If it is set, the tile area is less likely to cross the page tile area. As a result, even if the size of the tile area changes, it can be stored in the same page, and can be accessed in the high-speed page mode.

The SDRAM is composed of a plurality of banks, and each bank can be controlled independently. This is called multi-bank operation. A method for realizing address translation that speeds up access between the pixel cache 11 and the frame buffer 14 by using this will be described.
FIG. 11 shows one of the page tile areas shown in FIG. As shown in the figure, the page tile area is further divided into tiles, and the area is called a block. Each block is made to correspond to the bank of the SDRAM so as to alternate. In the figure, blocks A, B, C, and D correspond to SDRAM banks A, B, C, and D shown in FIG.
The block size is determined based on the maximum number of pixels that can be accessed in X burst transfers. When Y is the number of pixels input / output in one burst transfer, the number of pixels in the block is (X * Y). The block size is arbitrarily determined from the number of pixels that can be included in the block. The numbers in the block shown in FIG. 11 are values obtained by dividing the column address by (burst length * X).
As shown in the figure, the tile area corresponding to the entry in the pixel cache 11 may be composed of a plurality of blocks or only one block. Therefore, the tile area is a multiple of the block size. For example, a tile area 120 shown in FIG. 12 may be configured with two horizontal blocks and four vertical blocks, or a tile area 121 may be configured with four horizontal blocks and four vertical blocks. When the tile area is composed of Z blocks, pixel data can be transferred by Z burst transfer.
In multi-bank operation, commands can be issued independently to different banks. For example, when Read is performed on the bank A, another command can be issued to the bank B before the Read data output is completed. Therefore, by mapping the blocks to the banks alternately, it is possible to increase the opportunities for using multi-bank operations.

As described above, according to the first embodiment, even if the size of the tile area of the frame buffer 14 is changed by the pixel cache 11, the address conversion function of the memory control device 12 allows the area within the same page area of the memory 13. Since the pixel data of one tile area is stored in the storage area, a delay in access to the frame buffer 14 can be avoided, and the drawing processing of the graphics hardware 100 can be speeded up.
In addition, the pixel cache 11 determines the tile area where the unused portion is the smallest depending on the figure to be drawn, and performs data input / output with the frame buffer 14 in units of the tile area. The graphics hardware 100 capable of operating at high speed can be realized.
In addition, since the memory control device 12 converts the address output from the pixel cache 11 so that each tile area is composed of a plurality of bank areas of the memory 13, an opportunity to use a multi-bank operation. And the access to the frame buffer 14 can be speeded up.

Embodiment 2. FIG.
In the second embodiment, access from the graphics engine 10 to the pixel cache 11 is made efficient.
When the graphics engine 10 acquires pixel data, it is more efficient to continuously access one tile area. Here, the tile area is either a tile area corresponding to an entry in the pixel cache 11 or a page tile area corresponding to a page in the memory 13. When an area crossing the tile area is accessed, the pixel data 24 in the entry may be rewritten in the pixel cache 11. When rewriting occurs, access to the frame buffer 14 occurs, and the wait time of the graphics engine 10 occurs. In particular, when the page tile area corresponding to the page of the memory 13 is straddled, the waiting time becomes long.
Therefore, the graphics engine 10 is optimized so that pixels are output in order for each tile area. For example, as shown in FIG. 13, when drawing a triangle, pixel data is generated in order for each tile region.
As a result, access across the tile area from the graphics engine 10 is reduced, and the processing speed can be increased.

Embodiment 3 FIG.
FIG. 14 is a block diagram showing a configuration of graphics hardware 200 according to the third embodiment. As shown in the figure, the graphics hardware 200 includes a buffer memory 17 that can temporarily hold pixel data between the graphics engine 10 and the pixel cache 11.
In the third embodiment, the pixel data output from the graphics engine 10 is rearranged in the order according to the tile area in the buffer memory 17 and then output to the pixel cache 11.
For example, as shown in FIG. 15, when drawing a triangle, even if the graphics engine 10 outputs pixel data in the horizontal order, the data is rearranged in the order of each tile area via the buffer memory 17. It has been.
As described above, according to the third embodiment, by rearranging the order of the pixel data in the buffer memory 17, the access across the tile area is reduced, and the processing speed can be increased.

It is a block diagram which shows the structure of the graphics hardware by Embodiment 1 of this invention. It is the figure which showed the structure of the pixel cache by Embodiment 1 of this invention. It is a figure which shows the response | compatibility of the pixel data of a pixel cache, and a frame buffer by Embodiment 1 of this invention. It is a figure which shows the example of a division | segmentation of the tile area | region of a frame buffer. It is a figure explaining the dimension change method of the tile area | region by Embodiment 1 of this invention. It is a figure explaining the prefetch of the tile area | region by Embodiment 1 of this invention. It is a flowchart of operation | movement of a pixel cache by Embodiment 1 of this invention. It is a figure which shows the structure of SDRAM. It is a figure which shows the example which made the page of SDRAM correspond to the frame buffer by Embodiment 1 of this invention. It is a figure explaining the allocation method of a page tile area | region by Embodiment 1 of this invention. It is a figure showing the structure of one page tile area | region by Embodiment 1 of this invention. It is a figure which shows the structural example of the page tile area | region by Embodiment 1 of this invention. It is a figure explaining optimization of the access method to the tile area | region of a pixel cache by the graphics engine by Embodiment 2 of this invention. It is a block diagram which shows the structure of the graphics hardware by Embodiment 3 of this invention. It is a figure explaining optimization of the access method to the tile area | region of a pixel cache by the graphics engine by Embodiment 3 of this invention.

Explanation of symbols

10 graphics engine, 11 pixel cache, 12 memory controller, 13 memory (drawing memory), 14 frame buffer (drawing memory), 15 display device, 16 CPU, 17 buffer memory, 21 control flag, 22 tile size, 23 Tag address, 24 pixel data, 100,200 Graphics hardware.

Claims (12)

A graphics engine that performs rendering using pixel data;
A drawing memory for storing pixel data to be supplied to the graphics engine and capable of burst transfer of the pixel data;
Pixel data is input / output to / from the drawing memory in units of tile areas whose dimensions can be changed by dividing the storage area of the drawing memory into tiles, and the acquired pixel data is supplied to the graphics engine. Pixel cache,
A memory control device that converts an address output when the pixel cache accesses the drawing memory into a physical address of the drawing memory and mediates access;
The graphics hardware according to claim 1, wherein the memory control device performs address conversion so that pixel data in the tile area is within a range of the same page area of the drawing memory.   The graphics hardware according to claim 1, wherein the pixel cache stores pixel data of a tile area in a plurality of storage areas on the pixel cache in an overlapping manner.   2. The graphics hardware according to claim 1, wherein the pixel cache determines a dimension of the tile area based on a shape of a graphic to be drawn.   4. The graphics hardware according to claim 3, wherein the pixel cache determines the size of the tile area so that the unused storage area in the tile area is minimized.   2. The graphics hardware according to claim 1, wherein when the pixel cache acquires pixel data of a certain tile area, the pixel cache also acquires pixel data of an adjacent tile area. In the pixel cache, the pixel data to be accessed by the graphics engine is not held in the pixel cache, and when the pixel data is exchanged with the drawing memory,
2. The graphics hardware according to claim 1, wherein after obtaining new pixel data from the drawing memory, the pixel data is saved in the drawing memory.   2. The graphics hardware according to claim 1, wherein the memory control device performs address conversion so that a page of the drawing memory corresponds to a page tile area including a plurality of tile areas.   2. The graphics hardware of claim 1, wherein the pixel cache determines the size of the tile area to be a divisor of the size of the page tile area.   The memory control device performs address conversion so that a block, which is a minimum configuration area of a tile area, is configured from one bank area of a drawing memory, and adjacent blocks are configured from different banks. The graphics hardware according to claim 1.   2. The graphics hardware according to claim 1, wherein the memory control device performs address conversion so that the size of the block which is the minimum configuration area of the tile area is optimized to the burst transfer data amount of the drawing memory. .   The graphics hardware according to claim 1, wherein the graphics engine continuously accesses pixel data in the same tile area. 2. The graphics hardware according to claim 1, wherein a buffer memory is provided between the graphics engine and the pixel cache, and pixel data output from the graphics engine is rearranged in the order of each tile area in the buffer memory. Wear.

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