JP2008269727A5 - - Google Patents

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Publication number
JP2008269727A5
JP2008269727A5 JP2007113820A JP2007113820A JP2008269727A5 JP 2008269727 A5 JP2008269727 A5 JP 2008269727A5 JP 2007113820 A JP2007113820 A JP 2007113820A JP 2007113820 A JP2007113820 A JP 2007113820A JP 2008269727 A5 JP2008269727 A5 JP 2008269727A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007113820A
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JP2008269727A (ja
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Application filed filed Critical
Priority to JP2007113820A priority Critical patent/JP2008269727A/ja
Priority claimed from JP2007113820A external-priority patent/JP2008269727A/ja
Priority to US12/108,948 priority patent/US7706194B2/en
Publication of JP2008269727A publication Critical patent/JP2008269727A/ja
Publication of JP2008269727A5 publication Critical patent/JP2008269727A5/ja
Pending legal-status Critical Current

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JP2007113820A 2007-04-24 2007-04-24 昇圧回路、半導体記憶装置およびその駆動方法 Pending JP2008269727A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007113820A JP2008269727A (ja) 2007-04-24 2007-04-24 昇圧回路、半導体記憶装置およびその駆動方法
US12/108,948 US7706194B2 (en) 2007-04-24 2008-04-24 Charge pump circuit, semiconductor memory device, and method for driving the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007113820A JP2008269727A (ja) 2007-04-24 2007-04-24 昇圧回路、半導体記憶装置およびその駆動方法

Publications (2)

Publication Number Publication Date
JP2008269727A JP2008269727A (ja) 2008-11-06
JP2008269727A5 true JP2008269727A5 (ja) 2010-01-28

Family

ID=39886792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007113820A Pending JP2008269727A (ja) 2007-04-24 2007-04-24 昇圧回路、半導体記憶装置およびその駆動方法

Country Status (2)

Country Link
US (1) US7706194B2 (ja)
JP (1) JP2008269727A (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010182845A (ja) * 2009-02-05 2010-08-19 Seiko Epson Corp 不揮発性メモリー装置
WO2011111144A1 (ja) * 2010-03-10 2011-09-15 パナソニック株式会社 メモリセルのドレイン電圧用及びゲート電圧用のレギュレータを共有したフラッシュメモリ
JP2011216136A (ja) 2010-03-31 2011-10-27 Fujitsu Semiconductor Ltd 半導体集積回路装置
US8619489B2 (en) 2010-04-30 2013-12-31 Stmicroelectronics S.R.L. Driving circuit for memory device
KR101682189B1 (ko) * 2011-01-04 2016-12-05 삼성전자주식회사 플래시 메모리 장치 및 그것의 워드라인 전압 발생 방법
US8559229B2 (en) * 2010-09-30 2013-10-15 Samsung Electronics Co., Ltd. Flash memory device and wordline voltage generating method thereof
JP5890207B2 (ja) * 2012-03-13 2016-03-22 ルネサスエレクトロニクス株式会社 半導体装置
US9025391B2 (en) * 2012-11-27 2015-05-05 Infineon Technologies Ag Circuit arrangement and method for operating a circuit arrangement
KR102053944B1 (ko) * 2013-02-21 2019-12-11 삼성전자주식회사 불 휘발성 메모리 장치 및 그것을 포함하는 메모리 시스템
JP2014211941A (ja) * 2014-07-03 2014-11-13 スパンションエルエルシー 半導体集積回路装置
US9779819B1 (en) 2016-06-24 2017-10-03 Micron Technology, Inc. Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells
CN116207979A (zh) * 2023-01-17 2023-06-02 中国科学院微电子研究所 一种输出电压可控的电荷泵及其控制方法、电子设备

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375083A (en) * 1993-02-04 1994-12-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit including a substrate having a memory cell array surrounded by a well structure
JP3162564B2 (ja) * 1993-08-17 2001-05-08 株式会社東芝 昇圧回路及び昇圧回路を備えた不揮発性半導体記憶装置
US6222779B1 (en) * 1998-04-24 2001-04-24 Kabushiki Kaisha Toshiba Semiconductor storage device with automatic write/erase function
DE69816032D1 (de) * 1998-04-30 2003-08-07 St Microelectronics Srl Verfahren zur Sicherung von Daten im Falle unerwünschter Unterbrechnungen während ein Programmzyklus eines nichtflüchtigen Speichers, und ein nichtflüchtiger Speicher
JP2000149582A (ja) * 1998-09-08 2000-05-30 Toshiba Corp 昇圧回路，電圧発生回路及び半導体メモリ
JP4149637B2 (ja) 2000-05-25 2008-09-10 株式会社東芝 半導体装置
US7177197B2 (en) * 2001-09-17 2007-02-13 Sandisk Corporation Latched programming of memory and method
JP3836787B2 (ja) * 2001-12-27 2006-10-25 株式会社東芝 半導体装置
US6842383B2 (en) 2003-01-30 2005-01-11 Saifun Semiconductors Ltd. Method and circuit for operating a memory cell using a single charge pump
JP2004348806A (ja) * 2003-03-26 2004-12-09 Sharp Corp 半導体記憶装置およびそれを備えた携帯電子機器
KR100572323B1 (ko) * 2003-12-11 2006-04-19 삼성전자주식회사 멀티레벨 고전압 발생장치
JP2005267734A (ja) 2004-03-18 2005-09-29 Renesas Technology Corp 昇圧回路及びそれを用いた不揮発性メモリ
KR100724333B1 (ko) * 2005-10-05 2007-06-04 삼성전자주식회사 리던던시 플래그 신호의 응답마진이 향상되는 반도체메모리 장치 및 이를 이용한 리던던시 구동 방법
ITVA20060011A1 (it) * 2006-02-22 2007-08-23 St Microelectronics Srl Dispositivo di memoria e relativo metodo di controllo

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