JP2009004480A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2009004480A
JP2009004480A JP2007162424A JP2007162424A JP2009004480A JP 2009004480 A JP2009004480 A JP 2009004480A JP 2007162424 A JP2007162424 A JP 2007162424A JP 2007162424 A JP2007162424 A JP 2007162424A JP 2009004480 A JP2009004480 A JP 2009004480A
Authority
JP
Japan
Prior art keywords
film
groove
mask
region
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007162424A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009004480A5 (2
Inventor
Shingo Ujihara
慎吾 氏原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2007162424A priority Critical patent/JP2009004480A/ja
Priority to US12/142,320 priority patent/US20080318383A1/en
Publication of JP2009004480A publication Critical patent/JP2009004480A/ja
Publication of JP2009004480A5 publication Critical patent/JP2009004480A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Landscapes

  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
JP2007162424A 2007-06-20 2007-06-20 半導体装置の製造方法 Pending JP2009004480A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007162424A JP2009004480A (ja) 2007-06-20 2007-06-20 半導体装置の製造方法
US12/142,320 US20080318383A1 (en) 2007-06-20 2008-06-19 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007162424A JP2009004480A (ja) 2007-06-20 2007-06-20 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2009004480A true JP2009004480A (ja) 2009-01-08
JP2009004480A5 JP2009004480A5 (2) 2010-07-08

Family

ID=40136921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007162424A Pending JP2009004480A (ja) 2007-06-20 2007-06-20 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US20080318383A1 (2)
JP (1) JP2009004480A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101802371B1 (ko) * 2011-05-12 2017-11-29 에스케이하이닉스 주식회사 반도체 셀 및 그 형성 방법

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113054014A (zh) * 2019-12-26 2021-06-29 株洲中车时代半导体有限公司 SiC沟槽氧化层和SiC MOSFET沟槽栅的制备方法及SiC MOSFET器件
CN114038792B (zh) * 2021-10-26 2025-09-02 上海华力集成电路制造有限公司 一种消除栅氧化层下埋工艺中硅残留的方法
CN120187084B (zh) * 2025-05-19 2025-08-19 晶芯成(北京)科技有限公司 半导体结构及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243954A (ja) * 1999-02-22 2000-09-08 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2005183976A (ja) * 2003-12-19 2005-07-07 Samsung Electronics Co Ltd シリコン基板とのエッチング選択比が大きいマスク層を用いたリセスチャンネルアレイトランジスタの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468771B1 (ko) * 2002-10-10 2005-01-29 삼성전자주식회사 모스 트랜지스터의 제조방법
KR100604816B1 (ko) * 2003-05-19 2006-07-28 삼성전자주식회사 집적 회로 소자 리세스 트랜지스터의 제조 방법 및 이에의해 제조된 집적회로 소자 리세스 트랜지스터

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243954A (ja) * 1999-02-22 2000-09-08 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2005183976A (ja) * 2003-12-19 2005-07-07 Samsung Electronics Co Ltd シリコン基板とのエッチング選択比が大きいマスク層を用いたリセスチャンネルアレイトランジスタの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101802371B1 (ko) * 2011-05-12 2017-11-29 에스케이하이닉스 주식회사 반도체 셀 및 그 형성 방법

Also Published As

Publication number Publication date
US20080318383A1 (en) 2008-12-25

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