JP2009272016A - Flash memory system - Google Patents

Abstract

An object of the present invention is to provide a high-capacity and high-reliability flash memory system by reducing the proximity effect due to interference between adjacent memory cells that becomes apparent as the flash memory is highly integrated and miniaturized.
In a NAND flash memory system having a NAND flash memory chip 1 and a memory controller 2 for controlling writing to each memory cell of the NAND flash memory chip 1, data patterns of surrounding adjacent memory cells and By predicting the amount of interference in advance from the degree of parasitic capacitance coupling between adjacent memory cells, converting the data pattern so that it becomes the original characteristics after being damaged, and adjusting the write amount for each memory cell , Reduce the proximity effect between adjacent memory cells.
[Selection] Figure 7

Description

  The present invention relates to a technology of a flash memory system, and more particularly to a technology effective when applied to a multi-level flash memory that stores information of 2 bits or more in one memory cell.

  According to a study by the present inventor, techniques relating to the multi-level flash memory include, for example, techniques described in Patent Document 1 and Patent Document 2.

  In the technique of Patent Document 1, when both adjacent memory cells are written based on data of two pages serving as adjacent bit lines (BL), the threshold voltage (Vth) of the memory cell written first is set. Write low. As a result, when the memory cell to be written later increases the Vth of the memory cell written earlier by the proximity effect, the memory cell Vth written earlier becomes the intended Vth. Can be reduced. This Patent Document 1 is a technique related to a so-called proximity effect reduction method between adjacent BLs.

The technique of Patent Document 2 writes data for the entire erase block. Thereafter, the Vth increase due to the proximity effect is calculated from the data pattern, and the Vth distribution is narrowed by performing additional writing on the memory cell having a small Vth increase in accordance with the memory cell having a large Vth increase. This Patent Document 2 is a technique related to a so-called block additional writing method.
Japanese Patent Laying-Open No. 2005-25898 JP 2007-207333 A

  By the way, as a result of examination by the present inventor regarding the technology of the multi-value flash memory as described above, the following has been clarified.

  For example, the technique of Patent Document 1 can obtain the effect of reducing the proximity effect only between adjacent BLs. That is, the proximity effect between adjacent word lines (WL) and oblique adjacent memory cells is not considered. In addition, it is a control of selecting whether to receive the proximity effect from the data pattern and writing at a low level or normal writing, and one bit of 0 or 1 in one memory cell instead of multi-level flash memory It is assumed that binary storage is performed. Therefore, it is considered that application to multi-level storage is not possible.

  In the technique of Patent Document 2, since normal writing is performed and additional writing is performed again, it takes a long time to write, and writing is considered to be considerably slow. In addition, at the time of starting additional writing, it is difficult to set the initial WL voltage because writing is not performed from a state in which all memory cells are in the erase distribution. Furthermore, an algorithm for calculating the additional write correction amount is not shown, and it is considered that the implementation is difficult.

  In the multi-level flash memory as described above, for example, in the NAND flash memory, if the adjacent memory cell of the target memory cell is written due to the coupling due to the parasitic capacitance between the floating gates (FG) of the adjacent memory cell, the target memory cell In recent years, the proximity effect of increasing the Vth of the metal has become a problem. As device miniaturization proceeds in the future, the parasitic capacitance between adjacent FGs will increase, and the amount of fluctuation of the memory cell Vth due to the proximity effect will increase.

  For this reason, it becomes difficult to narrow the Vth distribution in multi-value storage in which information of 2 bits or more is stored in one memory cell by forming four or more Vth distributions, and the limit of multi-value storage is called out. It's getting on. Such coupling between adjacent memory cells is not only a NAND flash memory, but is a problem that manifests itself in any memory if a large capacity is desired, and a new memory operation method that reduces the proximity effect is required. ing.

  Therefore, a typical object of the present invention is to provide a flash memory system having a large capacity and high reliability by reducing the proximity effect due to interference between adjacent memory cells which becomes apparent as the flash memory is highly integrated and miniaturized. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a typical outline is applied to a flash memory in which when a memory cell adjacent to the target memory cell is written, the characteristics of the target memory cell change due to interference. In a flash memory system having a memory controller that controls writing to each memory cell in the flash memory, the amount of interference is predicted in advance from the data pattern of neighboring memory cells and the degree of parasitic capacitance coupling between adjacent memory cells. By changing the data pattern so as to have the original characteristics after being damaged and adjusting the write amount for each memory cell, the proximity effect between adjacent memory cells is reduced.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In other words, the effect obtained by the typical one is that the proximity effect due to the interference between adjacent memory cells, which becomes apparent as the flash memory is highly integrated and miniaturized, is reduced, and a large-capacity and highly reliable flash memory system is achieved. Can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  Further, in the following, in order to make the characteristics of the present invention and each embodiment of the present invention easier to understand, it will be described in comparison with the prerequisite technology for the present invention. Furthermore, although a NAND flash memory will be described as an example, it goes without saying that the present invention can also be applied to a NOR flash memory, a phase change memory, and the like.

<Prerequisite technology for the present invention>
The prerequisite technology for the present invention will be described with reference to FIGS.

  FIG. 1 is a diagram for explaining a general memory array configuration of a NAND flash memory.

General memory array of the NAND flash memory includes a plurality of word lines _{WL (WL <0> ~WL <} 15>), a plurality of bit lines _{BL (BL E <0>,} BL O <1>, BL E _<2> , BLO _<3> ,...) And a plurality of memory cells MC arranged at the intersections of the word lines WL and the bit lines BL. Bit line BL, and the even-numbered even-numbered bit lines BL _E, consists odd odd bit lines BL _O, respectively, one of which is connected to the drain side select transistor having a gate controlled by a control signal STD, the other control signals It is connected to a source side select transistor that is gate-controlled by STS, and this source side select transistor is connected to a common source line CS.

  In this example, a configuration of 16 memory cells in series is shown as an example. The unit shown in FIG. 1 is an erase unit called one block common to the P wells.

In flash memory, the unit of writing is called a page. In this example, an example of a page configuration of a 2-bit / memory cell multi-level NAND flash memory is shown. The even-numbered bit lines BL E _/ odd-numbered bit lines BL _O of the memory cells MC connected to the same word line WL is set to a different page, further the upper and lower bits of the multi-level to another page in the same memory cell MC. Therefore, the configuration is 4 pages per word line (pages 0 to 3, pages 4 to 7,..., Pages 56 to 59, pages 60 to 63), and 64 pages per erase block (pages 0 to 63).

Writing is performed in page units. A high voltage is applied to the selected word line, and electrons are injected into the FG (floating gate) of the selected memory cell from the channel to which 0 V is applied between the source and drain of the memory cell by FN tunneling. Electron injection lowers the potential of the selection FG and increases the Vth (threshold voltage) of the memory cell as viewed from the word line. The sense amplifier is used to read, one sense amplifier in the even bit lines BL _E and odd bit lines BL _O is shared.

  Erasing is performed in units of blocks. A high voltage is applied to the P well of the substrate and the source and drain of the memory cell, and FG electrons are extracted to the substrate by FN tunneling to lower the Vth of the memory cell.

  FIG. 2 is a diagram for explaining memory cell threshold voltage distribution and data logic assignment of a multi-value (2 bits / memory cell) NAND flash memory.

  This is a distribution after erasure in which data ‘11’ is in an initial state. In order to write as a multi-value, it is necessary to write the lower bit page first, and then write the upper bit page. When writing a page of lower bits, the Vth of the write selection cell in the target page is increased from “11” to “10”. For a memory cell in which writing is not performed within the target page, that is, the lower bit is left as data '11', a voltage difference between WL and the channel of the memory cell is given by applying a slightly higher voltage to the channel as a write blocking voltage. To prevent writing. Next, the upper bit page is similarly written. When the data of the memory cell after writing the lower bit is ‘11’, the writing of the upper bit is a transition from data ‘11’ to ‘01’, and a transition from the erase distribution to the highest Vth distribution. When the data of the memory cell after writing the lower bit is “10”, the upper bit write is a transition from the third Vth distribution to the second Vth distribution from the higher side (from “10” to “00”). Become.

  FIG. 3 is a diagram for explaining parasitic capacitance coupling between adjacent floating gates in the memory array plane of the NAND flash memory.

  In the memory array of the NAND flash memory, the word line WL of polycrystalline silicon runs in the X direction, and the bit line BL which is the diffusion layer source, drain and channel of the memory cell runs in the Y direction. A polycrystalline silicon floating gate FG of each memory cell is formed under WL at the intersection of WL and BL.

When attention is paid to the FG of a certain memory cell, there are FGs of memory cells adjacent to each other in the WL direction, adjacent to the BL direction, and obliquely. As shown in FIG. 3, when attention is paid to the memory cell at the intersection of _{WL <n>} and _{BL O <n>,} and FG of interest memory cell, between the FG of adjacent memory cells, the WL direction _{C X} , the BL direction _{C Y,} parasitic capacitance of _{C XY} is present in an oblique direction.

Since FG is a floating high impedance node, when any of the memory cells adjacent to the memory cell of interest is written and the FG potential of the adjacent memory cell decreases, parasitic capacitance C _X between adjacent FGs in the WL direction, BL direction The FG potential of the memory cell of interest also decreases via the adjacent FG parasitic capacitance C _Y and the diagonally adjacent FG parasitic capacitance C _XY . That is, when adjacent memory cells are written and Vth rises, Vth of the memory cell of interest also rises. This is called a proximity effect.

  FIG. 4 is a diagram for explaining the parasitic capacitance coupling between adjacent floating gates in the memory array cross section in the word line direction of the NAND flash memory.

In the memory array of the NAND flash memory, a polycrystalline silicon FG is formed under a polycrystalline silicon word line WL as shown in FIG. The voltage ratio of the FG potential rise / WL potential rise when the WL potential is raised is determined by the capacitance coupling ratio of C _ONO / (C _OX + C _ONO ) if C _X which is a parasitic capacitance is ignored in FIG. . C _ONO represents a WL-FG coupling capacitance, and C _OX represents an oxide film capacitance. FN tunneling writing is performed by applying a high voltage to WL at the time of writing, but since the probability of FN tunneling is determined by the electric field between FG and the channel, in order to obtain a high FG potential at a constant WL potential, a capacitance cup It is necessary to increase the ring ratio C _ONO / (C _OX + C _ONO ).

When writing is performed in the order of page 0, page 1,..., Page 63 in accordance with the page allocation of FIG. 1, page 1 is written after page 0 is written. Here, when considering the parasitic capacitance C _X between adjacent FG, when Vth of the memory cell belonging to the page 1 by the writing of the page 1 is assumed to increase by [Delta] Vth _a uniformly, the Vth of interest memory cells belonging to page 0 Under the influence of the proximity effect of the adjacent memory cells on both sides, it varies by ΔVth _a × 2C _X / C _total . C _total is all capacitances attached to the target memory cell FG including C _OX and C _ONO .

As described above, the degree of the proximity effect is determined by the magnitude of the parasitic capacitance coupling coefficient C _X / C _total . As the process becomes finer, the distance between adjacent memory cells becomes closer, so the degree of proximity effect increases as the capacity increases.

  FIG. 5 is a diagram for explaining the parasitic capacitance coupling between adjacent floating gates in the memory array cross section in the bit line direction of the NAND flash memory.

As with _{C X} in FIG. 4, there is a parasitic capacitance _{C Y} between adjacent FG for BL direction.

When writing is performed in the order of page 0, page 1,..., Page 63 in accordance with the page assignment in FIG. 1, page 4 and page 6 are written after page 0 and page 2 are written. Here, when considering the parasitic capacitance C _Y between adjacent FG, when Vth of the memory cells belonging to the page 6 by the writing of the page 6 is assumed to rise by [Delta] Vth _a uniformly, page 0, attention memory cells belonging to page 2 Vth varies by ΔVth _a × C _Y / C _total under the influence of the proximity effect of one side adjacent memory cell. C _total is all capacitances attached to the target memory cell FG including C _OX and C _ONO .

As in FIG. 4, the degree of such proximity effect is determined by the magnitude of the parasitic capacitance coupling coefficient C _Y / C _total . As the process becomes finer, the distance between adjacent memory cells becomes closer, so the degree of proximity effect increases as the capacity increases.

Incidentally, FIG. 4, FIG. 5, WL directions has been described proximity effect due BL direction of adjacent FG parasitic capacitance, the parasitic capacitance of C _XY stick in a diagonal direction as shown in FIG. As the process generation progresses, all of C _X , C _Y , and C _XY increase.

  FIG. 6 is a diagram for explaining threshold voltage fluctuations due to the proximity effect in the NAND flash memory.

  When attention is paid to the memory cell included in a certain page due to the parasitic capacitance between adjacent FGs as shown in FIGS. 3, 4 and 5, the page including the adjacent memory cell is written after the target page is written. As a result, the Vth of the memory cell belonging to the page of interest rises due to the proximity effect.

  When this is regarded as a Vth distribution, it is as shown in FIG. When writing to a certain write verify level, the write is repeated until Vth of all memory cells in the target write target page becomes equal to or higher than the write verify level, and writing is performed when all the memory cells reach the write verify level. End. At this time, it is assumed that the Vth distribution of the memory cell of the page of interest immediately after writing is the distribution of the dotted line in FIG.

  Next, when a page including a memory cell adjacent to the memory cell in the page of interest is written, the memory cell in the page of interest is affected by the proximity effect and Vth rises. Since the Vth shift amount due to the proximity effect is determined by the Vth shift amount of the adjacent memory cell × parasitic capacitance coupling coefficient, it depends on the data of the adjacent memory cell. For this reason, the memory cells in the page of interest include memory cells that are greatly affected by the proximity effect and memory cells that are hardly affected by the data pattern of the adjacent memory cell.

  Therefore, as shown in FIG. 6, the Vth distribution of the memory cell of the page of interest spreads to the higher Vth side when affected by the proximity effect.

  In the multi-level NAND flash memory, since the Vth distribution is written into four values as shown in FIG. 2, the range in which each Vth distribution can be taken becomes narrower than the binary NAND flash memory. Further, since electrons injected into the FG gradually escape through the oxide film, the Vth distribution varies with time. For this reason, in the multi-level NAND flash memory, the reliability such as the data retention time is inferior to the binary NAND flash memory.

  Since the Vth distribution spreads due to the proximity effect, the Vth distributions after the four-value writing approach each other. As the proximity effect becomes more prominent in the process miniaturization in the future, the reliability cannot be secured. As the number of rewrites increases, the oxide film deteriorates, so that the outflow of electrons from the FG through the oxide film after writing becomes significant, and it becomes increasingly difficult to secure the number of rewrites and the data retention time in the future.

  Therefore, in each embodiment of the present invention, these problems are solved by the configuration and control method described below.

<Embodiment 1 of the present invention>
A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 7 is a diagram for explaining the configuration of the NAND flash memory system according to the first embodiment.

  The NAND flash memory system includes a NAND flash memory chip 1 having a plurality of memory cells and a memory controller 2 that controls writing to each memory cell of the NAND flash memory chip 1. The NAND flash memory chip 1 is also simply referred to as the flash memory chip 1.

  The NAND flash memory chip 1 drives a memory array 11 (detailed in FIG. 9) including a plurality of memory cells MC disposed at intersections of each word line WL and each bit line BL, and each word line WL. From the X decoder 12, the sense circuit / write data buffer 13 for writing and reading data by driving each bit line BL, the management area 14 for writing the measured value of the parasitic capacitance coupling coefficient, etc. Composed.

  The memory controller 2 includes a work RAM 21 that stores addresses, write user data, and the like, a code ROM 22 that stores a data conversion processing program, and a CPU 23 that executes processing based on the data conversion processing program.

  In the NAND flash memory system configured as described above, the user data is received by the memory controller 2 and stored in the work RAM 21. In the conventional NAND flash memory, writing is performed in units of pages (= 1/4 WL). However, in the present invention, since the proximity effect between adjacent WL, adjacent BL, and diagonally adjacent memory cells is reduced, not in units of pages. Writing is performed in units of blocks composed of a plurality of WLs and a plurality of BLs. For this reason, user data is sequentially stored in the work RAM 21, and data conversion for reducing the proximity effect is started when the user data capacity reaches the capacity of one block.

  After the user data for one block is stored in the work RAM 21, the CPU 23 starts data conversion for reducing the proximity effect. Although not particularly limited, the parasitic capacitance coupling coefficient between adjacent FGs is measured when the flash memory chip 1 is tested for each value between adjacent WLs, between adjacent BLs, and between diagonally adjacent memory cells. 1 is read from the flash memory chip 1 when the flash memory system is powered on and written to the work RAM 21 in the memory controller 2 or a register in the CPU 23 so that it can be read at high speed. Keep it.

The CPU 23 performs data conversion based on one block of user data and parasitic capacitance coupling coefficient. When the memory cell that gives the proximity effect is the harming memory cell, and the memory cell that receives the proximity effect is the damaged memory cell, Vth increase due to the proximity effect of the damaged memory cell is
Damaged memory cell ΔVth = parasitic capacitance coupling coefficient × harmful memory cell ΔVth
... Formula (1)
Therefore, ΔVth can be calculated in the order of pages written over the entire block, and each memory cell Vth in a state of receiving the proximity effect after completion of block writing can be predicted.

  Since it is possible to predict Vth after completion of writing in a state where the proximity effect is received, it is possible to calculate Vth that exactly matches the target when the proximity effect is received. That is, it is possible to write to a lower Vth in advance as Vth rises due to the proximity effect.

It is assumed that a certain memory cell is written in Vth of 3.0 V corresponding to data “00” in four values. Actually, if it is written to 2.8V, it can be calculated that it becomes exactly 3.0V after the block writing is completed. The flash memory chip 1 is configured such that when each memory cell stores log ₂ n-bit information, it can be written in m values while reading n values. Here, m> n. As an example, it is assumed that a four-value read of “11”, “10”, “00”, “01” is a 16-value write configuration. The verify level for writing to '0000' is 3.0V, the verify level for writing to '0001' is 2.9V, and the verify level for writing to '0010' is 2.8V , A circuit having a verify level of 2.7 V for writing to “0011” is realized in the NAND flash memory chip 1 in advance. Since we want to read “00” at the time of reading, we want to set Vth after writing to 3.0V. Since it is known from the calculation in the memory controller 2 that if the write is performed at the verify level of 2.8 V, the Vth of 3.0 V will be obtained after the block write is completed. Therefore, the user data “00” received by the memory controller 2 is the memory controller 2. To '0010'.

  This conversion process is performed by the CPU 23 in the memory controller 2. A series of conversion processing programs are stored in the code ROM 22, and the CPU 23 fetches instructions from the code ROM 22, reads and writes the work RAM 21, and performs the conversion processing.

  The memory controller 2 transfers the converted data to the NAND flash memory chip 1, and the flash memory chip 1 repeats normal page unit writing and performs 16-value block writing. The memory cell to be read out as “00” is written as 0010V data to Vth of 2.8V, but after that, the proximity effect is damaged, and Vth of 3.0V is written after the entire block is written. Become.

  Further, since reading is performed as four values by a normal operation at the time of reading, there is no decrease in reading speed. As described above, the proximity effect can be reduced by the ΔVth calculation based on the proximity effect, the verify level calculation for reaching the target Vth at the end of block writing, and the data conversion process.

  FIG. 8 is a diagram for explaining a write operation in the NAND flash memory system according to the first embodiment. (A) shows a normal write operation, and (b) shows a write operation of the present embodiment.

  In the write operation of a normal four-value NAND flash memory chip, as shown in FIG. 8A, writing is performed from the erased state toward the verify levels 1, 2, and 3, and any memory cell is immediately after the verify level. However, as writing proceeds, the distribution spreads to the higher Vth side due to the influence of the proximity effect.

  On the other hand, in the write operation of the first embodiment, as shown in FIG. 8B, the verify level is set to a voltage lower than the Vth level to be finally written as shown in the portion A according to the data pattern. There is a memory cell in which (a three-level example illustrated by a thin dotted line in FIG. 8B) is set. The memory cells existing in the A portion are also affected by the proximity effect, and finally move to a higher Vth side than the A portion, thereby forming a narrow Vth distribution.

  As a result, as shown in FIG. 8, in the write operation of the first embodiment, the Vth window margin between each Vth distribution and each read level can be widened in comparison with the normal write operation. Miniaturization is possible without impairing reliability such as rewrite resistance. Alternatively, it is possible to increase the capacity by multi-values such as 8-values and 16-values greater than 4 values.

  FIG. 9 is a diagram for explaining page allocation in the NAND flash memory system according to the first embodiment.

  In the first embodiment, in order to predict a data pattern-dependent proximity effect, when attention is paid to a certain memory cell, the data of adjacent WL, adjacent BL, and diagonally adjacent memory cells must be known. Therefore, it is necessary to perform writing in units of erase blocks including a plurality of WLs and a plurality of BLs.

  However, in the flash memory chip, even-numbered BL and odd-numbered BL share a sense amplifier necessary for verification, and in the array configuration, some WLs are written and other WLs block writing. Cannot be written at the same time. Therefore, as usual, it is necessary to write all erase blocks by repeating page writing with a page having a size smaller than the block written at a time.

Further, in the first embodiment, as described in the explanation of FIG. 7, it is necessary to convert data from “00” data to “0010” data to increase the Vth resolution at the time of writing rather than reading. It is easier to implement without assigning the upper bit and the lower bit to different pages and assigning them to the same page. Therefore, as shown in FIG. 9, page allocation (pages 0 to 31) in which one page = 1/2 WL and the upper and lower bits are the same page is preferable. That is, the same even-numbered bit lines BL E _/ odd-numbered bit lines BL _O of the memory cells MC connected to the word line WL is a separate page, the same page upper bits and lower bits of the multi-level in the same memory cell MC And

  FIG. 10 is a flowchart for explaining a data conversion processing method in the memory controller in the NAND flash memory system according to the first embodiment.

  When writing from page 0 in FIG. 9 to page 31, which is the last page, in order, memory cells Vth belonging to page <n> may be damaged from page <n + 1>, page <n + 2>, and page <n + 2>. is there. The ΔVth of the memory cell damaged due to the proximity effect can be calculated by the above-described equation (1), and the Vth of all the memory cells after the block write is completed from the first page 0 to the page 31 sequentially according to this equation ( S1).

  As shown in FIG. 9, the page 31 is the page written last, and thus is not damaged by the proximity effect. For this reason, the verify levels of all the memory cells belonging to the page 31 are immediately determined from the data (S2). In this way, the data is converted back to the page to be written last so that the influence of the proximity effect is canceled after the block writing to the younger page in order.

  First, when data conversion of the page 30 is started (S3), the page 30 is a page written before the page 31, and thus is damaged from the page 31. In the above prediction calculation, for example, Vth of the lowest erase level is given as the verify level of the memory cell with the lowest address in the page 30 (S4), and Vth is recalculated after the writing of all the memory cells in the block is completed (S4). S5).

  If the Vth prediction calculation value after block writing of the address youngest memory cell of page 30 does not finally reach the target Vth level (S6-No), the verify level value is incremented by the set width (S7). Then, Vth is predicted and calculated after block writing of all the memory cells in the block. This is repeated until the predicted calculation value exceeds the target value, and when the target value exceeds the target value, that is, when the target memory cell Vth after block writing becomes close to the target value (S6-Yes), iterative calculation is performed for the target memory cell. Exit.

  Thereafter, the data logical value is converted from the verify level of the target memory cell (S8). For example, Vth should be written to 3.0 V in order to finally read data “00”. For this purpose, it is necessary to set Vth to 2.8 V before receiving the proximity effect. In the case of “corresponding to“, ”data to be written to the target memory cell is converted from“ 00 ”to“ 0010 ”.

  Similarly, Vth is to be written to 3.0 V in order to read data “00”, but for this purpose, it is necessary to set it to 2.9 V before receiving the proximity effect, which corresponds to “0001” as write data. In this case, data to be written to the target memory cell is converted from “00” to “0001”. Even when the same data is written in this way, the degree of the proximity effect differs depending on the data pattern of the neighboring memory cells, so that the data after conversion is different.

  Thus, after the data conversion for the target memory cell is performed, the calculation target address is incremented (S10) until the verify value calculation is completed for all the addresses (S10), and all the memory cells in the page 30 are detected. Perform conversion. When the conversion of page 30 is completed, the next page is called page 29. Until the verify value calculation is completed for all pages (S11), the target page is decremented (S12). Data conversion is performed for each memory cell.

  As described above, a general-purpose calculation algorithm can be provided by searching for the verify level optimum value while incrementing the verify level of the memory cell of interest. For example, in FIG. 9, when the page 28 is written, the page 31 receives an oblique proximity effect. When page 29 is written, page 31 is subjected to the proximity effect between adjacent WLs. Even when page 30 is written, page 31 is subjected to the proximity effect between adjacent BLs. Thus, there is a possibility that the page 31 is damaged before the page 30 is damaged by the writing of the page 31, and the memory cell Vth belonging to the page 31 is raised from the erase level.

  For this reason, when page 31 is written and page 30 is damaged, ΔVth (harmfulness) of page 31 does not change from the erase level, but changes from Vth that has already increased due to damage. In consideration of such effects, the method of simply going back from page 31 and converting to page 0 using the inverse function of equation (1) described above has a large error. For this reason, as shown in FIG. 10, a method of updating the verify level of the memory cell of interest, calculating Vth of all the memory cells over the entire block each time, and obtaining the optimum verify level exploratoryly is simple and highly accurate. Further, in the memories other than the flash memory, the proximity effect mechanism can be expressed by an equation, but even when it is difficult to analytically obtain the inverse function, the calculation can be easily performed.

  Data conversion calculation is performed using the work RAM 21, and the result is stored in the work RAM 21. When the data conversion is completed, data is transferred to the flash memory chip 1 in order from page 0, and writing is started. Since data transfer and writing can be performed at the same time, it is not necessary to start writing in the flash memory chip 1 after transferring all the converted data of the block. That is, by transferring the converted data of page 1 simultaneously with the writing of page 0, the capacity of the write data buffer in the flash memory chip 1 can be reduced, and the write time can be shortened.

  FIG. 11 is a flowchart for explaining a method of actually measuring the parasitic capacitance coupling coefficient in the NAND flash memory system according to the first embodiment.

  The parasitic capacitance coupling coefficient used for the data conversion calculation varies depending on the dimensional variation at the time of manufacture. For this reason, in the test process or post-shipment field, measured values are measured for each lot, wafer, chip, bank or block, and calculation is performed using these values. Can be reduced. Measuring the measured value for each block is the most effective because it can reduce the influence of variation between blocks, but there is a trade-off between the cost factor for increasing the management area in which the test time and measured values are written and the granularity of the correction target It becomes the relationship.

  As shown in the flow of FIG. 11, the parasitic capacitance coupling coefficient has a different value between adjacent WLs, between adjacent BLs, and between diagonally adjacent memory cells, and therefore needs to be measured separately for each.

  As a measurement flow, first, the entire block including the memory cell to be measured is erased (Vth distribution narrowing to the erase level) (S21), and the adjacent memory cell (between adjacent WL, adjacent to the measurement target memory cell) Write between BL and diagonally adjacent memory cells toward a predetermined verify level (S22a, S22b, S22c). Thereafter, Vth of the memory cell to be measured is measured (S23a, S23b, S23c). This can be done by incrementing the WL voltage in fine voltage steps and looking for the WL voltage at which the sense amplifier output is inverted. Since the Vth variation amount of the harmful memory cell giving the proximity effect is known from the difference between the verify level and the erase level, the parasitic capacitance coupling coefficient is obtained from the above-described equation (1) (S24a, S24b, S24c). Then, the parasitic capacitance coupling coefficient value is written in the management area 14 (S25).

  As described above, according to the NAND flash memory system of the first embodiment, the NAND flash memory chip 1 and the memory controller 2 that controls writing to each memory cell of the NAND flash memory chip 1 are provided. The following effects can be obtained.

  (1) The amount of increase in Vth due to the proximity effect is calculated for each memory cell before writing to the flash memory chip 1, and after the entire erase block is written under the influence of the proximity effect, each memory cell has the target Vth. Since the verify level that has been corrected in advance for each memory cell so as to settle is written, the influence of the proximity effect due to device miniaturization can be reduced, and a narrowed Vth distribution can be formed. Therefore, even in a multi-level flash memory, a Vth window margin between logic levels, that is, reliability can be secured, and miniaturization can be continued in the future in order to realize a large capacity.

  (2) Since data is written for the entire block composed of a plurality of WLs and a plurality of BLs instead of the conventional page unit, any proximity effect between adjacent WLs, between adjacent BLs, and between diagonally adjacent memory cells can be reduced.

  (3) Since the correction calculation is performed using the actually measured value instead of the predetermined set value as the parasitic capacitance coupling coefficient, it is possible to reduce the proximity effect that is strong against manufacturing variations.

  (4) Since writing is started from the erase level for the block to be written, initial voltage setting is easier compared to the additional writing described in Patent Document 2.

  (5) Since numerical calculation is performed by iterative calculation and the user data pattern is converted into a corrected data pattern in an exploratory manner, it is only necessary to express the mechanism of the proximity effect by a mathematical expression, and an inverse function of the mathematical expression expressing the proximity effect. The procedure of requesting is no longer necessary. For example, it can be easily applied to a case where the proximity effect mechanism is expressed by a complicated mathematical expression in a memory other than a flash memory.

  (6) Since the influence of the proximity effect can be reduced and the Vth distribution can be narrowed, it is possible to increase the memory capacity by promoting multi-values such as 8-value, 16-value, and 32-value / memory cells.

  (7) As the flash memory chip 1, n-value reading and m-value writing (where m> n) can be realized, and the writing need only have a higher resolution than reading, and the correction conversion calculation is performed using a general-purpose microcomputer (CPU 23) + DRAM ( A system configuration is possible in which the data pattern after correction conversion is transferred to the flash memory chip 1 by the memory controller 2 of the work RAM 21). Therefore, a low-cost flash memory system can be realized without using a dedicated controller chip.

<Embodiment 2 of the present invention>
A second embodiment of the present invention will be described with reference to FIG.

  FIG. 12 is a diagram for explaining a reduction in capacity of a write unit by securing a shield area in the NAND flash memory system according to the second embodiment.

  The block of FIG. 9 corresponding to the first embodiment is composed of 32 pages of 16 WL. Actually, the unit of simultaneous writing is 1 page = 1/2 WL every, and the entire block is written by repeating page writing. However, in order to apply correction in consideration of the data of adjacent memory cells, the data of one block Need to be written together. In this case, there is a concern that the size of the writing unit becomes larger than that of a normal flash memory chip, and the usability is deteriorated.

Therefore, in the second embodiment, the block allocation is as shown in FIG. One block is divided into ₇ WL = 14 pages from WL _<0> to WL _<6> and 7WL = 14 pages from WL _{< 9>} to WL _<15> . Since WL _<7> causes proximity effect damage to WL _<6> and WL _<8> suffers proximity effect damage from WL _<9> , these are not used as ordinary memories but as dummy shields WL. By doing so, the unit of writing can be reduced from 1 block = 16 WL = 32 pages to 7WL = 14 pages, and usability is improved.

  However, since it is necessary to use the WL at the write unit boundary as a shield, the shield WL increases as the write unit is reduced, and the memory capacity actually usable by the user decreases.

In FIG. 12, for keeping the size of the write unit constant, but has set 2WL of _{WL <7>} and _{WL <8>} in the shield region, _{WL <7>} only as a shield, _{WL <0>} The write unit may be divided into 7WL = 14 pages from WL _<6> to 8WL = 16 pages from WL _{< 8>} to WL _<15> . Alternatively, if one block is composed of an odd number of WLs instead of an even number, it is possible to divide into two writing units of the same size while using 1WL as a shield. Furthermore, it is not limited to two divisions and may be three or more divisions.

  The second embodiment is the same as the first embodiment except that a divided block obtained by dividing an erase block is used as a write unit. For all memory cells in this divided block, the threshold voltage rises due to the proximity effect. The amount is calculated in advance from the data pattern and the parasitic capacitance coupling coefficient, and is written after the verify level at the time of writing is adjusted in advance for each memory cell so that the target threshold voltage is obtained after the writing of the divided blocks is completed. When generating the converted data pattern in which this proximity effect is corrected, the threshold voltage of each memory cell after writing is predicted from the user data to be written, and the threshold voltage after writing is adjusted while adjusting the verify level during writing. And the iterative calculation is repeated until the difference between the target threshold voltage at the end of writing in the divided block and the predicted threshold voltage after writing is within the allowable range. Further, the parasitic capacitance coupling coefficient can be measured with an actual measurement value for each lot, wafer, chip, bank, or divided block, and calculation using this value can reduce the influence of the proximity effect with high accuracy.

  As described above, according to the NAND flash memory system of the second embodiment, the effects (1) to (7) can be obtained as in the first embodiment, and the erase block is stored in the erase block. Since the writing unit can be reduced by dividing, usability can be improved as compared with the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the NAND flash memory has been described as an example. However, the present invention is not limited to this, and can be applied to a NOR flash memory, a phase change memory, and the like. As for the NOR type flash memory, the proximity effect mechanism is the same as that of the NAND type flash memory, but the capacity has not increased as much as the NAND type, and the distance between adjacent FGs is farther than the NAND type. The problem of proximity effect has not been revealed. The phase change memory has an operating principle in which the crystal state of chalcogenide is controlled by Joule heat and data is rewritten by changing the resistance value of the memory cell resistance element. In the future, when adjacent cells approach each other due to miniaturization, heat is considered to change the resistance value of the adjacent cells during rewriting.

  The flash memory system of the present invention can be applied to a NOR flash memory, a phase change memory, and the like in addition to a NAND flash memory, and further, a flash SSD (Solid State Drive) having an HDD (Hard Disk Drive) interface, It can be widely used for general-purpose memory devices such as an SD card, a memory stick, and a USB memory, a RAID system including a flash SSD, and a storage area network (SAN).

FIG. 2 is a diagram for explaining a general memory array configuration of a NAND flash memory in the base technology for the present invention. FIG. 6 is a diagram for explaining memory cell threshold voltage distribution and data logic assignment of a multi-level NAND flash memory in the base technology for the present invention. In the base technology for the present invention, it is a diagram for explaining parasitic capacitance coupling between adjacent floating gates in a memory array plane of a NAND flash memory. FIG. 5 is a diagram for explaining parasitic capacitance coupling between adjacent floating gates in a memory array cross section in the word line direction of a NAND flash memory in the premise technique for the present invention. FIG. 5 is a diagram for explaining parasitic capacitance coupling between adjacent floating gates in a memory array cross section in the bit line direction of a NAND flash memory in the base technology for the present invention. In the base technology for the present invention, it is a diagram for explaining the threshold voltage fluctuation due to the proximity effect in the NAND flash memory. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a configuration of a NAND flash memory system according to a first embodiment of the present invention. FIG. 3 is a diagram for explaining a write operation in the NAND flash memory system according to the first embodiment of the present invention, where (a) shows a normal write operation, and (b) shows a write operation of the present embodiment. . FIG. 3 is a diagram for explaining page allocation in the NAND flash memory system according to the first embodiment of the present invention. 5 is a flowchart for explaining a data conversion processing method in the memory controller in the NAND flash memory system according to the first embodiment of the present invention; 5 is a flowchart for explaining a method of actually measuring a parasitic capacitance coupling coefficient in the NAND flash memory system according to the first embodiment of the present invention. In the NAND flash memory system according to the second embodiment of the present invention, it is a diagram for explaining a reduction in capacity of a write unit by securing a shield region.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 NAND type flash memory chip 2 Memory controller 11 Memory array 12 X decoder 13 Sense circuit / write data buffer 14 Management area 21 Work RAM
22 Code ROM
23 CPU
WL Word line BL Bit line MC Memory cell STD, STS Control signal CS Common source line FG Floating gate

Claims (11)

A flash memory having a plurality of memory cells, and a memory controller for controlling writing to each memory cell of the flash memory,
In the flash memory, each memory cell stores information of 2 bits or more, and an erase block is a write unit.
The memory controller calculates in advance the increase amount of the threshold voltage due to the proximity effect from the data pattern and the parasitic capacitance coupling coefficient for all the memory cells of the erase block so that the target threshold voltage is obtained after the erase block is written. A flash memory system, wherein a write verify level is adjusted in advance for each memory cell before writing. The flash memory system according to claim 1.
The parasitic capacitance coupling coefficient is measured for each lot, for each wafer, for each chip, for each bank, or for each erase block, and this measured value is written in the management area of the flash memory.
The memory controller calculates a verification level correction amount for the influence of the proximity effect using an actual value written in the management area, and corrects the proximity effect due to manufacturing variation. Flash memory system. The flash memory system according to claim 1.
In the flash memory, each memory cell stores log ₂ n-bit information, and reading of n value is writing of m value where m> n,
The memory controller converts the n-value data pattern into the m-value data pattern for correcting the proximity effect, and writes the converted m-value converted data pattern. Flash memory system. The flash memory system according to claim 1.
The memory controller performs a correction calculation of the proximity effect based on the data pattern and the parasitic capacitance coupling coefficient, and transfers the converted data pattern after the correction calculation to the flash memory. Memory system. The flash memory system according to claim 1.
When generating the converted data pattern in which the proximity effect is corrected, the memory controller predicts and calculates the threshold voltage of each memory cell after writing from the user data to be written, and writes while adjusting the verify level at the time of writing. A later threshold voltage is calculated, and the iterative calculation is repeated until the difference between the target threshold voltage at the end of writing of the erase block and the predicted calculated threshold voltage is within an allowable range. And flash memory system. A flash memory having a plurality of memory cells, and a memory controller for controlling writing to each memory cell of the flash memory,
In the flash memory, each memory cell stores information of 2 bits or more, a divided block obtained by dividing an erase block is used as a writing unit, and a memory cell located at a physical boundary of the divided is not used for writing and serves as a shield. Used,
The memory controller calculates an increase amount of a threshold voltage due to the proximity effect in advance from a data pattern and a parasitic capacitance coupling coefficient for all the memory cells of the divided block so that a target threshold voltage is obtained after the writing of the divided block is completed. A flash memory system, wherein a write verify level is adjusted in advance for each memory cell before writing. The flash memory system according to claim 6.
The parasitic capacitance coupling coefficient is measured for each lot, for each wafer, for each chip, for each bank, or for each divided block, and this measured value is written in the management area of the flash memory.
The memory controller calculates a verification level correction amount for the influence of the proximity effect using an actual value written in the management area, and corrects the proximity effect due to manufacturing variation. Flash memory system. The flash memory system according to claim 6.
In the flash memory, each memory cell stores log ₂ n-bit information, and reading of n value is writing of m value where m> n,
The memory controller converts the n-value data pattern into the m-value data pattern for correcting the proximity effect, and writes the converted m-value converted data pattern. Flash memory system. The flash memory system according to claim 6.
The memory controller performs a correction calculation of the proximity effect based on the data pattern and the parasitic capacitance coupling coefficient, and transfers the converted data pattern after the correction calculation to the flash memory. Memory system. The flash memory system according to claim 6.
When generating the converted data pattern in which the proximity effect is corrected, the memory controller predicts and calculates the threshold voltage of each memory cell after writing from the user data to be written, and writes while adjusting the verify level at the time of writing. A later threshold voltage is calculated, and the iterative calculation is repeated until a difference between the target threshold voltage at the end of writing of the divided block and the predicted calculated threshold voltage is within an allowable range. And flash memory system. A flash memory having a plurality of memory cells, and a memory controller for controlling writing to each memory cell of the flash memory,
In the flash memory, each memory cell stores log ₂ n-bit information, and reading of n value is writing of m value where m> n,
The memory controller converts the n-value data pattern into the m-value data pattern to correct the proximity effect, and writes the converted m-value converted data pattern. Memory system.

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