JP2009508187A - クリティカルセクションをトランザクション的に実行することによるロックの回避 - Google Patents

クリティカルセクションをトランザクション的に実行することによるロックの回避 Download PDF

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Publication number
JP2009508187A
JP2009508187A JP2008524994A JP2008524994A JP2009508187A JP 2009508187 A JP2009508187 A JP 2009508187A JP 2008524994 A JP2008524994 A JP 2008524994A JP 2008524994 A JP2008524994 A JP 2008524994A JP 2009508187 A JP2009508187 A JP 2009508187A
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Japan
Prior art keywords
critical section
transactional execution
program
transactionally
lock
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Pending
Application number
JP2008524994A
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English (en)
Japanese (ja)
Inventor
マーク エス． モイア，
マーク トレンブレイ，
シャイレンダー チョードリー，
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Sun Microsystems Inc
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Sun Microsystems Inc
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Filing date
Publication date
Priority claimed from US11/195,093 external-priority patent/US7398355B1/en
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of JP2009508187A publication Critical patent/JP2009508187A/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/52—Binary to binary

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2008524994A 2005-08-01 2006-07-21 クリティカルセクションをトランザクション的に実行することによるロックの回避 Pending JP2009508187A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/195,093 US7398355B1 (en) 2003-02-13 2005-08-01 Avoiding locks by transactionally executing critical sections
PCT/US2006/028152 WO2007015925A1 (fr) 2005-08-01 2006-07-21 Elimination des verrous au moyen de l'execution transactionnelle de sections critiques

Publications (1)

Publication Number Publication Date
JP2009508187A true JP2009508187A (ja) 2009-02-26

Family

ID=37309335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008524994A Pending JP2009508187A (ja) 2005-08-01 2006-07-21 クリティカルセクションをトランザクション的に実行することによるロックの回避

Country Status (3)

Country Link
EP (1) EP1913473A1 (fr)
JP (1) JP2009508187A (fr)
WO (1) WO2007015925A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010244544A (ja) * 2009-04-08 2010-10-28 Intel Corp マルチスレッドのためのレジスタチェックポイントメカニズム
JP2013537334A (ja) * 2010-09-25 2013-09-30 インテル コーポレイション ハードウェア制限に基づく調整可能なトランザクション・サイズを利用してコードを動的に最適化する装置、方法およびシステム
JP2015523651A (ja) * 2012-06-15 2015-08-13 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ コンピューティング環境においてマシン命令を実行するための方法、システム、およびプログラム（トランザクション開始／終了命令）
JP2015526790A (ja) * 2012-06-15 2015-09-10 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ トランザクション処理における選択されたレジスタの保存／復元
US9250980B2 (en) 2009-12-18 2016-02-02 International Business Machines Corporation System, method, program, and code generation unit
JP2017509083A (ja) * 2014-03-27 2017-03-30 インテル コーポレイション バイナリトランザクションベースのプロセッサによるロックエリジョン

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8627014B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Memory model for hardware attributes within a transactional memory system
US9448796B2 (en) 2012-06-15 2016-09-20 International Business Machines Corporation Restricted instructions in transactional execution
US10437602B2 (en) 2012-06-15 2019-10-08 International Business Machines Corporation Program interruption filtering in transactional execution
US9740549B2 (en) 2012-06-15 2017-08-22 International Business Machines Corporation Facilitating transaction completion subsequent to repeated aborts of the transaction
US9384004B2 (en) 2012-06-15 2016-07-05 International Business Machines Corporation Randomized testing within transactional execution
US9772854B2 (en) 2012-06-15 2017-09-26 International Business Machines Corporation Selectively controlling instruction execution in transactional processing
US8688661B2 (en) 2012-06-15 2014-04-01 International Business Machines Corporation Transactional processing
US9436477B2 (en) 2012-06-15 2016-09-06 International Business Machines Corporation Transaction abort instruction
US20130339680A1 (en) 2012-06-15 2013-12-19 International Business Machines Corporation Nontransactional store instruction
US8682877B2 (en) 2012-06-15 2014-03-25 International Business Machines Corporation Constrained transaction execution
CN107239415B (zh) * 2016-03-28 2020-02-14 华为技术有限公司 一种执行临界区操作的方法及装置
CN114706691B (zh) * 2022-04-15 2025-03-18 郑州信大捷安信息技术股份有限公司 一种基于文件锁的多任务互斥方法和系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040162967A1 (en) * 2003-02-13 2004-08-19 Marc Tremblay Start transactional execution (STE) instruction to support transactional program execution
WO2004075054A1 (fr) * 2003-02-13 2004-09-02 Sun Microsystems Inc. Instruction d'echec dans la prise en charge des transactions pendant l'execution d'un programme
US20040187123A1 (en) * 2003-02-13 2004-09-23 Marc Tremblay Selectively unmarking load-marked cache lines during transactional program execution

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040162967A1 (en) * 2003-02-13 2004-08-19 Marc Tremblay Start transactional execution (STE) instruction to support transactional program execution
WO2004075054A1 (fr) * 2003-02-13 2004-09-02 Sun Microsystems Inc. Instruction d'echec dans la prise en charge des transactions pendant l'execution d'un programme
US20040187123A1 (en) * 2003-02-13 2004-09-23 Marc Tremblay Selectively unmarking load-marked cache lines during transactional program execution

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JPN7011004294; Ｍｏｉｒ，Ｍａｒｋ: 'Ｈｙｂｒｉｄ　Ｔｒａｎｓａｃｔｉｏｎａｌ　Ｍｅｍｏｒｙ' Ｓｕｎ　Ｍｉｃｒｏｓｙｓｔｅｍｓ　Ｌａｂｏｒａｔｏｒｉｅｓ　Ｐａｐｅｒ , 200507 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010244544A (ja) * 2009-04-08 2010-10-28 Intel Corp マルチスレッドのためのレジスタチェックポイントメカニズム
US9940138B2 (en) 2009-04-08 2018-04-10 Intel Corporation Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations
US9250980B2 (en) 2009-12-18 2016-02-02 International Business Machines Corporation System, method, program, and code generation unit
US9904581B2 (en) 2009-12-18 2018-02-27 International Business Machines Corporation System, method, program, and code generation unit
US10169092B2 (en) 2009-12-18 2019-01-01 International Business Machines Corporation System, method, program, and code generation unit
JP2013537334A (ja) * 2010-09-25 2013-09-30 インテル コーポレイション ハードウェア制限に基づく調整可能なトランザクション・サイズを利用してコードを動的に最適化する装置、方法およびシステム
JP2015523651A (ja) * 2012-06-15 2015-08-13 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ コンピューティング環境においてマシン命令を実行するための方法、システム、およびプログラム（トランザクション開始／終了命令）
JP2015526790A (ja) * 2012-06-15 2015-09-10 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ トランザクション処理における選択されたレジスタの保存／復元
JP2017509083A (ja) * 2014-03-27 2017-03-30 インテル コーポレイション バイナリトランザクションベースのプロセッサによるロックエリジョン

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Publication number Publication date
WO2007015925A1 (fr) 2007-02-08
EP1913473A1 (fr) 2008-04-23

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