JP2012105455A - Motor control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that noise resistance amount detection means in conventional examples can only detect and monitor the intensity of noise as a time width, cannot detect noise of a very short time width for example, and furthermore cannot detect noise when a factor other than noise causes a turbulence in a signal.SOLUTION: In a motor control device provided with an inverter circuit 1 and a current detector 4 for detecting the three-phase AC output current of an inverter circuit 1, clock signals and data signals of AD converters 5, 6 are inputted to the current detector 4, a noise level is detected by measuring the clock numbers within a certain time period, and not only a normal noise but also a noise of a very short time width can be detected.

Description

  The present invention relates to a motor control device including a current detection circuit capable of detecting a noise level.

  There is Patent Document 1 as a background art of this technical field. This Patent Document 1 describes “an information processing / control device that increases the noise resistance by monitoring the output of an analog / digital signal conversion circuit and its noise tolerance detecting means”.

JP 2003-148997 A

  As described above, Patent Document 1 describes noise tolerance detection means. However, the information processing / control apparatus of Patent Document 1 can only detect and monitor the magnitude of noise as a time width. Such an information processing / control device cannot detect noise having a very short time width, for example. For example, it cannot be detected when a signal is disturbed due to a cause other than noise.

  Therefore, the present invention provides a control device that can detect not only normal noise but also noise with a very short time width, for example, detecting noise as the number of pulses in a certain time instead of time width. It is an object of the present invention to provide a control device capable of performing the above.

  It is another object of the present invention to provide a control device that can detect when a signal is disturbed due to a cause other than noise.

  For example, it measures the pulse width of signals and the phase difference between signals, outputs a warning alarm when measurement results vary, and determines that a failure has occurred if the signal level is H level or L level for a certain period of time. It is an object of the present invention to provide a control device that outputs a warning alarm.

In order to solve the above-described means, the present invention adopts the configurations described in the claims.
The present invention includes a plurality of means for solving the above-mentioned problems. For example, the noise is measured by measuring the number of clocks in a predetermined time before and after the digital filter for removing noise with respect to the clock. A current detection circuit capable of detecting the level is provided.

  The motor control device of the present invention includes an inverter circuit that performs a switching operation by a gate drive signal supplied from a control circuit via a base drive circuit, converts a DC voltage, and outputs three-phase AC power, and a servo from the inverter circuit. A current detection device that detects a current of a three-phase AC output supplied to a motor and detects digital data converted from an analog signal into a digital signal by an AD converter. The digital data signal and the clock signal of the AD converter are input to and a noise level is detected based on the clock signal.

  The motor control device according to the present invention is characterized in that the noise level is detected by measuring the number of clocks of the clock signal during a predetermined time.

  Further, the motor control device of the present invention measures the clock signal and the digital signal by measuring the time when the clock signal and the digital data signal output from the AD converter are at the H level and the time when the digital data signal is at the L level, respectively. The pulse width of the data signal is measured.

  The motor control device according to the present invention is characterized in that a phase difference between the clock signal output from the AD converter and the digital data signal is measured.

  In addition, the motor control device of the present invention is characterized by detecting the noise occurrence frequency by changing the clock number measurement time.

  In addition, the motor control device of the present invention measures the frequency of occurrence of clock number measurement abnormality, pulse width measurement abnormality, and phase difference measurement abnormality, and identifies the noise source by detecting the frequency and magnitude of noise generation. It is characterized by that.

  In the motor control device of the present invention, the current detection circuit includes a digital filter that removes noise of the clock signal, measures the number of clocks during a predetermined time before and after the digital filter, It is characterized by comparing the number of clocks in a certain period before and after.

  Further, the motor control device of the present invention is characterized in that the effect of the digital filter can be known by measuring and comparing the number of clocks in a predetermined time before and after the digital filter.

  In addition, the motor control device of the present invention is characterized in that the number of digital filters in the current detection circuit and the filter frequency are changed according to the detected noise level.

  The motor control device of the present invention is characterized in that the number of stages of the digital filter and the filter frequency are changed according to the detected noise level, and the control gain is automatically adjusted to the optimum value accordingly.

  According to the present invention, a control device capable of detecting not only normal noise but also noise having a very short time width, and a control device capable of detecting when a signal is disturbed due to a cause other than noise. Can be provided.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

FIG. 1 is an example of a configuration diagram of a motor control device. FIG. 2 is a configuration diagram of a current detection circuit according to the present invention. FIG. 3 is a flowchart for explaining a method for determining in which circuit the alarm and warning are detected. FIG. 4 is a flowchart for explaining a warning or alarm detection method when measuring the number of clocks. FIG. 5 is a flowchart for explaining the operation of the clock number measuring circuit. FIG. 6 is a flowchart for explaining a warning or alarm detection method when measuring the pulse width of a clock or data. FIG. 7 is a flowchart for explaining the operation of the circuit for measuring the time when the clock or data is at the H level. FIG. 8 is a flowchart for explaining the operation of the circuit for measuring the time when the clock or data is at the L level. FIG. 9 is a flowchart for explaining a warning or alarm detection method when measuring the phase difference between the clock and data. FIG. 10 is a flowchart for explaining the operation of a circuit for detecting the phase difference between the clock and data as the time from when the data becomes H level to when the clock becomes L level. FIG. 11 is a flowchart for explaining the operation of a circuit for detecting the phase difference between the clock and data as the time from when the data becomes L level to when the clock becomes L level. FIG. 12 is an example of a timing operation diagram of the clock and data before and after the digital filter during normal operation. FIG. 13 is an example of a timing operation diagram of the clock and data before and after the digital filter when noise is generated. FIG. 14 is an example of a timing operation diagram for explaining the pulse width measurement results at normal time and abnormal time. FIG. 15 is an example of a timing operation diagram for explaining a phase difference measurement result between a normal time and an abnormal time.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In this embodiment, an example of a motor control device having a current detection circuit protection method will be described.
FIG. 1 is an example of a configuration diagram of a motor control device having a current detection circuit protection system according to the present embodiment. In this figure, reference numeral 1 denotes an inverter circuit, which is composed of six switching elements Q1 to Q6 and a three-phase AC inverter circuit composed of six flywheel diodes D1 to D6.

  The inverter circuit 1 performs a switching operation by a gate drive signal supplied from the control circuit 3 via the base drive circuit 2, converts the DC voltage between the PL line and the NL line into three-phase AC power, and outputs the UL line. And outputs a three-phase AC voltage between the VL line and the WL line. For this reason, the base drive circuit 2 and the control circuit 3 are configured such that predetermined signals can be exchanged with each other via the line CS1.

  A servo motor 7 is connected to a driven portion (not shown) via a torque transmission system (not shown), and is set in a predetermined direction in accordance with the three-phase AC power supplied from the inverter circuit 1. It rotates at a predetermined rotational speed with torque, and moves and drives a drive mechanism such as a machining production line with a predetermined speed and a predetermined force to perform positioning.

  At this time, the rotational speed and rotational position of the servo motor 7 are detected by the encoder 8 built in the servo motor and fed back to the control circuit 3 via the line CS3. At this time, the current UL flowing in the U phase of the servo motor 7 is converted from an analog signal to a digital signal by the AD converter 5 and the WL flowing in the W phase is converted by the AD converter 6 and detected by the current detection circuit 4. The This detected current value is fed back to the control circuit 3 via the line CS2 and reflected in the control of the inverter circuit 1.

  Next, current detection will be described. When the AD converter 5 receives the current UL flowing in the U phase of the servo motor 7 as an analog voltage, the AD converter 5 converts the current UL into digital data synchronized with the clock output by the AD converter 5 and outputs the digital data. Similarly, the AD converter 6 converts the current WL flowing in the W phase of the servo motor 7 into digital data synchronized with the clock output by itself, and outputs the digital data. The clock and data output by the AD converters 5 and 6 are serial-parallel converted in the current detection circuit 4 and current calculation processing is performed.

  At this time, when the clock and data output from the AD converters 5 and 6 cause waveform breakage due to noise, normal current calculation processing cannot be performed inside the current detection circuit 4, and normal motor control can be performed. Can not. Also, if the AD converter itself has an abnormality or failure, the clock and data cycle may be disturbed, or data may not be output in synchronization with the clock, that is, the phase difference between the clock and data may have changed. Therefore, normal current calculation processing cannot be performed, and normal motor control cannot be performed.

  Therefore, in this embodiment, the influence of noise is prevented as described below, the host apparatus is notified that it is affected by the noise, and the host apparatus is notified of a failure / failure of the AD converter itself. FIG. 2 shows a current detection circuit according to this embodiment. The motor current is converted into serial data in synchronization with the clock by the AD converter 9 and input to the current detection circuit 10.

  Noise is removed from the input clock by the digital filter 11, and noise is removed from the data by the digital filter 12. The clock and data from which noise has been removed are subjected to serial-parallel conversion by the serial-parallel conversion circuit 16, and current calculation is performed by the control circuit 18.

  This current detection circuit has a protection circuit for preventing malfunction due to noise and preventing malfunction due to failure or failure of the AD converter itself or its peripheral circuits. The clock number measurement circuit 13 can monitor the clocks at the front and rear stages of the digital filter, and can measure the number of clocks during a specified time. The clock / data pulse width measurement circuit 14 can measure the pulse width of the clock and data after passing through the digital filter.

  The clock and data phase difference measurement circuit 15 can measure the phase difference between the clock and data after passing through the digital filter. Each of these three measurement circuits has a function of determining whether a measured value is a warning level or an alarm level, and outputs an alarm or warning to the determination circuit 17 when the determination level is exceeded. The determination circuit 17 determines in which circuit an alarm or warning has occurred, and notifies the control circuit 18 of it.

  The operation of the determination circuit 17 in FIG. 2 will be described with reference to the flowchart in FIG. First, in processing step S1, it is checked whether the clock number measurement result is satisfactory. If NO, that is, if there is a problem with the clock number measurement result, it is determined that the clock number is abnormal, and the control circuit 18 in FIG. 2 is notified. If YES, that is, if it is determined that there is no problem in the clock number measurement result, the process proceeds to processing step S2.

  In processing step S2, it is checked whether there is a problem with the measurement result of the pulse width of the clock or data. If NO, that is, if there is a problem with the pulse width measurement result, it is determined that the pulse width is abnormal, and the control circuit 18 shown in FIG. If YES, that is, if it is determined that there is no problem in the pulse width measurement result, the process proceeds to processing step S3.

  In processing step S3, it is checked whether there is a problem with the measurement result of the phase difference between the clock and data. If NO, that is, if there is a problem in the phase difference measurement result, it is determined that the phase difference is abnormal, and the control circuit 18 in FIG. 2 is notified. If YES, that is, if it is determined that there is no problem in the phase difference measurement result, it is determined that there is no abnormality in all the measurement results.

  The operation of the clock number measurement circuit 13 in FIG. 2 will be described with reference to the flowchart in FIG. First, in processing step S11, when the measurement result of the clock number is small, the warning level Nlw and the alarm level Nla for determining whether the measurement result is normal or abnormal and when the measurement result of the clock number is large, the normal or abnormal A warning level Nhw and an alarm level Nha are set to determine whether or not.

  Next, the operation of the clock number measurement counter is started in processing step S12, and when the measurement of the clock number for measuring the clock number is completed, the clock number N measured in processing step S12 in processing step S13 is higher than the warning level Nhw. Judge whether it is larger. If the determination is YES, that is, if the clock number N is larger than the warning level Nhw, the process proceeds to processing step S14 to determine whether the clock number N is larger than the alarm level Nha.

  If the determination is YES, that is, if the number of clocks N is larger than the alarm level Nha, the process proceeds to processing step S17, where an alarm is output to the host device, and the system is stopped. If the determination is NO, that is, if the number of clocks N is smaller than the alarm level Nha, the process proceeds to process step S18, a warning is output to the host device, and the process returns to process step S13.

  If NO in process step S13, that is, if the clock number N is smaller than the warning level Nhw, the process proceeds to process step S15, where it is determined whether the clock number N is smaller than the alarm level Nlw. If the determination is YES, that is, if the clock number N is smaller than the warning level Nlw, the process proceeds to processing step S16 to determine whether the clock number N is smaller than the alarm level Nla.

  If the determination is YES, that is, if the number of clocks N is smaller than the alarm level Nla, the process proceeds to processing step S19, an alarm is output to the host device, and the system is stopped. If the determination is NO, that is, if the number of clocks N is larger than the alarm level Nla, the process proceeds to process step S110, a warning output is made to the host device, and the process returns to process step S13.

  The operation of the clock number measurement counter in process step S12 of FIG. 4 will be described with reference to the flowchart of FIG. First, in step S121, a fixed period counter for measuring the time for measuring the number of clocks is operated. Next, a counter for measuring the number of clocks is operated in processing step S122. In process step S123, the process waits until the value of the fixed period counter reaches a specified value, and the process proceeds to process step S124.

  In processing step S124, the value of the fixed cycle counter is cleared. In processing step S125, the clock number measurement result N is stored in the register. In processing step S126, the value of the clock number measurement counter is cleared, and the process returns to processing step S121. Repeat the operation.

  The operation of the clock and data pulse width measurement circuit 14 of FIG. 2 will be described with reference to the flowchart of FIG. First, in processing step S21, the warning level THlw and the alarm level THla for determining whether the measurement is normal or abnormal when the measurement result of the pulse width at the H level is small, and the measurement result of the pulse width at the H level. Is set to a warning level THhw and an alarm level THha for determining whether the value is normal or abnormal.

  Further, when the measurement result of the pulse width at the L level is small, the warning level TLlw and the alarm level TLla for determining whether the measurement result is normal or abnormal, and normal when the measurement result of the pulse width at the L level is large The warning level TLhw and the alarm level TLha are set for determining whether the error is abnormal or not, and the process proceeds to processing step S22.

  In step S22, the pulse width is measured, and it is determined whether the pulse width measured in the processing steps after processing step S23 is normal or abnormal. In process step S23, it is determined whether the determination target is the pulse width TH on the H side. If the determination is YES, that is, if the determination target is the pulse width TH on the H side, the process proceeds to processing step S24. In process step S24, it is determined whether the measured pulse width TH is larger than the warning level THhw. If the determination is YES, that is, if the pulse width TH is greater than the warning level THhw, the process proceeds to processing step S25, where it is determined whether the pulse width TH is greater than the alarm level THha.

  If the determination is YES, that is, if the pulse width TH is larger than the alarm level THha, the process proceeds to processing step S28, an alarm is output to the host device, and the system is stopped. If the determination is NO, that is, if the pulse width TH is smaller than the alarm level THha, the process proceeds to process step S29, a warning is output to the host device, and the process returns to process step S23.

  If the determination in process step S24 is NO, that is, if the pulse width TH is smaller than the warning level THhw, the process proceeds to process step S26, where it is determined whether the pulse width TH is smaller than the alarm level THlw. If the determination is YES, that is, if the pulse width TH is smaller than the warning level THlw, the process proceeds to processing step S27 to determine whether the pulse width TH is smaller than the alarm level THla.

  If the determination is YES, that is, if the pulse width TH is smaller than the alarm level THla, the process proceeds to processing step S210 to output an alarm to the host device and stop the system. If the determination is NO, that is, if the pulse width TH is larger than the alarm level THla, the process proceeds to process step S211, a warning is output to the host device, and the process returns to process step S23.

  If the determination in process step S23 is NO, that is, if the determination target is not the pulse width TH on the H side but the pulse width TL on the L side, the process proceeds to process step S212. In process step S212, it is determined whether the measured pulse width TL is larger than the warning level TLhw. If the determination is YES, that is, if the pulse width TL is larger than the warning level TLhw, the process proceeds to processing step S213, where it is determined whether the pulse width TL is larger than the alarm level TLha.

  If the determination is YES, that is, if the pulse width TL is larger than the alarm level TLha, the process proceeds to processing step S216 to output an alarm to the host device and stop the system. If the determination is NO, that is, if the pulse width TL is smaller than the alarm level TLha, the process proceeds to process step S217, a warning is output to the host device, and the process returns to process step S23.

  If the determination in process step S212 is NO, that is, if the pulse width TL is smaller than the warning level TLhw, the process proceeds to process step S214, and it is determined whether the pulse width TL is smaller than the alarm level TLlw. If the determination is YES, that is, if the pulse width TL is smaller than the warning level TLlw, the process proceeds to processing step S215 to determine whether the pulse width TL is smaller than the alarm level TLla.

  If the determination is YES, that is, if the pulse width TL is smaller than the alarm level TLla, the process proceeds to processing step S218 to output an alarm to the host device and stop the system. If the determination is NO, that is, if the pulse width TL is larger than the alarm level TLla, the process proceeds to process step S219, a warning is output to the host device, and the process returns to process step S23.

  The operation of the pulse width measurement counter in process step S22 of FIG. 6 will be described using the flowcharts of FIGS. In FIG. 7, the pulse width at the H level is measured. First, the rising edge of the measurement target signal is detected in processing step S221, and the process proceeds to processing step S222. The processing step S222 starts the operation of the counter for measuring the pulse width, the processing step S223 detects the falling edge of the signal to be measured, the processing step S224 stores the pulse width measurement result TH in the register, and the processing step S221 follows. Return and repeat the above operation.

  In FIG. 8, the pulse width at the L level is measured. First, in processing step S225, the falling edge of the signal to be measured is detected, and the process proceeds to processing step S226. The operation of the counter that measures the pulse width is started in processing step S226, the rising edge of the signal to be measured is detected in processing step S227, the pulse width measurement result TL is stored in the register in processing step S228, and the process returns to processing step S225. Repeat the above operation.

  The operation of the clock and data phase difference measurement circuit 15 of FIG. 2 will be described with reference to the flowchart of FIG. The phase difference in this embodiment is the time from when data changes until the falling edge of the clock is detected. The time from the rise of data to the detection of the falling edge of the clock is PH, and the time from the fall of the data to the detection of the falling edge of the clock is PL.

  First, in processing step S31, when the measurement result of the phase difference PH is small, the setting of the warning level PHlw and the alarm level PHla for determining whether the measurement result is normal or abnormal and the measurement result of the phase difference PH are large. The warning level PHhw and the alarm level PHha are set for determining whether the alarm is abnormal.

  Further, when the measurement result of the phase difference PL is small, the warning level PLlw and the alarm level PLla for determining whether the measurement result is normal or abnormal are determined, and when the measurement result of the phase difference PL is large, it is determined whether the measurement result is normal or abnormal. The warning level PLhw and the alarm level PLha are set, and the process proceeds to processing step S32.

  The phase difference is measured in the processing step S32, and it is determined whether the phase difference measured in the processing steps after the processing step S33 is normal or abnormal. In process step S33, it is determined whether the determination target is the phase difference PH. If the determination is YES, that is, if the determination target is the phase difference PH, the process proceeds to processing step S34. In processing step S34, it is determined whether or not the measured phase difference PH is larger than the warning level PHhw. If the determination is YES, that is, the phase difference PH is greater than the warning level PHhw, the process proceeds to processing step S35, where it is determined whether the phase difference PH is greater than the alarm level PHha.

  If the determination is YES, that is, if the phase difference PH is greater than the alarm level PHha, the process proceeds to step S38, where an alarm is output to the host device and the system is stopped. If the determination is NO, that is, if the phase difference PH is smaller than the alarm level PHha, the process proceeds to process step S39, a warning is output to the host device, and the process returns to process step S33.

  When the determination is NO in processing step S34, that is, when the phase difference PH is smaller than the warning level PHhw, the process proceeds to processing step S36, where it is determined whether the phase difference PH is smaller than the alarm level PHlw. If the determination is YES, that is, if the phase difference PH is smaller than the warning level PHlw, the process proceeds to processing step S37 to determine whether the phase difference PH is smaller than the alarm level PHla.

  If the determination is YES, that is, if the phase difference PH is smaller than the alarm level PHla, the process proceeds to processing step S310 to output an alarm to the host device and stop the system. If the determination is NO, that is, the phase difference PH is greater than the alarm level PHla, the process proceeds to process step S311, a warning is output to the host device, and the process returns to process step S33.

  If the determination in process step S33 is NO, that is, if the determination target is not the phase difference PH but the phase difference PL, the process proceeds to process step S312. In processing step S312, it is determined whether or not the measured phase difference PL is larger than the warning level PLhw. If the determination is YES, that is, if the phase difference PL is greater than the warning level PLhw, the process proceeds to processing step S313, and it is determined whether the phase difference PL is greater than the alarm level PLha.

  If the determination is YES, that is, if the phase difference PL is larger than the alarm level PLha, the process proceeds to processing step S316 to output an alarm to the host device and stop the system. If the determination is NO, that is, the phase difference PL is smaller than the alarm level PLha, the process proceeds to process step S317, a warning output is made to the host device, and the process returns to process step S33.

  If the determination in process step S312 is NO, that is, the phase difference PL is smaller than the warning level PLhw, the process proceeds to process step S314, and it is determined whether the phase difference PL is smaller than the alarm level PLlw. If the determination is YES, that is, if the phase difference PL is smaller than the warning level PLlw, the process proceeds to processing step S315 to determine whether the phase difference PL is smaller than the alarm level PLla.

  If the determination is YES, that is, if the phase difference PL is smaller than the alarm level PLla, the process proceeds to processing step S318 to output an alarm to the host device and stop the system. If the determination is NO, that is, the phase difference PL is larger than the alarm level PLla, the process proceeds to process step S319, a warning output is made to the host device, and the process returns to process step S33.

  The operation of the phase difference measurement counter in process step S32 of FIG. 9 will be described with reference to the flowcharts of FIGS.

  In FIG. 10, the time from when the data rises to when the falling edge of the clock is detected is measured. First, a rising edge of data is detected in process step S321, and the process proceeds to process step S322. In processing step S322, it is determined whether or not the clock is at the H level. If YES, that is, if the clock is at the H level, the process proceeds to processing step S323 and the operation of the phase difference measurement counter is started. Next, the falling edge of the clock is detected in processing step S324, the phase difference measurement result PH is stored in the register in processing step S325, the process returns to processing step S321, and the above operation is repeated.

  In FIG. 11, the time from when the data falls to when the falling edge of the clock is detected is measured. First, a falling edge of data is detected in process step S326, and the process proceeds to process step S327. In processing step S327, it is determined whether or not the clock is at the H level. If YES, that is, if the clock is at the H level, the process proceeds to processing step S328 and the operation of the phase difference measurement counter is started. Next, the falling edge of the clock is detected in processing step S329, the phase difference measurement result PL is stored in the register in processing step S3210, the process returns to processing step S326, and the above operation is repeated.

  The operation of this embodiment will be described with reference to the timing charts of FIGS. FIG. 12 shows an example of clock and data waveforms before and after the digital filter when a normal clock and data are output from the AD converter. As shown in the figure, the clock and data input to the digital filter have a delay corresponding to the number of stages of the digital filter, and are output from the digital filter in synchronization with the reference clock.

  FIG. 13 shows an example of the waveform when the waveform breakage occurs due to noise in the clock and data output from the AD converter, and the waveform when the waveform breakage is removed by the digital filter. At this time, when the number of clocks before passing through the digital filter is measured, the count result increases by the number N of clock cracks due to noise, and an alarm or warning is output. By preventing the noise waveform from being broken by the digital filter, the measurement result of the clock number becomes a normal count value of 4.

  FIG. 14 is an example of a timing diagram for the pulse width measurement results of the normal clock and data and the abnormal clock and data. In this example, regarding the data, the pulse width measurement result is shorter in the THD1 in the abnormal state than in the THD1 in the normal state, and the pulse width measurement result is longer in the TLD1 in the abnormal state than in the TLD1 in the normal state. Is output. As for the clock, the pulse width measurement result is shorter in the abnormal TLC1 than in the normal TLC1, and the pulse width measurement result is longer in the abnormal THC2 than in the normal THC2, and an alarm or warning is output.

  FIG. 15 is an example of a timing diagram for the phase difference measurement result between the normal clock and data and the abnormal clock and data. In this example, the phase difference measurement result is longer in PL1 at the time of abnormality than PL1 at the time of normality, and an alarm or warning is output.

  The motor control device of the present invention can measure the pulse width of the clock signal and the digital data signal, measure the phase difference between the clock signal and the digital data signal, and detect the noise occurrence frequency. By measuring the frequency of occurrence of width measurement abnormality and phase difference measurement abnormality and detecting the frequency and magnitude of noise generation, the noise source can be specified.

  Further, the motor control device of the present invention can know the effect of the digital filter by measuring the number of clocks in a certain time before and after the digital filter and comparing the number of clocks in the certain time before and after the digital filter, Change the number of digital filter stages and filter frequency in the current detection circuit according to the detected noise level, change the number of digital filter stages and filter frequency according to the detected noise level, and control accordingly Gain can be automatically adjusted to the optimum value.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. In addition, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files for realizing each function can be stored in a recording device such as a memory, a hard disk, or an SSD, or a recording medium such as an IC card, an SD card, or a DVD.

  Further, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

DESCRIPTION OF SYMBOLS 1 Inverter circuit 2 Base drive circuit 3 Control circuit 4 Current detection circuit 5 AD converter 6 AD converter 7 Servo motor 8 Encoder 9 AD converter 10 Current detection circuit 11 Digital filter 12 Digital filter 13 Clock number measurement circuit 14 Clock data Pulse width measurement circuit 15 Clock / data phase difference measurement circuit 16 Serial-parallel conversion circuit 17 Determination circuit 18 Control circuit

Claims (10)

An inverter circuit that performs a switching operation by a gate drive signal supplied from a control circuit via a base drive circuit, converts a DC voltage, and outputs three-phase AC power;
In a motor control device comprising: a current detection device that detects a current of a three-phase AC output supplied from the inverter circuit to a servomotor and detects digital data converted from an analog signal to a digital signal by an AD converter; ,
The motor control device, wherein the digital data signal and the clock signal of the AD converter are input to the current detection device, and a noise level is detected based on the clock signal. The motor control device according to claim 1,
A motor control device for detecting a noise level by measuring the number of clocks of the clock signal during a predetermined time. The motor control device according to claim 1,
Measuring the pulse width of the clock signal and the digital data signal by measuring the time when the clock signal and the digital data signal output from the AD converter are at the H level and the time when the digital data signal is at the L level, respectively. A motor control device. The motor control device according to claim 1,
A motor control device that measures a phase difference between the clock signal output from the AD converter and the digital data signal. The motor control device according to claim 1,
A motor control device that detects a frequency of noise occurrence by changing a clock number measurement time. The motor control device according to claim 1,
A motor control device characterized by measuring the frequency of occurrence of clock number measurement abnormality, pulse width measurement abnormality, and phase difference measurement abnormality, and identifying the noise source by detecting the frequency and magnitude of noise generation. The motor control device according to claim 2,
The current detection device includes a digital filter that removes noise of the clock signal, measures the number of clocks in a certain time before and after the digital filter, and determines the number of clocks in a certain time before and after the digital filter. A motor controller characterized by comparing. The motor control device according to claim 7,
The motor control device characterized in that the effect of the digital filter can be known by measuring and comparing the number of clocks in a certain time before and after the digital filter. The motor control device according to claim 7,
A motor control device that changes the number of stages of digital filters and the filter frequency in the current detection device in accordance with the detected noise level. The motor control device according to claim 9,
A motor control device, wherein the number of stages of the digital filter and the filter frequency are changed according to the detected noise level, and the control gain is automatically adjusted to an optimum value accordingly.

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