JP2012155649A - Semiconductor integrated circuit and bus control method of semiconductor integrated circuit - Google Patents

Abstract

When debugging a program using a ROM emulator, it is necessary to provide a dedicated connector on a board on which a CPU is mounted. By adding this connector, the wiring resistance increases and the access timing of the memory is deteriorated. Therefore, a semiconductor integrated circuit that realizes program debugging without affecting the access timing between memories is provided.
A semiconductor integrated circuit includes a memory controller that controls access to a memory, a boundary scan circuit that is disposed between a terminal of the memory controller and an external terminal, and an output of a mode signal that determines an operation mode of the boundary scan circuit. And a timing control circuit that issues a control signal for permitting read access of the memory controller to the memory controller via the boundary scan circuit based on the mode signal when debugging the program.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit and a bus control method for the semiconductor integrated circuit. In particular, the present invention relates to a semiconductor integrated circuit having a program debugging function.

  A circuit used for an embedded device includes a semiconductor integrated circuit that operates as a CPU (Central Processing Unit). For debugging a program to be executed by the CPU, there is a method in which a connector is inserted into a socket of the CPU to be debugged and the function of the CPU is emulated from a computer. Another method is to use a ROM emulator that uses a CPU as a debugging target as it is and downloads a program to an externally provided memory (a memory different from the memory used during normal operation) for debugging. Exists.

  Non-Patent Document 1 discloses a ROM emulator incorporating a ROM. In debugging a program using a ROM emulator, a method in which a CPU and a computer communicate with each other according to a procedure compliant with JTAG (Joint Test Action Group) to access a memory included in the ROM emulator is often adopted. When debugging using JTAG, it is necessary to acquire and set data exchanged between the external terminal of the semiconductor integrated circuit and the CPU, and the semiconductor integrated circuit (CPU) may include a boundary scan circuit. I need it. Non-Patent Document 2 discloses a configuration of a boundary scan circuit.

  Further, Patent Document 1 discloses a semiconductor device that reduces the substrate area and rewrites different types of nonvolatile memories by sharing hardware for data rewriting and boundary scan test. In the technique disclosed in Patent Document 1, a boundary scan circuit is used as a primary storage memory for a program rewrite program.

  Also, in Patent Document 2, among a plurality of signals exchanged between a computer and an expansion unit, a predetermined signal group is transferred after being converted into serial data, and a specific signal that directly affects the operation speed is directly received. A passing interface is disclosed.

JP 2001-236307 A JP 2000-065899 A

Computex, “ROM emulator (ROMiCEminiREM16)”, [online], [searched on January 12, 2011], Internet <URL: http://www.computex.co.jp/products/romicemini/rem.htm > DEBSOL, “boundary scan course”, [online], [searched on January 12, 2011], Internet <URL: http://www.debsol.com/AboutBS01.html>

  The following analysis has been made from the viewpoint of the present invention.

  As described above, debugging by the ROM emulator is performed by downloading a program to a memory different from the memory originally used by the CPU. However, the recent increase in CPU operation clock speed is significant, and the influence of the connector connecting the CPU and ROM emulator cannot be ignored when the CPU operation clock speed increases.

  FIG. 2 is a diagram illustrating an example of a CPU debugging system using a ROM emulator. Details of the debug system shown in FIG. 2 will be described later. In the debugging system shown in FIG. 2, a program necessary for the original operation of the CPU 10 is stored in the ROM 20, and a program to be debugged is downloaded to a memory built in the ROM emulator 2. When the program is debugged, the program stored in the ROM 20 is not used, but the program downloaded to the memory built in the ROM emulator 2 is used. Therefore, at the time of debugging, a connector 40 for switching the connection between the CPU 10 and the ROM 20 and the ROM emulator 2 is necessary.

  If the connector 40 used only for debugging is added on the board on which the CPU 10 is mounted, the resistance component of the connector itself and the wiring resistance associated with the connector are increased, causing signal delay and reflection. As a result, the timing when the CPU 10 accesses the memory (the memory incorporated in the ROM 20 or the ROM emulator 2) is adversely affected. In other words, the presence of the wiring pattern necessary for arranging the connector 40 and the connector 40 increases the wiring resistance, and delays the signal not only during debugging but also in operations other than debugging (normal operation). And reflection occurs.

  As a result, a measure such as inserting a wait is required when accessing the memory from the CPU 10, which is a restriction on the memory access speed of the CPU 10.

  As described above, there are problems to be solved in the prior art.

  In one aspect of the present invention, a semiconductor integrated circuit and a bus control method for a semiconductor integrated circuit that can debug a program without affecting the access timing to the memory are desired.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit capable of executing a program, a memory controller for controlling access to a memory, and a boundary scan arranged between a terminal of the memory controller and an external terminal A JTAG interface capable of outputting a mode signal for determining an operation mode of the boundary scan circuit based on a JTAG signal supplied from the outside, and reading of the memory controller based on the mode signal when debugging a program A timing control circuit that outputs a control signal for permitting access to the boundary scan circuit. The boundary scan circuit is a semiconductor integrated circuit that permits read access to the memory controller based on the control signal. Provided.

  According to a second aspect of the present invention, based on a memory controller for controlling access to a memory, a boundary scan circuit disposed between a terminal of the memory controller and an external terminal, and a JTAG signal given from the outside, A JTAG interface capable of outputting a mode signal for determining an operation mode of a boundary scan circuit, and a bus control method for a semiconductor integrated circuit capable of executing a program, wherein the boundary scan circuit is connected to the boundary scan circuit during program debugging. A step of setting data, a data update step of allowing the memory controller to perform a read operation for one cycle based on the mode signal, and causing the memory controller to read the data; and after the data update step, the memory Controller Bus control method for a semiconductor integrated circuit including the step of prohibiting the read cycle, is provided.

  According to each aspect of the present invention, there are provided a semiconductor integrated circuit and a semiconductor integrated circuit bus control method that can debug a program without affecting the access timing to the memory.

It is a figure for demonstrating the outline | summary of this invention. It is a figure which shows an example of the debugging system of CPU using a ROM emulator. It is a figure which shows one structural example of a semiconductor integrated circuit provided with a boundary scan circuit. 4 is a configuration example of a boundary scan register shown in FIG. 3. It is a figure showing an example of 1 composition of a debugging system containing CPU concerning a 1st embodiment of the present invention. It is a figure which shows an example of an internal structure of CPU shown in FIG. FIG. 7 is a diagram illustrating an example of an internal configuration of a boundary scan register illustrated in FIG. 6. FIG. 7 is a diagram illustrating an example of an internal configuration of a timing control circuit illustrated in FIG. 6. It is a figure which shows the operation timing of the timing control circuit shown in FIG. It is a figure which shows the outline of the operation | movement at the time of debugging by the debug system shown in FIG. It is a timing chart which shows operation | movement of each signal of CPU shown in FIG. It is the figure which showed the signal flow at the time of capture mode. It is the figure which showed the signal flow at the time of scan shift mode. It is the figure which showed the signal flow at the time of update mode. It is a figure which shows the example of 1 structure of the timing control circuit with which CPU which concerns on 2nd Embodiment is provided. FIG. 16 is a diagram showing an operation timing of the timing control circuit shown in FIG. 15.

  First, the outline of the embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, in order to use the ROM emulator, a connector used only for debugging is required. As a result, the wiring resistance of the substrate including the CPU increases as compared with the case where no connector is present. As a result, delay and reflection occur in the address signal and data signal necessary for accessing the memory data. Therefore, it is necessary to adjust the timing for accessing the memory from the CPU, not only during debugging but also during normal operation. That is, it becomes a restriction on the memory access speed of the CPU.

  Therefore, the semiconductor integrated circuit shown in FIG. 1 is provided. The semiconductor integrated circuit shown in FIG. 1 includes a memory controller that controls access to a memory, a boundary scan circuit disposed between a terminal of the memory controller and an external terminal, and a boundary scan circuit based on a JTAG signal supplied from the outside. A JTAG interface capable of outputting a mode signal for determining an operation mode, and a timing control circuit for outputting a control signal for permitting read access of the memory controller to the boundary scan circuit based on the mode signal when debugging a program And.

  When debugging a program, access information to the memory from the CPU is fetched into the computer via the boundary scan circuit, and the result of emulation on the computer is set from the boundary scan circuit to the memory controller. At this time, if the read access of the memory controller is not restricted, a data acquisition operation (data fetch) occurs before the emulation is executed on the computer. Therefore, the memory controller's access to the memory at the time of debugging is restricted, and after the data emulated on the computer can be set, read access in the memory controller is permitted. That is, the memory controller is always in a wait state during debugging. Then, after the computer emulation result is prepared, the emulation result is set in the boundary scan circuit. Thereafter, an instruction to read the emulation result into the memory controller is issued from the JTAG interface, and the JTAG interface outputs the mode signal to the timing control circuit. In the timing control circuit, a control signal for permitting a read cycle is issued from the mode signal to the memory controller, and the boundary scan circuit receiving the control signal permits read access of the memory controller.

  As a result, when debugging a program to be executed by the semiconductor integrated circuit shown in FIG. 1, the program to be debugged can be stored on a computer, which is indispensable for debugging a ROM emulator or the like. It becomes possible to delete the connector. It is possible to suppress signal delays and reflections that have occurred due to the presence of connectors that are required only during debugging, and it is not necessary to adjust the timing of memory access for the purpose of realizing a debugging function. Therefore, it is possible to eliminate restrictions on the memory access speed of the CPU.

  Next, a CPU debugging system using the ROM emulator shown in FIG. 2 will be described. The debugging system shown in FIG. 2 includes an evaluation board 1, a ROM emulator 2, a JTAG master 3, and a PC (Personal Computer) 4. The evaluation board 1 includes a CPU 10, a ROM 20, a CS controller 30, and a connector 40.

  The CPU 10 is a semiconductor integrated circuit that operates as a central processing unit (CPU). The CPU 10 includes a memory controller (hereinafter referred to as MEMC) 101 that controls access to a memory connected to the CPU 10 and a JTAG-IF 102 that serves as an interface for communication signals compliant with JTAG. The MEMC 101 of the CPU 10 and the memory built in the ROM 20 or the ROM emulator 2 are connected via a connector 40.

  The ROM 20 stores a program to be executed by the CPU 10. However, the ROM 20 does not store a target program during debugging.

  The CS controller 30 supplies a CS (Chip Select) signal supplied by the CPU 10 to the ROM 20 when the CPU 10 executes a program stored in the ROM 20, and supplies a CS signal to the ROM emulator 2 during debugging. Therefore, during debugging, the CPU 10 accesses the memory built in the ROM emulator 2 via the connector 40.

  The connector 40 is provided on a bus connecting the CPU 10 and the ROM 20, and further connects the CPU 10 and the ROM emulator 2. As described above, the program to be debugged is downloaded to the memory built in the ROM emulator 2. The memory built in the ROM emulator 2 is rewritten (program download) from the PC 4. Further, the CPU 10 communicates with the PC 4 through a procedure compliant with JTAG through the JTAG master 3.

  In the debug system shown in FIG. 2, a program to be debugged is downloaded to a memory built in the ROM emulator 2, and control such as execution / stop of the program in the CPU 10 is performed from the PC 4 via the JTAG master 3. At that time, it is necessary to acquire data exchanged between the CPU 10 and the memory built in the ROM emulator 2 and to set arbitrary data for the CPU 10. For this reason, the CPU 10 includes a boundary scan circuit.

  Next, the boundary scan circuit will be described. FIG. 3 is a diagram illustrating a configuration example of the semiconductor integrated circuit 5 including the boundary scan circuit disclosed in Non-Patent Document 2.

  The semiconductor integrated circuit 5 shown in FIG. 3 includes an internal logic circuit 50, boundary scan registers 51 to 58, and a TAP (Test Access Port) controller 59. The boundary scan registers 51 to 58 and the TAP controller 59 constitute a boundary scan circuit.

  The boundary scan circuit shown in FIG. 3 is for enabling acquisition of data exchanged between the external terminal of the semiconductor integrated circuit 5 and the internal logic circuit 50 and setting of arbitrary data. In the semiconductor integrated circuit 5, boundary scan registers 51 to 58 are provided between the external terminal and the internal logic circuit 50. Note that the boundary scan registers 51 to 58 are connected in series, and the data held by each boundary scan register can be sequentially output to the boundary scan register of the next stage (constituting a shift register). ).

  The TAP controller 59 controls the boundary scan registers 51 to 58. For example, the TAP controller 59 controls the fetching of data in each boundary scan register and the operation of shifting the fetched data to the next-stage boundary scan register.

  Next, the boundary scan register will be described. FIG. 4 is a configuration example of the boundary scan register disclosed in Non-Patent Document 2. The boundary scan register shown in FIG. 4 is capable of bidirectional data input / output, and includes multiplexers 60 to 64, flip-flops 65 and 66, and a buffer 67. Note that H and L indicated in the multiplexers 60 to 64 indicate an input terminal selected when the input switching signal is at the H level and an input terminal selected when the input switching signal is at the L level (in the following description). The same shall apply).

  In the debugging system having the configuration shown in FIG. 2, a program to be debugged is downloaded to a memory built in the ROM emulator. Therefore, in order to debug a program, a connector 40 for connecting the CPU 10 and the ROM emulator 2 is necessary. Furthermore, a CS controller 30 for switching the CS signal output by the CPU 10 is also necessary.

  By adding the connector 40 and the CS controller 30 that are necessary only during debugging, the wiring resistance between the CPU 10 and the memory incorporated in the ROM 20 or the ROM emulator 2 increases. As a result, there arises a problem that an address signal or a data signal used when accessing the memory is delayed or reflected. This signal delay and reflection also occurs during normal operation (except during debugging). Therefore, when the CPU 10 accesses the memory, it is necessary to take a measure such as inserting a wait, which causes the memory access speed of the CPU 10 to decrease.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 5 is a diagram illustrating a configuration example of a debug system including a semiconductor integrated circuit (CPU) according to the present embodiment. In FIG. 5, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

The debug system shown in FIG. 5 includes an evaluation board 7, a JTAG master 3, and a PC 4. The PC 4 stores a program to be debugged. The evaluation board 7 includes a CPU 70 and a ROM 20.

  The CPU 70 includes a MEMC 101, a JTAG-IF 102, and a timing control circuit 103, and is a semiconductor integrated circuit that operates as a central processing unit. Comparing the debug system shown in FIG. 2 with the debug system shown in FIG. 5, it can be seen that the CS controller 30 and the connector 40 are not present on the evaluation board 7.

  FIG. 6 is a diagram illustrating an example of the internal configuration of the CPU 70. The CPU 70 illustrated in FIG. 6 includes a MEMC 101, a JTAG-IF 102, a timing control circuit 103, and boundary scan registers 104 to 106. The MEMC 101 is connected to the address / command terminal of the CPU 70 via the boundary scan register 106. Similarly, the MEMC 101 is connected to the data terminal via the boundary scan register 105 and to the wait terminal via the boundary scan register 104. Note that the address / command terminal, data terminal, and wait terminal of the CPU 70 are connected to the address terminal, data terminal, and wait terminal of the ROM 20, respectively.

  In addition, while the ROM 20 is in the wait state, no memory access from the MEMC to the ROM 20 is performed. In the debug system shown in FIG. 5, the state of the wait terminal at the time of debugging is always set to L level using a switch or the like provided on the substrate.

  The timing control circuit 103 receives a CPU_CLK serving as a reference clock from the MEMC 101 and receives a SelectA signal from the JTAG-IF 102. The SelectA signal corresponds to the mode signal described above. The timing control circuit 103 outputs the SelectB signal to the boundary scan registers 104 to 106. The SelectB signal corresponds to the control signal described above.

  The JTAG-IF 102 outputs a Scan_In1 signal to the boundary scan register 104, and outputs a Shift signal to the boundary scan registers 104 to 106. Further, the JTAG-IF 102 outputs a clock (JTAG_CLK) to the boundary scan registers 104 to 106.

  Note that the Scan_In signals input to the boundary scan registers 104 to 106 are represented as Scan_In1, Scan_In2, and Scan_In3. Similarly, the Scan_Out signals output from the boundary scan registers 104 to 106 are represented as Scan_Out1, Scan_Out2, and Scan_Out3.

  Next, the configuration of the boundary scan registers 104 to 106 will be described. Since the configuration of the boundary scan registers 104 to 106 is the same, only the boundary scan register 104 will be described. FIG. 7 is a diagram illustrating an example of the internal configuration of the boundary scan register 104.

  The boundary scan register 104 includes multiplexers 1041 and 1042 and a flip-flop 1043. The wait terminal of the CPU 70 is connected to the input terminal of the multiplexer 1041, and the output terminal of the flip-flop 1043 is connected to the other input terminal of the multiplexer 1041. The output terminal of the multiplexer 1041 is connected to the input terminal of the MEMC 101 and the input terminal of the multiplexer 1042. The signal output from the multiplexer 1041 is determined based on the SelectB signal. In addition to the output of the multiplexer 1041, the Scan_In1 signal is input to the multiplexer 1042. The signal output from the multiplexer 1042 is determined based on the Shift signal. The output terminal of the multiplexer 1042 is connected to the input terminal of the flip-flop 1043. The output terminal of the flip-flop 1043 is connected to the input terminal of the multiplexer 1041 and is output to the flip-flop 105 in the next stage as a Scan_Out1 signal of the boundary scan register 104.

  Next, a detailed configuration of the timing control circuit 103 will be described. FIG. 8 is a diagram illustrating an example of the internal configuration of the timing control circuit 103.

  The timing control circuit 103 includes flip-flops 1031 to 1033 and an AND circuit 1034. The SelectA signal output from the JTAG-IF 102 is received at the data input terminal of the flip-flop 1031. The output terminal of the flip-flop 1031 is connected to the data input terminal of the flip-flop 1032 and the input terminal of the AND circuit 1034. Further, the other input terminal of the AND circuit 1034 is connected to the inverting output terminal of the flip-flop 1032. The output terminal of the AND circuit 1034 is connected to the data input terminal of the flip-flop 1033. The SelectB signal is output from the output terminal of the flip-flop 1033. Note that CPU_CLK supplied by the MEMC 101 is input to clock terminals of the flip-flops 1031 to 1033.

  FIG. 9 is a diagram illustrating the operation of the timing control circuit 103 when one cycle of memory access is equal to one cycle of CPU_CLK. The vertical axis in FIG. 9 represents CPU_CLK, the SelectA signal, the output of the flip-flop 1031, the inverted output of the flip-flop 1032, the output of the AND circuit 1034, and the SelectB signal.

  Since the SelectA signal input during the period of time T0 to T2 is at the L level, the output of the flip-flop 1031 and the output of the AND circuit 1034 are at the L level. The inverted output of the flip-flop 1032 becomes H level. Thereafter, it is assumed that the SelectA signal has changed to the H level during the period of time T2 and T3. As a result, at time T3, the output of the flip-flop 1031 becomes H level. At the same time, the output of the AND circuit 1034 also becomes H level. Then, since the output of the flip-flop 1032 is inverted after being delayed by one clock, it becomes L level at time T4. The output of the AND circuit 1034 that has received the inverted output of the flip-flop 1032 becomes L level at time T4.

  In this way, the output of the AND circuit 1034 outputs an H level only during the period between times T3 and T4. Then, the flip-flop 1033 synchronizes the output of the AND circuit 1034 with the CPU_CLK and outputs it as a SelectB signal with a delay of one clock.

  On the other hand, if the SelectA signal transits to the L level during the period of time T7 and T8, the output of the flip-flop 1031 becomes the L level. When the output of the flip-flop 1031 becomes L level, the inverted output of the flip-flop 1032 becomes H level at time T9. The state of each signal at time T9 is the same as the state at time T0, and the above-described operation is repeated after time T9.

  Next, the operation of the debug system including the CPU 70 according to the present embodiment will be described. FIG. 10 is a diagram showing an outline of an operation when debugging is performed by a debugging system including the CPU 70.

  In step S01, an instruction to fetch data specifying an address is output from the CPU 70 to the MEMC 101. Upon receiving the instruction, the MEMC 101 outputs the designated address signal to the boundary scan register 106.

  In step S02, the data held in the boundary scan registers 104 to 106 is taken into the PC 4. In this step, the data held in each boundary scan register is sequentially sent to the next-stage boundary scan register, and the data output from the last-stage boundary scan register (boundary scan register 106) is sequentially fetched in the PC4. Here, the operation of capturing data in the boundary scan registers 104 to 106 is called the capture mode of the boundary scan register, and the operation of sequentially transmitting the data held in each boundary scan register to the boundary scan register of the next stage is performed in the boundary scan register. This is called a scan shift mode.

  In step S03, the ROM data is emulated in the PC 4 based on the fetched address signal. Further, the emulation result is generated as response data.

  In step S04, the response data generated in step S03 is set in the boundary scan registers 104 to 106.

  In step S05, the response data set in the boundary scan registers 104 to 106 is read into the MEMC 101. Here, the operation of reading data set in the boundary scan register into the MEMC is called an update mode of the boundary scan register.

  When step S05 ends, the process proceeds to step S01, and debugging of the program is continued.

  Subsequently, the operation of the CPU 70 in each step of FIG. 10 will be described. FIG. 11 is a timing chart showing the operation of each signal of the CPU 70. The vertical axis in FIG. 11 represents CPU_CLK, SelectA signal, SelectB signal, wait signal (wait terminal state), output of multiplexer 1041, Shift signal, Scan_In1 signal, output of multiplexer 1042, output of flip-flop 1043, and Scan_Out1 signal. Show.

  The period from time T0 to T2 corresponds to the capture mode described above. In the period from time T0 to time T2, the SelectA signal output from the JTAG-IF 102 is at the L level, so the SelectB signal output from the timing control circuit 103 is also at the L level. Then, the multiplexer 1041 outputs the state of the wait terminal, and since the state of the wait terminal is at the L level, the output of the multiplexer 1041 is at the L level. The MEMC 101 that has received the L level as the output of the boundary scan register 104 interprets that the wait terminal that is an external terminal of the CPU 70 is at the L level, and does not access (suspend) the memory. If the Shift signal is L level, the multiplexer 1042 selects the output (L level) of the multiplexer 1041 and outputs it to the flip-flop 1043. The flip-flop 1043 outputs the input signal (L level) to the next-stage boundary scan register 105 as a Scan_Out1 signal. In this manner, the value of the wait signal held in the boundary scan register 104 is output to the boundary scan register 105 and MEMC 101 in the next stage.

  FIG. 12 is a diagram illustrating a signal flow of the boundary scan register 104 in the capture mode. In FIG. 12, a dotted line is a signal path selected in the capture mode. As is clear from FIG. 12, the boundary scan register 104 transmits a wait signal to the MEMC 101 and outputs the information held in the flip-flop 1043 to the boundary scan register 105 in the next stage.

  Next, the scan shift mode will be described. A period from time T2 to time T3 in FIG. 11 corresponds to the above-described scan shift mode. In the scan shift mode, a signal input from the outside of the CPU 70 is transmitted to the MEMC 101, and data output from the boundary scan register at the previous stage is transmitted (shifted) to the boundary scan register at the next stage. Even during the period from time T2 to time T3, the SelectB signal is at the L level, so the wait signal is transmitted to the MEMC 101. However, in the scan shift mode, the Shift signal received by the multiplexer 1042 is at the H level, so the Scan_In1 signal is selected and output to the flip-flop 1043 at the subsequent stage. The flip-flop 1043 outputs a Scan_In1 signal as a Scan_Out1 signal in synchronization with JTAG_CLK supplied by the JTAG-IF102. In this way, by outputting the data captured by the boundary scan registers 104 to 106 to the boundary scan register of the next stage, the address signal output from the MEMC 101 and the state of the data terminal and wait terminal of the CPU 70 (finally in the PC 4) Signal).

  FIG. 13 shows the signal flow of the boundary scan register 104 in the scan shift mode, as in FIG.

  Next, the update mode will be described. The period from time T10 to time T12 in FIG. 11 corresponds to the update mode described above. In the update mode, the data (response data) set in the boundary scan circuit formed by the boundary scan registers 104 to 106 is read into the MEMC 101. In the update mode, the Shift signal is at the H level, and the Scan_In1 signal is selected and output as the output of the multiplexer 1042. Then, when the H level is set in the Scan_In1 signal, the H level is output to the multiplexer 1041 via the flip-flop 1043.

  On the other hand, in the timing control circuit 103, the SelectA signal changes from the L level to the H level during the period between the times T10 and T11. Based on this change, the SelectB signal becomes the H level only during the period between the times T11 and T12. . The multiplexer 1041 selects and outputs the output of the flip-flop 1043 only during the period of time T11 and T12. In this case, since the H level is set for the Scan_In1 signal, the MEMC 101 accepts the H level of the Scan_In1 signal for a period of one clock.

  The output of the boundary scan register 104 (the output of the multiplexer 1041) is interpreted as a wait signal in the MEMC 101, and it is recognized that the wait signal has changed to the H level. As a result, the MEMC 101 cancels the wait and executes memory access (data fetch). Therefore, the JTAG-IF 102 sets the data (response data) emulated by the PC 4 in the boundary scan registers 104 to 106 by time T11, so that the response data can be read into the MEMC 101.

  Further, since the SelectB signal output from the timing control circuit 103 becomes L level at time T12, the output of the multiplexer 1041 outputs the state of the wait terminal. Since the state of the wait terminal is at the L level, the memory access by the MEMC 101 is interrupted again. With the above operation, step S05 in FIG. 10 is completed. Thereafter, the process returns to step S01 to execute the next emulation. Specifically, at time T14, the L level is output as the SelectA signal from the JTAG-IF 102, and data is taken into the PC 4 until time T21. After that, by selecting the SelectA signal at the H level between times T21 and T22, the SelectB signal becomes the H level only for one cycle, and the MEMC 101 can read the data.

  FIG. 14 shows the signal flow of the boundary scan register 104 in the update mode, as in FIG.

  As described above, in the semiconductor integrated circuit including the boundary scan circuit, the timing control circuit 103 is provided, and the program can be debugged by appropriately controlling the wait signal supplied to the memory controller (MEMC 101). If the wait signal is not properly controlled, the MEMC 101 interprets that the memory can be accessed, and thus immediately starts to fetch data when the update mode by the boundary scan register ends.

  Taking the timing of FIG. 11 as an example, if the wait signal is not again output to the MEMC 101 at time T12, the MEMC determines that the memory can be accessed and starts fetching data one after another. However, the program must be emulated in the PC 4 during debugging, and data cannot be prepared immediately after time T12. Therefore, the wait signal for the MEMC 101 is controlled by the timing control circuit 103 as needed based on the L level.

  In the debugging by the ROM emulator, a dedicated connector is necessary. However, if the debugging system includes the semiconductor integrated circuit according to the present embodiment, the dedicated connector is not necessary. In the debugging method using the ROM emulator, the signal is delayed due to the influence of the additional wiring such as the connector, and there is a problem that the data cannot be read correctly unless the delay of the additional wiring is taken into consideration. In order to solve this problem, it is necessary to take measures such as changing the timing of accessing the memory (such as inserting an extra wait).

  However, in the debug system including the semiconductor integrated circuit according to the present embodiment, an operation is performed in which data is directly read via the boundary scan register, data to be returned to the MEMC 101 is created from the read data, and the MEMC 101 is read. Therefore, it is not necessary to adjust the memory access timing.

  Further, a connector or the like that is necessary only when debugging a program is unnecessary, and the cost of a product including the semiconductor integrated circuit according to the present embodiment can be reduced.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings.

  The semiconductor integrated circuit (CPU) according to the present embodiment includes a MEMC 101a that can output a signal indicating that a read access cycle is in progress. A signal (access notification signal) indicating that a read access cycle is in progress is defined as an RDZ signal. If the RDZ signal is at L level, it indicates that the MEMC 101a is in a read cycle.

  FIG. 15 is a diagram illustrating a configuration example of the timing control circuit 103a included in the CPU 70a according to the present embodiment. The timing control circuit 103a shown in FIG. 15 includes an AND circuit 1035 and an inverter 1036.

  The RDZ signal output from the MEMC 101a is input to the inverter 1036, and the output terminal of the inverter 1036 is connected to the input terminal of the AND circuit 1035. In addition, the SelectA signal output from the JTAG-IF 102 is received by another input terminal of the AND circuit 1035. Note that the difference between the CPU 70 according to the first embodiment and the CPU 70a according to the present embodiment is the MEMC 101a and the timing control circuit 103a, and other descriptions are omitted.

  FIG. 16 is a diagram illustrating the operation of the timing control circuit 103a. The vertical axis in FIG. 16 indicates CPU_CLK, the RDZ signal output from the MEMC 101a, the SelectA signal, the output of the inverter 1036, and the SelectB signal. The RDZ signal in FIG. 16 changes to the L level at time T1, and changes to the H level within the period between times T9 and T10. This means that the read cycle by the MEMC 101a continues. Then, the SelectA signal output from the JTAG-IF 102 changes to the H level at time T3. Then, since the H level output from the inverter 1036 and the H level of the SelectA signal are input to the AND circuit 1035, the SelectB signal changes to the H level at time T3. Thereafter, the RDZ signal changes to H level (the read access cycle is completed) and simultaneously the SelectB signal changes to L level.

  Thus, the SelectB signal becomes H level only during one read access of the MEMC 101a. In other words, the SelectA signal is set to the H level for the purpose of causing the MEMC 101a to capture the data held in each boundary scan register from the JTAG-IF 102, and the read access cycle of the MEMC 101a continues (the RDZ signal is L). Only during the level period), the SelectB signal is set to the H level. As a result, an update mode using a boundary scan register can be realized. Since the operation after the SelectB signal generated by the timing control circuit 103a is the same as the operation of the CPU 70 according to the first embodiment, a description thereof will be omitted.

  As described above, if the MEMC 101a can output the RDZ signal, the timing control circuit 103a can have a simple configuration.

  It should be noted that the disclosures of the above patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. For example, in the first and second embodiments, the boundary scan register has been described as a one-way type scan circuit, but a bidirectional type as shown in FIG. 4 may be employed.

1, 7 Evaluation board 2 ROM emulator 3 JTAG master 4 PC
5 Semiconductor integrated circuit 10, 70, 70a CPU
20 ROM
30 CS controller 40 Connector 50 Internal logic circuits 51-58, 104-106 Boundary scan register 59 TAP controllers 60-64, 1041, 1042 Multiplexers 65, 66, 1043, 1031-1033 Flip-flop 67 Buffer 101, 101a Memory controller 102 JTAG-IF
103, 103a Timing control circuit 1034, 1035 AND circuit 1036 Inverter

Claims (9)

A semiconductor integrated circuit capable of executing a program,
A memory controller that controls access to the memory;
A boundary scan circuit disposed between a terminal of the memory controller and an external terminal;
A JTAG interface capable of outputting a mode signal for determining an operation mode of the boundary scan circuit based on an externally applied JTAG signal;
A timing control circuit for outputting a control signal for permitting read access of the memory controller to the boundary scan circuit based on the mode signal when debugging a program;
With
The boundary scan circuit permits read access of the memory controller based on the control signal.   The semiconductor integrated circuit according to claim 1, wherein the timing control circuit permits one cycle of read access to the memory controller by the control signal. The boundary scan circuit includes a first boundary scan register disposed between a wait terminal that receives a wait signal output from the memory and the memory controller;
2. The first boundary scan register receives a signal for cutting off the wait signal and validating a read cycle of the memory controller from the JTAG interface during a period in which the timing control circuit outputs the control signal. Or 2 semiconductor integrated circuits. The boundary scan circuit further includes a second boundary scan register connected between the address terminal of the memory and the memory controller;
A third boundary scan register connected between the data terminal of the memory and the memory controller;
The semiconductor integrated circuit according to claim 3, wherein the JTAG interface receives information relating to debug shifted by the boundary scan circuit. The first to third boundary scan registers are
A first multiplexer comprising a first input terminal and a second input terminal;
A first multiplexer comprising a third input terminal and a fourth input terminal;
A flip-flop synchronized with a clock supplied by the JTAG interface;
Including
The first multiplexer is connected to the first input terminal and the external terminal, and is connected to the second input terminal and the output terminal of the flip-flop, and the first multiplexer is connected to the first multiplexer based on the control signal. Switch between the input terminal and the second input terminal,
The second multiplexer is connected to the third input terminal and the output terminal of the first multiplexer, and to the fourth input terminal and a terminal from which the JTAG interface outputs a scan-in signal. , Switching between the third input terminal and the fourth input terminal based on the Shift signal output from the JTAG interface,
The semiconductor integrated circuit according to claim 1, wherein an input terminal of the flip-flop is connected to an output terminal of the second multiplexer. The timing control circuit includes:
A second flip-flop for receiving the mode signal from a data terminal;
A third flip-flop to which an output terminal and a data terminal of the second flip-flop are connected;
A first AND circuit in which an output terminal of the second flip-flop and an inverting output terminal of the third flip-flop are connected to a first input terminal and a second input terminal, respectively;
A fourth flip-flop, wherein an output terminal of the first AND circuit is connected to a data terminal, and the control signal is output from the output terminal;
A semiconductor integrated circuit according to any one of claims 1 to 5. Furthermore, the memory controller is capable of outputting an access notification signal for notifying whether or not the memory is being accessed.
The semiconductor integrated circuit according to claim 1, wherein the timing control circuit outputs the control signal based on the mode signal and the access notification signal. The timing control circuit includes:
An inverter for inverting the access notification signal;
A second AND circuit that outputs the control signal by a logical product of the output of the inverter and the mode signal;
A semiconductor integrated circuit according to claim 7. A memory controller that controls access to the memory;
A boundary scan circuit disposed between a terminal of the memory controller and an external terminal;
A JTAG interface capable of outputting a mode signal for determining an operation mode of the boundary scan circuit based on an externally applied JTAG signal;
A semiconductor integrated circuit bus control method capable of executing a program,
When debugging a program,
Setting data in the boundary scan circuit;
A data update step of allowing the memory controller to perform a read operation based on the mode signal for a period of one cycle and causing the memory controller to read the data;
A step of prohibiting a read cycle of the memory controller after the data update step;
A method for controlling a bus of a semiconductor integrated circuit, comprising:

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