JP2012190145A - Semiconductor integrated circuit - Google Patents

Abstract

There is a risk of malfunction due to a decrease in power supply voltage supplied by a capacitor.
A semiconductor integrated circuit having a low power consumption mode that is in a power consumption state lower than a normal operation, wherein the power supply voltage level is detected in the low power consumption mode state, and the detected power supply voltage level Storage means for storing, a pseudo load means for lowering the power supply voltage by flowing a current smaller than that during the normal operation, and a first stored in the storage means before flowing current through the pseudo load means A switching means for switching the detection level of the detection means to a second voltage level according to a voltage level, and whether the power supply voltage lowered by flowing a current through the pseudo load means becomes the second voltage level. Control means for determining and controlling whether or not to release the low power consumption mode.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit.

  In the field of semiconductor integrated circuits (hereinafter referred to as LSI) mounted on battery drive devices such as remote controls, the power supply voltage of the LSI is external when the battery is removed so that the setting data of the battery drive device is not lost. The voltage charged from the attached capacitor is supplied. Normally, the remote controller holds setting data suitable for the user in the RAM, and if this setting data is lost, it becomes necessary to set the data again.

  In the case where the power supply voltage is supplied by the voltage charged from the external capacitor when the battery is removed, there is a possibility that the stored setting data may be lost if a large current is generated and the power supply voltage is lowered. Therefore, the LSI operates in a low power consumption state (hereinafter referred to as a STOP state) in which the operation of the CPU and the clocks of peripheral circuits other than the low-frequency clock for the watchdog timer are stopped so as not to lose the setting data. )It has become.

  However, if the STOP state release key is accidentally pressed when the battery is removed, the STOP state is released and the CPU and peripheral circuits operate. When the CPU and peripheral circuits are in an operating state, a large current flows, and the power supply voltage supplied by the capacitor rapidly decreases. Then, the power supply voltage becomes lower than the minimum operating voltage of the LSI, the peripheral circuit malfunctions and the value of the RAM is rewritten, or the limit voltage at which the RAM holds data (hereinafter referred to as the RAM holding voltage). If the power supply voltage is lowered to the maximum, the data set in the RAM may be lost.

  For this reason, there has been an increasing demand (necessity) for continuing a low power consumption state such as a STOP state in which the power supply voltage of the LSI is supplied by the voltage charged to the external capacitor after the battery is removed.

  There exists a thing like patent document 1 as a prior art which continues a low power consumption state. Patent Document 1 discloses a computer system having a resume function (a function that temporarily saves the state immediately before turning off the power in the memory and can resume the work immediately when the power is turned on again) for power saving. From the suspended state (the state where the operation is temporarily stopped with the data and program being left in the working state), if the battery voltage falls below the threshold value when current is passed through the pseudo load, the resume operation is stopped and the suspended state A technique for maintaining the above is disclosed.

  FIG. 9 is a block circuit diagram of the computer system 10 described in Patent Document 1. As shown in FIG. 9, the computer system 10 includes a logic circuit 12, a transistor T, and a voltage detector 20.

  The logic circuit 12 receives the resume request signal a from the operator via the input terminal 16, is given a high level or low level voltage detection signal b from the voltage detector 20, and receives a transistor T from the logic circuit 12. A control signal for turning on / off is output. A battery 18 is connected to the voltage detector 20, and a high level signal is output from the voltage detector 20 when the voltage value of the battery 18 is greater than the threshold value of the voltage detector 20, and the voltage value of the battery 18 is smaller than the threshold value. When a low level signal is output.

  For transistor T, the emitter is grounded, the base is grounded via resistor R1 and connected to logic circuit 12 via resistor R2, and the collector is connected to battery 18 and power supply circuit 22 via resistor R3. The Note that the threshold value of the voltage detector 20 is set to the minimum battery voltage value at which the power supply circuit 22 can stably supply the power supply voltage Vcc when the current required for resuming is taken out from the battery 18.

  The logic circuit 14 (not shown in FIG. 9) receives the output signal h and the voltage detection signal b of the logic circuit 12, and a signal j processed based on these signals is output from the output terminal 24 as a resume signal. Is output.

  In the computer system 10, when the resume request a is given to the input terminal 16, a high level is given to the transistor T, and the transistor T becomes conductive. When the battery (battery) voltage is below a predetermined level, the voltage detection signal b from the voltage detector 20 is at a low level, so the resume signal h is not output and the resume operation is stopped.

  As described above, the computer system of Patent Document 1 is a computer system that is driven by a battery (battery) and has a resume function. Input means for inputting a resume request in a suspended state, and compares the output voltage of the battery with a threshold value. When the resume request is input, the connection control for connecting the pseudo load to the battery if the output voltage is equal to or higher than the threshold, and prohibiting the connection of the pseudo load to the battery if the output voltage is lower than the threshold. When the output voltage is equal to or higher than the threshold when the pseudo load is connected to the battery, resume is executed, and when the output voltage is lower than the threshold, the resume control means is provided for continuing the suspended state.

JP-A-8-30349

  However, the above-described conventional technology only determines the power supply voltage based on the threshold value of the voltage detector, and stops the operation when the power supply voltage falls below the threshold value of the voltage detector, but permits the operation when the power supply voltage exceeds the threshold value. Therefore, it cannot be determined whether the power supply voltage is supplied by a battery or a capacitor.

  For this reason, when the conventional technology is applied to the remote control and the battery is removed and the supply of power supply voltage becomes a capacitor, the capacitor connected to the power supply of the remote control is about 47 μF, and thus exceeds the threshold of the voltage detector. When the operation is permitted, the CPU and peripheral circuits are in an operating state. As a result, a large current flows through the LSI, and the power supply voltage supplied by the capacitor drops sharply, becomes lower than the minimum operating voltage of the LSI, and the LSI peripheral circuit malfunctions and the RAM value is rewritten. Get up.

  Further, when the power supply voltage is lowered below the RAM holding voltage, there is a problem that data set in the RAM is lost.

  This is because in the operating state of the remote control, the voltage detection circuit detects a voltage drop, outputs a power-on clear (hereinafter referred to as POC), and resets to stop the operation, so that the infrared LED is lit. This is because the peak current consumption is about 0.5 A to 1 A, and before the POC is output, the power supply voltage rapidly decreases and becomes lower than the minimum operating voltage, resulting in malfunction.

  Here, the relationship among the minimum operating voltage, the POC voltage, and the voltage level of the RAM holding voltage will be described. The voltage relationship is “POC voltage> minimum operating voltage> RAM holding voltage”. Before reaching the minimum operating voltage, a reset is generated by POC generation to stop the operation, the RAM value is held, and there is a limit to normal operation Since it is the minimum operating voltage, the above-described relationship is established.

  The operation will be described using specific numerical values. The minimum operating voltage of the LSI is 1.4V, the RAM holding voltage is 0.9V, the POC voltage is 2.0V, the threshold voltage of the voltage detection circuit for stopping the operation is 2.1V, the pseudo load is 5Ω (400 mA), the pseudo load The calculation is performed with the ON time 100 μS, the battery removed, and a voltage of 3.2 V charged with a 47 μF capacitor.

  Before the pseudo load is turned on, the capacitor is charged with a voltage of 3.2 V, and when the voltage charged in the capacitor is calculated with a pseudo load of 5Ω (400 mA) and an ON time of 100 μS, it becomes 2.16 V. Operation is permitted because the voltage is higher than 2.1V. Although the operation starts when the operation is permitted, the power supply voltage of the LSI is lowered due to the current consumption, and POC is output. However, if the reaction time to the POC output is 200 μS, it will further drop to 0.85 V during this time. Therefore, the minimum operating voltage of the LSI is lower than 1.4V and the RAM holding voltage of 0.9V, the peripheral circuit of the LSI malfunctions and the RAM value is rewritten, and the power supply voltage is lowered to the RAM holding voltage. As a result, the data set in the RAM is lost.

  The present invention relates to a semiconductor integrated circuit having a low power consumption mode that is in a power consumption state lower than that of a normal operation, the detection means for detecting a power supply voltage level in the low power consumption mode state, and the detected power supply voltage level Storage means for storing, a pseudo load means for lowering the power supply voltage by flowing a current smaller than that during the normal operation, and a first stored in the storage means before flowing current through the pseudo load means A switching means for switching the detection level of the detection means to a second voltage level according to a voltage level, and whether the power supply voltage lowered by flowing a current through the pseudo load means becomes the second voltage level. Control means for determining and controlling whether or not to release the low power consumption mode.

  In the present invention, the power supply voltage range before flowing the current is detected by the simulated load means, and the detection level is changed to be lowered according to the detected power supply voltage level, and the current is supplied to the simulated load with a current smaller than the normal operation current. When the power supply voltage drops to the change detection level, it can be determined that the power supply voltage is supplied from, for example, a capacitor having a small power supply capability. Conversely, if the power supply voltage does not drop to the change detection level, it can be determined that a battery or the like having sufficient power supply capability is connected.

  According to the present invention, when the power supply voltage of a semiconductor integrated circuit is supplied from a capacitor or the like having a small power supply capability, it is possible to prevent a malfunction due to a drop in the power supply voltage.

1 is a block configuration of a semiconductor integrated circuit according to an embodiment. 1 is a configuration of a power supply voltage detection circuit according to an embodiment. 1 is a configuration of a power supply voltage detection level switching circuit according to an embodiment. 3 is a configuration of a voltage detection level storage circuit according to the embodiment. 3 is a configuration of a STOP cancellation control circuit according to the embodiment. It is the structure of the pseudo load circuit for power supply voltage drop concerning an embodiment. 3 is an operation timing chart of the semiconductor integrated circuit according to the embodiment. It is a table | surface of the signal level of the power supply voltage detection output which the power supply voltage detection circuit concerning Embodiment outputs. It is a structure of a prior art.

  BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows a block configuration of a semiconductor integrated circuit 1 according to the present embodiment.

  As shown in FIG. 1, the semiconductor integrated circuit 1 includes a CPU 2, a ROM 3, a memory 4, an oscillator 5, an interrupt circuit 6, a low frequency oscillator 7, a voltage detection level storage circuit 8, and a power supply voltage detection level. The switching circuit 9, the power supply voltage detection circuit 10, the low frequency clock control circuit 11, the STOP release control circuit 12, and the power supply voltage drop pseudo load circuit 13 are included.

  Each component of the semiconductor integrated circuit 1 operates at the power supply voltage VDD supplied by the battery during normal operation, and operates at the power supply voltage VDD supplied by the external capacitor 15 when the battery is removed. When the power supply voltage VDD is supplied by the capacitor 15, the power stored in the capacitor 15 is limited, so that the operation is performed in a STOP state (low power consumption mode), which will be described later, which consumes less power than in normal operation. To do.

  Further, the semiconductor integrated circuit 1 is connected to an external STOP release key 38 for releasing the STOP state. The stop release key 38 sets the STOP release key input signal S38 to low level when releasing the STOP state of the semiconductor integrated circuit 1.

  The memory 4 is expanded with programs, data, and the like that are processed by the CPU 2. The memory 4 is a volatile storage device, and when it becomes lower than the minimum operating voltage, stored data or the like cannot be retained. For example, when the semiconductor integrated circuit 1 operates with the power supply voltage VDD supplied from the external capacitor 15, the stored data is destroyed when the power supply voltage VDD supplied from the capacitor 15 decreases and becomes lower than the minimum operating voltage. there is a possibility.

  The ROM 3 is a nonvolatile storage device and holds programs, data, and the like.

  The oscillator 5 generates an operation clock during normal operation of the CPU 2, the ROM 3, the memory 4, and the like.

  The low frequency oscillator 7 generates a low frequency clock signal CLK in a STOP state (described later).

  The CPU 2 is a central processing unit and controls the system of the semiconductor integrated circuit 1. The CPU 2 performs arithmetic processing according to a program or data read from the ROM 3 or the like and developed in the memory 4. Further, a STOP signal S36 for setting the system of the semiconductor integrated circuit 1 to the STOP state is output. When the STOP signal S36 is high, the STOP state is established, and when the STOP signal S36 is low, the STOP is released.

  Here, the STOP state means that the semiconductor integrated circuit 1 is set in the low power consumption mode, so that the clock operation of the peripheral circuits of the CPU 2 such as the ROM 3 and the memory 4 is stopped by stopping the oscillator 5 and the low frequency. Only the minimum system such as the CPU 2 and the watchdog timer (not shown) is operated by the low frequency clock generated by the oscillator 7. Further, the STOP release state is a state of normal operation in which the STOP state is released.

  The interrupt circuit 6 performs interrupt control for causing the CPU 2 to enter the STOP release state in response to the STOP release signal S23.

  The power supply voltage detection circuit 10 includes resistors 16 to 25, power supply detection switch circuits 26 to 34, a reference voltage circuit 35, and comparators 36 and 37.

  Resistor 16 is connected between node N25 and ground terminal GND. Resistor 17 is connected between nodes N25 and N26. Resistor 18 is connected between nodes N26 and N27. Resistor 19 is connected between nodes N27 and N28. Resistor 20 is connected between nodes N28 and N29. Resistor 21 is connected between nodes N29 and N30. Resistor 22 is connected between nodes N30 and N31. Resistor 23 is connected between nodes N31 and N32. Resistor 24 is connected between nodes N32 and N33. The resistor 25 is connected between the node N33 and the power supply terminal VDD. The voltages that are resistance-divided by the nodes N25 to N33 are S25 to S33, respectively.

  The power detection switch circuit 26 is connected between the nodes N25 and N34, and the ON state is controlled according to the switch ON signal S5. The power detection switch circuit 27 is connected between the nodes N26 and N34, and the ON state is controlled according to the switch ON signal S6. The power detection switch circuit 28 is connected between the nodes N27 and N34, and the ON state is controlled according to the switch ON signal S7. The power detection switch circuit 29 is connected between the nodes N28 and N34, and the ON state is controlled according to the switch ON signal S8. The power detection switch circuit 30 is connected between the nodes N29 and N34, and the ON state is controlled according to the switch ON signal S9. The power detection switch circuit 31 is connected between the nodes N30 and N34, and the ON state is controlled according to the switch ON signal S10. The power detection switch circuit 32 is connected between the nodes N31 and N34, and the ON state is controlled according to the switch ON signal S11. The power detection switch circuit 33 is connected between the nodes N32 and N34, and the ON state is controlled according to the switch ON signal S12. The power detection switch circuit 34 is connected between the nodes N33 and N34, and the ON state is controlled according to the switch ON signal S13.

  Any one of the power detection switch circuits 26 to 34 is turned on in response to the switch ON signals S5 to S13. For this reason, the power supply detection voltage S34 becomes a resistance divided voltage corresponding to the turned-on power supply detection switch circuit. For example, when the power supply detection switch circuit 33 is turned on, the power supply detection voltage S34 becomes the resistance voltage division S32.

  The comparator 36 compares the voltage at the node N34 (hereinafter referred to as a power supply detection voltage) with the reference voltage S35 generated by the reference voltage circuit 35, and outputs a power supply voltage detection output S14. For example, when the reference voltage S35> the power supply detection voltage S34, the power supply voltage detection output S14 becomes a high level. On the contrary, when the reference voltage S35 <power detection voltage S34, the low level is output.

  The comparator 37 compares the voltage of the node N33 divided by the resistance with the reference voltage S35 generated by the reference voltage circuit 35, and outputs a POC output S22. For example, when the reference voltage S35> the voltage S33 of the node N33, the POC output S22 becomes a high level. Conversely, when the reference voltage S35 <the voltage S33 of the node N33, the POC output S22 becomes a low level. When the POC output S22 becomes high level, the entire system of the semiconductor integrated circuit 1 is reset (power-on-clear).

  The power supply voltage detection level switching circuit 9 includes a decode circuit 39, a voltage detection level switching selector 40, and an OR circuit 41.

  The decode circuit 39 outputs any one of the decode circuit output signals S39 to S46 as a high level in response to the register signals S2, S3, and S4. Hereinafter, the register signals S2, S3, and S4 are described as (S4, S3, and S2) as necessary. Note that “0” represents a low level and “1” represents a high level. For example, the decode circuit 39 outputs the decode circuit output signal S39 when (S4, S3, S2) = (1, 1, 1), and the decode circuit output signal S40 when (S4, S3, S2) = (1, 1, 0). , (S4, S3, S2) = (1, 0, 1), the decode circuit output signal S41, and (S4, S3, S2) = (1, 0, 0), the decode circuit output signal S42, (S4, S3, When S2) = (0, 1, 1), the decode circuit output signal S43, and when (S4, S3, S2) = (0, 1, 0), the decode circuit output signal S44, (S4, S3, S2) = (0, In the case of 0, 1), the decode circuit output signal S45 is set to a high level in the case of (S4, S3, S2) = (0, 0, 0).

  The OR circuit 41 receives the decode circuit output signals S45 and S46 and outputs an OR operation result.

  In response to the detection level switching signal S18, the voltage detection level switching selector 40 sets the values of the switch ON signals S5 to S13 to the values of the decode circuit output signals S39 to S46, the low level (GND), or the low level, the low level, respectively. The value is output as one of the values of the decode circuit output signals S39 to S44 and the output value of the OR circuit 41.

  The voltage detection level storage circuit 8 includes flip-flop circuits 42 to 45, an AND circuit 46, and inverter circuits 76 to 81.

  The flip-flop circuit 42 receives the output signal of the inverter circuit 79 at the data input terminal D, the low frequency clock CKL3 at the clock input terminal, the STOP release control reset signal S15 at the reset terminal R, and the register signal S2 from the data output terminal Q. Output.

  The flip-flop circuit 43 inputs the output signal of the inverter circuit 80 to the data input terminal D, the register signal S2 to the clock input terminal, the STOP release control reset signal S15 to the reset terminal R, and outputs the register signal S3 from the data output terminal Q. To do.

  The flip-flop circuit 44 inputs the output signal of the inverter circuit 81 to the data input terminal D, the register signal S3 to the clock input terminal, the STOP release control reset signal S15 to the reset terminal R, and outputs the register signal S4 from the data output terminal Q. To do.

  The flip-flop circuit 45 receives the high level (power supply voltage VDD) at the data input terminal D, the output of the inverter circuit 77 at the clock input terminal, the STOP release control reset signal S15 at the reset terminal R, and the signal S47 from the data output terminal Q. Is output.

  The inverter circuit 76 receives the power supply voltage detection output S14 and outputs an inverted signal thereof. The inverter circuit 77 receives the low frequency clock CLK3 and outputs an inverted signal thereof. The inverter circuit 79 receives the register signal S2 and outputs an inverted signal thereof. The inverter circuit 80 receives the register signal S3 and outputs an inverted signal thereof. The inverter circuit 81 receives the register signal S4 and outputs an inverted signal thereof.

  The AND circuit 46 receives the output of the inverter circuit 76 and the signal S47, and outputs the calculation result as a register initial value processing signal S16.

  The STOP cancellation control circuit 12 includes flip-flop circuits 55 to 59, AND circuits 53 and 54, and an inverter circuit 78.

  The AND circuit 54 receives the register initial value processing signal S16 and the low frequency clock CKL2, and outputs the calculation result as the low frequency clock CLK4.

  The flip-flop circuit 55 receives a high level (power supply voltage VDD) at the data input terminal D, a low frequency clock CLK4 at the clock input terminal, and a STOP release control reset signal S15 at the reset terminal R, and switches the detection level from the data output terminal Q. The signal S18 is output.

  The flip-flop circuit 56 receives the detection level switching signal S18 at the data input terminal D, the low frequency clock CKL2 at the clock input terminal, the STOP release control reset signal S15 at the reset terminal R, and the pseudo load ON start signal from the data output terminal Q. S20 is output.

  The flip-flop circuit 57 receives the pseudo load ON start signal S20 at the data input terminal D, the low frequency clock CKL2 at the clock input terminal, the STOP release control reset signal S15 at the reset terminal R, and the pseudo load OFF signal from the data output terminal Q. S21 is output.

  The flip-flop circuit 58 inputs the pseudo load OFF signal S21 to the data input terminal D, the low frequency clock CKL2 to the clock input terminal, the STOP release control reset signal S15 to the reset terminal R, and outputs the signal S49 from the data output terminal Q. .

  The flip-flop circuit 59 inputs the signal S49 to the data input terminal D, the low frequency clock CKL2 to the clock input terminal, the STOP cancellation control reset signal S15 to the reset terminal R, and outputs the determination processing end signal S17 from the data output terminal Q. .

  The inverter circuit 78 receives the power supply voltage detection output S14 and outputs an inverted signal thereof.

  The AND circuit 53 receives the output signal of the inverter circuit 78 and the signal S49, and outputs the calculation result as a STOP release signal S23.

  The power supply voltage drop pseudo load circuit 13 includes an AND circuit 60, a resistor 61, an NPN transistor 62, and an inverter circuit 82.

  The inverter circuit 82 receives the pseudo load OFF signal S21 and outputs an inverted signal thereof.

  The AND circuit 60 inputs the output signal of the inverter circuit 82 and the pseudo load ON start signal S20 and outputs the calculation result to the base of the NPN transistor 62.

  The resistor 61 is connected to the power supply line S24 and the collector of the NPN transistor 62. Note that the power supply voltage VDD of the capacitor 15 is supplied from the power supply wiring S24.

  In the NPN transistor 62, the collector is connected to the resistor 61, the emitter is connected to the ground terminal GND, and the output of the AND circuit 60 is input to the base. When the NPN transistor 62 is turned on, a current flows through the resistor 61. At this time, when the power supply voltage VDD is supplied only from the capacitor 15, the power supply voltage VDD decreases due to the current flowing through the resistor 61 and the NPN transistor 62. The current that flows when the NPN transistor 62 is on can be adjusted according to the resistance value of the resistor 61. The semiconductor integrated circuit 1 is adjusted so as to be limited to a current value sufficiently smaller than the current flowing from the power supply voltage VDD during normal operation.

  When the STOP signal S36 from the CPU 2 becomes high level, the low frequency clock control circuit 11 sets the STOP release control reset signal S15 to low level. When the determination process end signal S17 becomes high level, the STOP cancellation control reset signal S15 is set to high level. When the STOP release control reset signal S15 is at a high level, it is input to the reset terminals of the voltage detection level storage circuit 8 and the flip-flop circuits 42 to 45 and 55 to 59 of the STOP release control circuit 12, and the flip-flop circuits 42 to 45, 55 to 59 are initialized, and the outputs of these flip-flop circuits become low level.

  The low frequency clock control circuit 11 has a STOP release key latch. The STOP release key latch latches the STOP release key input signal S38 triggered by the fall of the STOP release key input signal S38 generated by the stop release key 38 from the high level to the low level.

  Then, the low frequency clock control circuit 11 receives a signal corresponding to the signal obtained by latching the STOP release key input signal S38, a signal synchronized with the low frequency clock CLK from the low frequency oscillator 7, and a STOP signal S36. An AND operation is performed to generate a low frequency clock CLK2. The signal corresponding to the signal obtained by latching the STOP release key input signal S38 is, for example, a signal obtained by inverting the signal obtained by latching the STOP release key input signal S38 by an inverter.

  Further, the low frequency clock control circuit 11 performs an AND operation on the low frequency clock CLK2 and a signal obtained by inverting the detection level switching signal S18 to generate a low frequency clock CLK3. For example, when the detection level switching signal S18 is at a low level, the low frequency clock CLK3 is generated, and when the detection level switching signal S18 is at a high level, the low frequency clock CLK3 is not generated and is fixed at a low level.

  Next, the operation of the semiconductor integrated circuit 1 will be described. FIG. 7 shows an example of an operation timing chart of the semiconductor integrated circuit 1. This example of the operation timing chart shows a case where the STOP is not canceled when the power supply voltage drop pseudo load circuit 13 determines the power supply voltage drop in the power supply voltage VDD range in which the power supply detection switch circuit 29 is turned on. As a premise of this example, the power supply voltage VDD is set to 3.1V.

  FIG. 8 shows a table of signal levels of the power supply voltage detection output S14 output from the power supply voltage detection circuit 10 according to the selection of the power supply voltage VDD range and the resistance divided voltages S25 to S33. In FIG. 8, “L” is described when the power supply voltage detection output S14 is output at a low level, and “H” is output when it is output at a high level.

  Time T1 in FIG. 7 is a STOP release state before entering the STOP state. Time T2 is in the STOP state. At time T3, the STOP release key is latched and the power detection switch circuit 26 at the power detection level is ON. At time T4, the power detection switch circuit 27 at the power detection level is in an ON state. At time T5, the power detection switch circuit 28 at the power detection level is in an ON state. At time T6, when the power supply detection switch circuit 28 is turned on, the power supply voltage detection output S14 changes to a low level, so that the power supply voltage VDD range before turning on the pseudo load is stored, and the power supply detection switch circuit 28 supplies the power supply detection switch. The circuit 30 is turned on and the detection level is lowered. At time T7, the pseudo load has started to be turned on. At time T8, the pseudo load is turned off. Time T9 is a state in which a determination is made according to the power supply voltage VDD detection level and a STOP cancellation signal is output. At time T10, the determination of the power supply voltage VDD is completed, the held flip-flop circuit is reset, and a STOP release key is awaited.

  First, the time T1 in the STOP release state before entering the STOP state will be described. At this time, the STOP signal S36 from the CPU 2 is at a low level, and the STOP release control reset signal S15 is at a high level. A high-level STOP release control reset signal S15 is input to the reset terminals of the voltage detection level storage circuit 8 and the flip-flop circuits 42 to 45 and 55 to 59 of the STOP release control circuit 12, and the flip-flop circuits 42 to 45, 55 to 55 59 is initialized. Therefore, register signals S2, S3, S4, signal S47, detection level switching signal S18, pseudo load ON start signal S20, pseudo load OFF signal S21, detection level determination start signal S49 after pseudo load ON, determination processing end signal S17 Becomes low level.

  Since the register signals (S4, S3, S2) = (0, 0, 0) as described above, only the decode circuit output signal S46 output from the decode circuit 39 of the power supply voltage detection level switching circuit 9 is at a high level. become. The detection level switching signal S18 is at a low level, only the switch ON signal S12 output from the voltage detection level switching selector 40 is at a high level, and only the power supply detection switch circuit 33 of the power supply voltage detection circuit 10 is turned ON.

  Here, the resistance voltage divisions S25 to S33 of the resistors 16 to 25 will be described based on a specific power supply voltage VDD.

  In the state where only the power supply detection switch circuit 33 is turned on as described above, the resistor voltage division S32 is selected and becomes the power supply detection voltage S34, and the power supply voltage VDD is 3.1 V. Therefore, as shown in FIG. S14 becomes low level.

  Then, the low-level power supply voltage detection output S14 is input to the inverter circuit 76 of the voltage detection level storage circuit 8, and the output becomes high level. The AND circuit 46 receives the output of the high level inverter circuit 76 and the output signal S47 of the low level flip-flop circuit 45, and outputs the low level register initial value processing signal S16.

  The low frequency clocks CLK2 and CLK3 from the low frequency clock control circuit 11 are output in the STOP state, and become low level at the timing of time T1. Further, since the detection level determination start signal S49 after turning on the pseudo load input to the two-input AND circuit 53 of the STOP cancellation control circuit 12 is low level, the STOP cancellation signal S23 is low level.

  Since the pseudo load ON start signal S20 input to the AND circuit 60 of the power supply voltage drop pseudo load circuit 13 is at the low level, the pseudo load ON signal S50 that is the output of the AND circuit 60 is also at the low level. The NPN transistor 62 is in an OFF state in which no current flows because the pseudo load ON signal S50 is at a low level.

  Next, the state at time T2 when the STOP state is set will be described. First, before time T2, a high-level STOP signal S36 is output from the CPU 2, and the semiconductor integrated circuit 1 enters the STOP state. Then, the STOP cancellation control reset signal S15 changes from the high level to the low level. In this STOP state, the battery is removed, and the semiconductor integrated circuit 1 operates at the power supply voltage VDD using only the capacitor 15 (the state shown in the block diagram of FIG. 1).

  In this state, the switch of the STOP release key 38 is pressed, and the STOP release key input signal S38 changes from the high level to the low level. The STOP release key 38 is normally pulled up to a high level. In the prior art, when the power supply voltage is supplied by the capacitor but the STOP state is released by the STOP release key, the power supply voltage supplied by the capacitor is lowered, causing the device to malfunction. Had occurred.

  Then, the STOP cancellation key input signal S38 is latched with the falling edge of the STOP cancellation key input signal S38 to the low level as a trigger. A low-frequency clock generated by ANDing the signal corresponding to the signal obtained by latching the STOP release key input signal S38, the signal synchronized with the low-frequency clock CLK, and the STOP signal S36 at the time T2. CLK2 is output from the low-frequency clock control circuit 11.

  Further, the low frequency clock control circuit 11 outputs a low frequency clock CLK3 created by performing an AND operation on the low frequency clock CLK2 and a signal obtained by inverting the detection level switching signal S18.

  At the rising edge of the low frequency clock CLK3, the flip-flop circuit 42 of the voltage detection level storage circuit 8 latches the inverted signal of the register signal S2 output from the inverter circuit 79 at time T2. Therefore, the output register signal S2 transits from the low level to the high level. Thereafter, the output level of the register signal S2 is inverted every time the low frequency clock CLK2 rises.

  The flip-flop circuit 43 latches the inverted signal of the register signal S3 output from the inverter circuit 80 at the rising edge of the register signal S2. Therefore, the output register signal S3 transitions from the low level to the high level. Thereafter, the output level of the register signal S3 is inverted every time the register signal S2 rises. That is, the output level is inverted every two rises of the low frequency clock CLK2.

  The flip-flop circuit 44 latches the inverted signal of the register signal S4 output from the inverter circuit 81 at the rising edge of the register signal S3. Therefore, the output register signal S4 transitions from the low level to the high level. The output level of the register signal S4 is inverted every time the register signal S3 rises thereafter. That is, the output level is inverted every four rises of the low frequency clock CLK2.

  At time T2, (S4, S3, S2) = (1, 1, 1), and only the decode circuit output signal S39 becomes the high level as the output signal of the decode circuit 39 of the power supply voltage detection level switching circuit 9. For this reason, only the switch ON signal S5 output from the voltage detection level switching selector 40 becomes the high level.

  Since only the switch ON signal S5 becomes high level, only the power supply detection switch circuit 26 of the power supply voltage detection circuit 10 is turned ON, and the resistance voltage division S25 is selected. Here, since the power supply voltage VDD is 3.1 V, the power supply voltage detection output S14 transitions from the low level to the high level from FIG.

  The flip-flop circuit 45 of the voltage detection level storage circuit 8 inputs the low frequency clock CLK3 to the clock input terminal via the inverter circuit 77. For this reason, at the timing of time T2, the falling clock is input to the clock input terminal of the flip-flop circuit 45, the high level of the data input terminal D is not taken in, and the output signal S47 remains at the low level. Therefore, at the timing of time T2, the change of the register initial value processing signal S16 to the high level during the period when the power supply voltage detection output S14 is output at the low level is stopped.

  Then, after a half clock of the low frequency clock CLK from the timing of the time T2, it rises and is input to the clock input terminal of the flip-flop circuit 45 via the inverter circuit 77, and the flip-flop circuit 45 takes in the high level data. For this reason, the signal S47 changes from the low level to the high level. The register initial value processing signal S16 output from the AND circuit 46 that ANDs the signal S47 and the output of the inverter circuit 76 remains at the low level until the pressure detection output S14 changes from the high level to the low level.

  Next, the time T3 when the power detection switch circuit 26 at the power detection level is ON will be described.

  At the timing of time T3, the low frequency clock CLK3 input to the flip-flop circuit 42 of the voltage detection level storage circuit 8 rises, and the low level data output from the inverter circuit 79 is latched. Therefore, the register signal S2 transits from the high level to the low level, and (S4, S3, S2) = (1, 1, 0).

  As a result, only the decode circuit output signal S40 becomes the high level as the output signal of the decode circuit 39 of the power supply voltage detection level switching circuit 9. For this reason, only the switch ON signal S6 output from the voltage detection level switching selector 40 becomes the high level.

  Since only the switch ON signal S6 becomes high level, only the power supply detection switch circuit 27 of the power supply voltage detection circuit 10 is turned ON, and the resistance voltage division S26 is selected. Here, since the power supply voltage VDD is 3.1 V, the power supply voltage detection output S14 remains at the high level from FIG. 8, and the register initial value processing signal S16 also remains at the low level.

  Next, the time T4 when the power detection switch circuit 27 at the power detection level is in the ON state will be described.

  Also at the timing of time T4, the low frequency clock CLK3 input to the flip-flop circuit 42 rises, and the high level data output from the inverter circuit 79 is latched. For this reason, the register signal S2 transits from the low level to the high level, and the flip-flop circuit 43 latches the low level data output from the inverter circuit 79. Therefore, (S4, S3, S2) = (1, 0, 1), and the output signal of the decode circuit 39 of the power supply voltage detection level switching circuit 9 is high only in the decode circuit output signal S41. For this reason, only the switch ON signal S7 output from the voltage detection level switching selector 40 becomes the high level.

  Since only the switch ON signal S7 is at a high level, only the power supply detection switch circuit 28 of the power supply voltage detection circuit 10 is turned ON, and the resistance voltage divider S27 is selected. Here, since the power supply voltage VDD is 3.1 V, the power supply voltage detection output S14 remains at the high level from FIG. 8, and the register initial value processing signal S16 also remains at the low level.

  Next, time T5 when the power detection switch circuit 28 at the power detection level is in the ON state will be described.

  Even at the timing of time T5, the low-frequency clock CLK3 input to the flip-flop circuit 42 rises, and the low-level data output from the inverter circuit 79 is latched. For this reason, the register signal S2 changes from the high level to the low level, and (S4, S3, S2) = (1, 0, 0).

  As a result, only the decode circuit output signal S42 becomes the high level as the output signal of the decode circuit 39 of the power supply voltage detection level switching circuit 9. For this reason, only the switch ON signal S8 output from the voltage detection level switching selector 40 becomes the high level.

  Since only the switch ON signal S8 is at a high level, only the power supply detection switch circuit 29 of the power supply voltage detection circuit 10 is turned ON, and the resistance voltage division S28 is selected. Here, since the power supply voltage VDD is 3.1 V, the power supply voltage detection output S14 transitions from the high level to the low level from FIG.

  Next, when the power supply detection switch circuit 28 is in an ON state, the power supply voltage detection output S14 is changed to a low level so that the range of the power supply voltage VDD before the pseudo load is turned on is stored, and the power supply detection switch circuit 30 is turned on and detected. The time T6 when the level is lowered will be described. The time T6 is the timing at which the power supply voltage detection output S14 described above transitions from the high level to the low level.

  The power supply voltage detection output S14 becomes low level, and the register initial value processing signal S16 output from the AND circuit 46 changes from low level to high level. The register initial value processing signal S16 is input to the AND circuit 54 of the STOP cancellation control circuit 12. Since the AND circuit 54 receives the low frequency clock CLK2 at one input, the AND circuit 54 outputs the low frequency clock CLK4 at the timing of time T6 when the register initial value processing signal S16 transits to the high level.

  The low-frequency clock CLK4 is input to the clock input terminal of the flip-flop circuit 55, and the flip-flop circuit 55 latches high-level data at the rising timing of the low-frequency clock CLK4. For this reason, the detection level switching signal S18, which is the output of the flip-flop circuit 55, transitions from the low level to the high level. When the detection level switching signal S18 becomes high level, the low frequency clock CLK3 output from the low frequency clock control circuit 11 is fixed at low level.

  When the low frequency clock CLK3 is fixed at the low level, the value of the register signal S2 output from the flip-flop circuit 42 of the voltage detection level storage circuit 8 is also fixed. Further, the value of the register signal S3 output from the flip-flop circuit 43 and the value of the register signal S4 output from the flip-flop circuit 44 are also fixed, and (S4, S3, S2) = (1, 0, 0). . This state is a state in which the range of the power supply voltage VDD before the current is passed through the pseudo load of the power supply voltage drop pseudo load circuit 13 is detected and stored.

  Since (S4, S3, S2) = (1, 0, 0) is fixed and only the decode circuit output signal S42 is at a high level, the detection level switching signal S18 is at a high level. The selector of the selector 40 is switched. For this reason, only the switch ON signal S10 output from the voltage detection level switching selector 40 is switched to a high level state. Then, the power supply detection switch circuit 31 is turned on by the switch ON signal S10, and the resistance voltage division S30 is selected.

  The resistance voltage division S30 is selected, and from FIG. 8, the limit voltage of the low level of the power supply voltage detection output S14 becomes “2.8V ≧ VDD> 2.6V”. This state is a change level that is lowered in accordance with the power supply voltage level stored before the power supply voltage VDD is lowered to determine whether the power supply voltage VDD is lowered after the current is passed through the pseudo load.

  Next, the time T7 when the pseudo load is turned on will be described.

  In the STOP cancellation control circuit 12, the flip-flop circuit 56 latches the high level of the detection level switching signal S18 at the timing of time T7 by the rising edge of the low frequency clock CLK2. For this reason, the pseudo load ON start signal S20 changes from the low level to the high level.

  As the pseudo load ON start signal S20 transitions from the low level to the high level, the pseudo load ON signal S50, which is the output of the AND circuit 60 of the power supply voltage drop pseudo load circuit 13, becomes high level, and the NPN transistor 62 is turned on. For this reason, a current limited by the resistor 61 connected to the power supply wiring S24 flows.

  Next, time T8 in a state where the pseudo load is turned off will be described.

  At the timing of time T8, the flip-flop circuit 57 latches the high level of the pseudo load ON start signal S20. For this reason, the pseudo load OFF signal S21 transits from the low level to the high level.

  When the pseudo load OFF signal S21 transits from a low level to a high level, the pseudo load ON signal S50, which is the output of the AND circuit 60 of the power supply voltage drop pseudo load circuit 13, becomes a low level, whereby the NPN transistor 62 is turned off, and the current Stop flowing.

  Here, since the semiconductor integrated circuit 1 operates only with the voltage supplied by the capacitor 15, the power supply voltage VDD decreases from 3.1V. When the power supply voltage VDD decreases to “2.8V ≧ VDD> 2.6V” during the period of time T7 to T8, the power supply voltage detection output S14 becomes high level. At this time, since the detection level determination start signal S49 after turning on the pseudo load input to the AND circuit 53 of the STOP cancellation control circuit 12 is at the low level, the STOP cancellation signal S23 is at the low level.

  Next, the time T9 in which the determination is made according to the power supply voltage detection level and the STOP release signal S23 is output will be described.

  At the timing of time T9, the flip-flop circuit 58 latches the high level of the pseudo load OFF signal S21. For this reason, the detection level determination start signal S49 after the pseudo load is turned on shifts from the low level to the high level.

  Since the power supply voltage detection output S14 is at a high level, the detection level determination start signal S49 after the pseudo load is turned on transitions from the low level to the high level, so that the STOP release signal S23 that is the output of the AND circuit 53 remains at the low level. Become. For this reason, no interrupt operation is generated for the interrupt circuit 6, the STOP signal S36 from the CPU 2 is kept at a high level, and the STOP is not released.

  This is because it is determined that the power supply voltage VDD is supplied only by the capacitor 15 because the power supply voltage VDD is lowered to the lowered change detection level, and control is performed without releasing the STOP.

  Next, the time T10 when the determination of the power supply voltage VDD is completed, the held flip-flop circuit is reset, and a STOP release key is waited for will be described.

  At the timing of time T10, the flip-flop circuit 59 latches the high level of the detection level determination start signal S49 after the pseudo load is turned on. For this reason, the determination processing end signal S17 changes from the low level to the high level.

  Since the determination processing end signal S17 transits from the low level to the high level, the STOP cancellation control reset signal S15 output from the low frequency clock control circuit 11 becomes the high level. The STOP release control reset signal S15 becomes high level, and the flip-flop circuits 42 to 44, 55 to 59 are reset, initialized, and returned to the state of waiting for STOP release.

  In the period from time T7 to time T8, when the power supply voltage VDD does not decrease to “2.8V ≧ VDD> 2.6V” even after the pseudo load is turned on, the power supply voltage detection output S14 is at a low level. Then, when the detection level determination start signal S49 after the pseudo load is turned on becomes high level, the STOP release signal S23 becomes high level. A high-level STOP cancellation signal S23 is input to the interrupt circuit 6, and the STOP signal S36 from the CPU 2 becomes low level to cancel the STOP state.

  This is because the power supply voltage VDD does not drop to the lowered change detection level, so that it is determined that the power supply voltage VDD is not supplied only by the capacitor 15 (the battery is connected), and the STOP is released. Is to do.

  In addition, when the power supply voltage VDD is low from the beginning before the current flows in the pseudo load, for example, when the power supply voltage VDD is 2.3 V, it is close to the voltage of 2.0 V at which POC (power on clear) occurs. By supplying a current, the power supply voltage VDD is lowered to 2.0 V or less (provided that it is higher than the minimum operating voltage of the semiconductor integrated circuit 1), and the POC output S22 is set to the high level. By setting the POC output S22 to the high level, the CPU 2 and peripheral circuits in the semiconductor integrated circuit 1 are initialized, the oscillator 5 and the low-frequency oscillator 7 are stopped, the memory 4 stops accessing, and the volatile memory The RAM is in a state where data is held (hereinafter referred to as a reset state).

  Here, an example of setting a detection level for determining whether or not the power supply voltage VDD drops after flowing a current with a pseudo load will be described. The capacitor 15 is C, the pseudo load of the combined resistance of the NPN transistor 62 and the resistor 61 is R, and the time during which a current is flowing through the pseudo load is t. Then, the relational expression where the voltage level before flowing current with the pseudo load is V0 and the detection level to be lowered is V is as follows.

  V = V0 × exp (−t / (R × C))

  At this time, when t = 2 mS, R = 300Ω, V0 = 3.1 V, and C = 47 μF,

  V = 3.1V × exp (−2 mS / (300Ω × 47 μF)) = 2.69, which is about 0.4 V lower than V0. Therefore, the detection level for determining whether the power supply voltage VDD has dropped after the current is passed through the pseudo load R is set to a detection level that is about 0.4 V lower than the power supply voltage VDD before the current is passed through the pseudo load R. To do.

  The semiconductor integrated circuit 1 according to the present embodiment as described above has an effect of preventing malfunction caused by a decrease in power supply voltage when the battery is removed and the power supply voltage VDD is supplied from the capacitor 15.

  As described above, this is because the power supply voltage level before flowing current with the pseudo load is detected, the detection level is lowered according to the detected power supply voltage VDD, and the power supply voltage VDD is lowered with respect to the lowered detection level. In this case, it is determined that the power supply voltage VDD is supplied by the capacitor and the STOP is not released.

  In the prior art, the power supply voltage is determined only by the threshold value of the voltage detector. When the power supply voltage falls below the threshold value of the voltage detector, the operation is stopped, but when it exceeds the threshold value, the operation is permitted. It was not possible to determine whether the voltage was supplied by a battery or a capacitor. For this reason, in the prior art, even though the power supply voltage is supplied by the capacitor, the same amount of electricity as that in the normal operation is consumed, and the data set in the RAM or the like is lost due to a decrease in the voltage. Was happening.

  However, the semiconductor integrated circuit 1 of the present embodiment can determine whether the power supply voltage is supplied by a battery or a capacitor by the above function, and does not cancel the STOP state when supplied by a capacitor. For this reason, it is possible to avoid the problem that the data set in the RAM or the like is lost without causing a decrease in the power supply voltage, which has been a problem in the prior art.

  Furthermore, there is an effect that it is possible to lengthen the data holding time stored in the memory with the battery removed. This is because the current flowing through the pseudo load circuit is reduced in order to determine whether the capacitor 15 is connected to the power supply voltage VDD.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1 Semiconductor integrated circuit 2 CPU
3 ROM
4 Memory 5 Oscillator 6 Interrupt circuit 7 Low frequency oscillator 8 Voltage detection level storage circuit 9 Power supply voltage detection level switching circuit 10 Power supply voltage detection circuit 11 Low frequency clock control circuit 12 STOP release control circuit 13 Pseudo load circuit for power supply voltage drop

Claims (10)

A semiconductor integrated circuit having a low power consumption mode which is a lower power consumption state than a normal operation,
In the low power consumption mode state,
Detection means for detecting a power supply voltage level;
Storage means for storing the detected power supply voltage level;
Pseudo load means for lowering the power supply voltage by flowing a current smaller than that during normal operation;
Switching means for switching the detection level of the detection means to a second voltage level in accordance with the first voltage level stored in the storage means before passing a current through the pseudo load means;
Control means for determining whether or not the power supply voltage lowered by flowing current through the pseudo load means becomes the second voltage level, and controlling whether or not to release the low power consumption mode; A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, wherein the power supply voltage is supplied by a battery during the normal operation, and is supplied by a capacitor during the low power consumption mode. A low-frequency oscillator that generates a low-frequency operation clock that is an operation clock of the semiconductor integrated circuit in the low-power consumption mode at a frequency lower than the operation clock during the normal operation;
The low-frequency clock control means for outputting the low-frequency operation clock as the first and second clocks in response to a release key signal from an external release key generation means. Semiconductor integrated circuit. The storage means
A register that generates a register signal that transitions from a first value to a second value in response to the first clock;
A first latch circuit for generating a first signal in response to the first clock;
The semiconductor integrated circuit according to claim 3, further comprising: a first logic circuit that generates a processing signal in accordance with the first signal and a voltage detection output generated by the detection unit. The switching means is
A decode circuit for generating a decode circuit output signal in accordance with the value of the register signal from the storage means;
5. A selector for switching from the decode circuit output signal corresponding to the first value to the decode circuit output signal corresponding to the second value in response to a detection level switching signal from the control means. A semiconductor integrated circuit according to 1. The detection means includes
A plurality of resistors connected in series between the supply terminal of the power supply voltage and a ground terminal;
A switch circuit that selects one of a plurality of resistance divided voltages obtained by dividing the power supply voltage by the plurality of resistors in response to the switch signal from the switching means;
A reference voltage generation circuit for generating a reference voltage;
The semiconductor integrated circuit according to claim 5, further comprising: a comparator that compares the reference voltage with a resistance voltage selected by the switch circuit and generates the voltage detection output according to the comparison result. The control means includes
A second latch circuit for generating the detection level switching signal based on a third clock signal corresponding to the processing signal generated by the storage means and a second clock from the low frequency clock control means;
A third latch circuit for generating a pseudo load on signal in response to the detection level switching signal;
A fourth latch circuit for generating a pseudo load off signal S21 in response to the pseudo load on signal;
A fifth latch circuit for generating a detection level determination start signal S49 in response to the pseudo load off signal;
The semiconductor integrated circuit according to claim 6, further comprising: a second logic circuit that generates a release signal S23 according to the detection level determination start signal S49 and the voltage detection output. The pseudo load means includes
A supply line to which the power supply voltage is supplied, a pseudo resistor connected in series between a ground terminal, and a transistor;
8. The semiconductor integrated circuit according to claim 7, wherein the transistor is turned on in response to the pseudo load on signal and turned off in response to the pseudo load off signal. 9. The semiconductor integrated circuit according to claim 8, wherein the low frequency clock control means stops the first clock in response to the detection level switching signal from the control means. 9. The semiconductor integrated circuit according to claim 8, further comprising an interrupt control unit that performs an interrupt process for canceling the low power consumption mode in response to the cancel signal from the control means.

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