JP2012190888A - Manufacturing method of electrooptical device - Google Patents

Abstract

An electro-optical device manufacturing method capable of forming a field effect transistor by controlling the impurity distribution in a semiconductor layer by a new parameter.
In forming a pixel transistor made of a field effect transistor having an LDD structure on one surface 10s of a substrate body 10w, an impurity introduction step is performed for introducing an impurity into a semiconductor layer 1a on the one surface 10s side. Thereafter, in the impurity diffusion step, a heating device 9 such as a laser annealing device, a heat gas annealing device, or a lamp annealing device is provided on the one surface 10s side.
20 and the semiconductor layer 1a in a state where the temperature on the one surface 10s side is higher than that on the other surface 10t side.
Heat.
[Selection] Figure 4

Description

The present invention relates to a method for manufacturing an electro-optical device having a field effect transistor on one surface of a substrate body of an element substrate for an electro-optical device.

In an electro-optical device such as a liquid crystal device or an organic electroluminescence device, pixels each including a pixel electrode are arranged in a matrix, and each of the plurality of pixels includes a pixel transistor including a field effect transistor. (See Patent Document 1).

When forming such a field effect transistor, generally, an impurity is introduced into a semiconductor layer provided on one surface of an element substrate, and then the element substrate is heated in a heating furnace to remove the impurity in the thickness direction of the semiconductor layer. An impurity diffusion step (activation step) is performed for diffusing the silicon.

JP 2010-96966 A

In electro-optical devices, it is well known that the display quality changes depending on the transistor characteristics of the field effect transistor, and it is also known that the impurity distribution in the semiconductor layer of the field effect transistor affects the transistor characteristics. . For example, in a liquid crystal device among electro-optical devices, if a particular pixel has a low resistance of a field effect transistor (pixel transistor), only the pixel has a high luminance state. In addition, if the off-leakage current of the field effect transistor is large, it may cause flicker or the like.

In view of the above problems, an object of the present invention is to provide a method for manufacturing an electro-optical device capable of forming a field effect transistor by controlling an impurity distribution in a semiconductor layer with a new parameter. .

In order to solve the above-described problems, a method for manufacturing an electro-optical device according to the present invention includes a semiconductor layer for a pixel transistor provided on one surface of the substrate body of an element substrate for an electro-optical device. An impurity introduction step of introducing impurities into the semiconductor layer, and an impurity diffusion step of diffusing the impurities in the thickness direction of the semiconductor layer by heating the semiconductor layer in a state where the temperature of the one surface is higher than that of the other surface; It is characterized by having.

In the present invention, when the semiconductor layer is heated in the impurity diffusion step, the entire substrate body is not heated uniformly, but the semiconductor layer is heated in a state where the temperature on one side is higher than that on the other side. Therefore, the difference between the temperature on the front side of the semiconductor layer (the side opposite to the side where the substrate body is located in the semiconductor layer) and the temperature on the bottom side of the semiconductor layer (the side where the substrate body is located in the semiconductor layer) is controlled. Then, the impurity distribution in the thickness direction of the semiconductor layer can be controlled. That is, conventionally, after the introduction of impurities, the impurity distribution is controlled only by the heating temperature and heating time of the semiconductor layer. According to the present invention, the temperature and bottom surface of the semiconductor layer are further controlled. The impurity distribution can also be controlled by a new parameter, the difference from the temperature on the side. Therefore, according to the present invention, the impurity distribution in the semiconductor layer can be optimized, so that the variation in transistor characteristics of the field effect transistor can be reduced and the transistor characteristics can be improved.

In particular, in the impurity introduction step, the present invention includes a first impurity introduction step of introducing the impurity into a first region of the semiconductor layer adjacent to a channel planned region overlapping with the gate electrode;
A second impurity introduction step of introducing the impurity into a second region of the semiconductor layer that is separated from the planned channel region, and an impurity dose in the first impurity introduction step is the second impurity introduction amount. It is effective when applied when the impurity dose is smaller than that in the process. That is, it is effective when applied to a field effect transistor having an LDD structure. In particular, field effect transistors with LDD structure have large variations in transistor characteristics depending on the properties of the low concentration region. Therefore, if the impurity concentration in the thickness direction in the low concentration region is optimized, the variation in transistor characteristics can be reduced. Can be improved.

In the present invention, in the impurity diffusion step, it is preferable that the one surface side is heated while the other surface side is cooled.

In the present invention, in the impurity diffusion step, for example, a method of heating the one surface side with a laser beam is adopted.

In the present invention, in the impurity diffusion step, a method of bringing a heating gas into contact with the one surface side may be employed.

In the present invention, in the impurity diffusion step, a method of heating the one surface side with an infrared lamp may be employed.

1 is a block diagram illustrating an electrical configuration of a liquid crystal device (electro-optical device) to which the present invention is applied. It is explanatory drawing of the liquid crystal panel used for the liquid crystal device to which this invention is applied. It is explanatory drawing of the pixel of the liquid crystal device to which this invention is applied. It is explanatory drawing which shows the principal part of the manufacturing process of the liquid crystal device which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the principal part of the manufacturing process of the liquid crystal device which concerns on Embodiment 2 of this invention. It is a schematic block diagram of the projection type display apparatus using the liquid crystal device to which this invention is applied.

Embodiments of the present invention will be described with reference to the drawings. In the following description, the case where the present invention is applied to a liquid crystal device and a manufacturing method thereof among various electro-optical devices will be mainly described. In the drawings referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. In addition, when the direction of the current flowing through the pixel transistor is reversed, the source and the drain are switched. In this description, the side to which the pixel electrode is connected (pixel side source / drain region) is the drain, and the data line is connected. The source side (data line side source / drain region) is the source. Further, when describing the layers formed on the element substrate, the upper layer side or the surface side means the side opposite to the side where the substrate body of the element substrate is located (the side on which the counter substrate is located), and the lower layer side means It means the side where the substrate body of the element substrate is located.

[Embodiment 1]
(overall structure)
FIG. 1 is a block diagram showing an electrical configuration of a liquid crystal device (electro-optical device) to which the present invention is applied. Note that FIG. 1 is a block diagram showing the electrical configuration to the last, and therefore the layout, such as the direction in which the capacitor lines extend, is schematically shown.

In FIG. 1, a liquid crystal device 100 according to the present embodiment includes a TN (Twisted Nematic) mode and a VA (V
ertical alignment) mode liquid crystal panel 100p. The liquid crystal panel 100p has an image display area 10a (a plurality of pixels 100a arranged in a matrix in the center area).
Pixel area). In the liquid crystal panel 100p, in the element substrate 10 (see FIG. 2 and the like) to be described later, a plurality of data lines 6a and a plurality of scanning lines 3a extend vertically and horizontally inside the image display region 10a. A pixel 100a is configured at a corresponding position. In each of the plurality of pixels 100a, a pixel transistor 30 made of a field effect transistor and a pixel electrode 9a described later are formed. The data line 6 a is electrically connected to the source of the pixel transistor 30, and the scanning line 3 is connected to the gate of the pixel transistor 30.
a is electrically connected, and the pixel electrode 9 a is electrically connected to the drain of the pixel transistor 30.

In the element substrate 10, a scanning line driving circuit 104 and a data line driving circuit 101 are provided on the outer peripheral side of the image display region 10 a. The data line driving circuit 101 is electrically connected to each data line 6a, and sequentially supplies the image signal supplied from the image processing circuit to each data line 6a. The scanning line driving circuit 104 is electrically connected to each scanning line 3a, and sequentially supplies a scanning signal to each scanning line 3a.

In each pixel 100a, the pixel electrode 9a is opposed to a common electrode formed on a counter substrate 20 (see FIG. 2 and the like), which will be described later, via a liquid crystal layer, and constitutes a liquid crystal capacitor 50a. Further, a storage capacitor 55 is added to each pixel 100a in parallel with the liquid crystal capacitor 50a in order to prevent fluctuation of the image signal held in the liquid crystal capacitor 50a. In this embodiment, in order to form the storage capacitor 55, the first electrode layer 5a straddling the plurality of pixels 100a is formed as a capacitor electrode layer. In this embodiment, the first electrode layer 5a is electrically connected to the common potential line 5c to which the common potential Vcom is applied.

(Configuration of the liquid crystal panel 100p)
FIG. 2 is an explanatory diagram of a liquid crystal panel 100p used in the liquid crystal device 100 to which the present invention is applied. FIGS. 2A and 2B show the liquid crystal panel 100p together with the respective components from the counter substrate side. FIG. 6 is a plan view and a sectional view taken along the line HH ′.

As shown in FIGS. 2A and 2B, in the liquid crystal panel 100p, the element substrate 10 and the counter substrate 20 are bonded to each other with a sealant 107 through a predetermined gap.
7 is provided in a frame shape along the outer edge of the counter substrate 20. The sealing material 107 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is mixed with a gap material such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value.

In the liquid crystal panel 100p having such a configuration, the element substrate 10 and the counter substrate 20 are both square, and the image display area 10a described with reference to FIG. 1 is provided as a square area in the approximate center of the liquid crystal panel 100p. ing. Corresponding to such a shape, the sealing material 107
Is also provided in a substantially rectangular shape, and a substantially rectangular peripheral region 10b is provided in a frame shape between the inner peripheral edge of the sealing material 107 and the outer peripheral edge of the image display region 10a. In the element substrate 10, a data line driving circuit 101 and a plurality of terminals 102 are formed along one side of the element substrate 10 outside the image display region 10 a, and scanning lines are formed along other sides adjacent to the one side. A drive circuit 104 is formed. Note that a flexible wiring board (not shown) is connected to the terminal 102, and various potentials and various signals are input to the element substrate 10 through the flexible wiring board.

As will be described in detail later, the pixel transistor 30 described with reference to FIG. 1 is provided in the image display region 10a on the one surface 10s side of the one surface 10s and the other surface 10t of the element substrate 10.
The pixel electrodes 9a electrically connected to the pixel transistors 30 are formed in a matrix, and the alignment film 16 is formed on the upper layer side of the pixel electrodes 9a.

Further, on the one surface 10s side of the element substrate 10, a dummy pixel electrode 9b (see FIG. 2B) formed simultaneously with the pixel electrode 9a is formed in the peripheral region 10b. For the dummy pixel electrode 9b, a configuration in which the dummy pixel transistor is electrically connected, a configuration in which the dummy pixel transistor is not provided, and a configuration in which the dummy pixel electrode is directly electrically connected to the wiring, or a floating state in which no potential is applied The structure which exists in is adopted. The dummy pixel electrode 9b is
When the surface on which the alignment film 16 is formed in the element substrate 10 is flattened by polishing, the height positions of the image display region 10a and the peripheral region 10b are compressed to make the surface on which the alignment film 16 is formed flat. To contribute. Further, if the dummy pixel electrode 9b is set to a predetermined potential, it is possible to prevent the disorder of the alignment of the liquid crystal molecules at the outer peripheral side end of the image display region 10a.

A common electrode 21 is formed on one side of the counter substrate 20 facing the element substrate 10, and an alignment film 26 is formed on the common electrode 21. The common electrode 21 is formed across the plurality of pixels 100a as substantially the entire surface of the counter substrate 20 or a plurality of strip electrodes. Further, a light shielding layer 108 is formed on the lower layer side of the common electrode 21 on one surface side of the counter substrate 20 facing the element substrate 10. In this embodiment, the light shielding layer 108 is formed in a frame shape extending along the outer peripheral edge of the image display region 10a, and functions as a parting. Here, the outer peripheral edge of the light shielding layer 108 is located with a gap between the inner peripheral edge of the sealing material 107 and the light shielding layer 108 and the sealing material 107 do not overlap. In the counter substrate 20, the light shielding layer 108 may be formed as a black matrix portion in an area that overlaps an inter-pixel area sandwiched between adjacent pixel electrodes 9 a.

In the liquid crystal panel 100p configured as described above, the element substrate 10 includes the sealing material 107.
An inter-substrate conduction electrode 109 is formed in a region overlapping the corner portion of the counter substrate 20 on the outer side to establish electrical continuity between the element substrate 10 and the counter substrate 20. The inter-substrate conducting material 109 a containing conductive particles is disposed on the inter-substrate conducting electrode 109, and the common electrode 21 of the counter substrate 20 is interposed via the inter-substrate conducting material 109 a and the inter-substrate conducting electrode 109. Are electrically connected to the element substrate 10 side. For this reason, the common electrode 21 is provided on the element substrate 1.
A common potential Vcom is applied from the 0 side. The sealing material 107 is provided along the outer peripheral edge of the counter substrate 20 with substantially the same width dimension. For this reason, the sealing material 107 is substantially rectangular. However, the sealing material 107 is provided so as to pass inside avoiding the inter-substrate conduction electrode 109 in a region overlapping the corner portion of the counter substrate 20, and the corner portion of the sealing material 107 has a substantially arc shape.

In the liquid crystal device 100 having such a configuration, when the pixel electrode 9a and the common electrode 21 are formed of a light-transmitting conductive film, a transmissive liquid crystal device can be configured. On the other hand, when the common electrode 21 is formed of a light-transmitting conductive film and the pixel electrode 9a is formed of a reflective conductive film, a reflective liquid crystal device can be configured. When the liquid crystal device 100 is of a reflective type, light incident from the counter substrate 20 side is modulated while being reflected by the substrate on the element substrate 10 side and emitted, thereby displaying an image. When the liquid crystal device 100 is a transmission type, the element substrate 10 and the counter substrate 20
Among them, light incident from one substrate is modulated while being transmitted through the other substrate and emitted to display an image.

The liquid crystal device 100 can be used as a color display device of an electronic device such as a mobile computer or a mobile phone. In this case, a color filter (not shown) and a protective film are formed on the counter substrate 20. In the liquid crystal device 100, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction with respect to the liquid crystal panel 100p according to the type of the liquid crystal layer 50 to be used and the normally white mode / normally black mode. The Further, the liquid crystal device 10
0 can be used as a light valve for RGB in a projection display device (liquid crystal projector) to be described later. In this case, each of the RGB liquid crystal devices 100 includes RG.
Since the light of each color separated through the dichroic mirror for B color separation is incident as projection light, a color filter is not formed.

In this embodiment, the liquid crystal device 100 is a transmissive liquid crystal device used as a RGB light valve in a projection display device described later, and light incident from the counter substrate 20 is transmitted through the element substrate 10 and emitted. The case will be mainly described. Further, in this embodiment, the liquid crystal device 100 will be described focusing on the case where the liquid crystal layer 50 includes a VA mode liquid crystal panel 100p using a nematic liquid crystal compound having a negative dielectric anisotropy.

(Specific pixel configuration)
FIG. 3 is an explanatory diagram of a pixel of the liquid crystal device 100 to which the present invention is applied, and FIGS.
FIG. 4 is a plan view of adjacent pixels in the element substrate 10 and a cross-sectional view when the liquid crystal device 100 is cut at a position corresponding to the line FF ′ in FIG. In FIG. 3A,
Scanning lines 3a = thick solid lines Semiconductor layers 1a = thin and short dotted lines Data lines 6a and drain electrodes 6b = dot-and-dash lines First electrode layer 5a and relay electrodes 5b = thin and long broken lines Second electrode layer 7a = Two-dot chain line Pixel electrode 9a = thick and short dashed line.

As shown in FIG. 3A, a rectangular pixel electrode 9a is formed on each of the plurality of pixels 100a on the element substrate 10, and the vertical and horizontal inter-pixel regions sandwiched between adjacent pixel electrodes 9a. A data line 6a and a scanning line 3a are formed along a region overlapping with 10f. More specifically, in the inter-pixel region 10f, the scanning line 3a extends along a region overlapping with the first inter-pixel region 10g extending in one direction, and in the second direction intersecting the one direction. A data line 6a extends along an area overlapping the second inter-pixel area 10h extending along the line. Each of the data line 6a and the scanning line 3a extends linearly, and a pixel transistor 30 is formed in a region where the data line 6a and the scanning line 3a intersect. On the element substrate 10, the first electrode layer 5a (capacitance electrode layer) described with reference to FIG. 1 is formed so as to overlap the data line 6a.

As shown in FIGS. 3A and 3B, the element substrate 10 is a pixel formed on the surface (one surface side) of the translucent substrate body 10w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side. The counter substrate 20 is mainly composed of an electrode 9a, a pixel transistor 30 for pixel switching, and an alignment film 16. The counter substrate 20 is a translucent substrate body 20w such as a quartz substrate or a glass substrate, and its liquid crystal layer 50.
The main electrode 21 and the alignment film 26 are mainly formed on the side surface (one surface side facing the element substrate 10).

In the element substrate 10, a scanning line 3 a made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound is formed on one surface side of the substrate body 10 w. In this embodiment, the scanning line 3 a is made of a light-shielding conductive film such as tungsten silicide (WSi), and also functions as a light-shielding film for the pixel transistor 30. In this embodiment, the scanning line 3a is made of tungsten silicide having a thickness of about 200 nm. An insulating film such as a silicon oxide film may be provided between the substrate body 10w and the scanning line 3a.

An insulating film 12 such as a silicon oxide film is formed on the upper side of the scanning line 3a on the one surface 10s side of the substrate body 10w, and the pixel transistor 30 including the semiconductor layer 1a on the surface of the insulating film 12 is formed. Is formed. In this embodiment, the insulating film 12 is, for example, a silicon oxide film formed by a plasma CVD method using tetraethoxysilane and oxygen gas, or a silicon film formed by a plasma CVD method using silane and nitrous oxide. It has a two-layer structure with an oxide film.

The pixel transistor 30 is connected to the scanning line 3a at the intersection region between the scanning line 3a and the data line 6a.
a semiconductor layer 1a oriented in the long side direction in the extending direction of a, and a gate electrode 3c extending in a direction orthogonal to the length direction of the semiconductor layer 1a and overlapping a central portion in the length direction of the semiconductor layer 1a. I have. Further, the pixel transistor 30 has a light-transmitting gate insulating layer 2 between the semiconductor layer 1a and the gate electrode 3c. The semiconductor layer 1a includes a channel region 1g opposed to the gate electrode 3c via the gate insulating layer 2, and includes a source region 1b and a drain region 1c on both sides of the channel region 1g. In this embodiment, the pixel transistor 30 has an LDD structure. Accordingly, each of the source region 1b and the drain region 1c includes the low concentration regions 1b1, 1c1 on both sides of the channel region 1g, and the low concentration regions 1b1, 1c1 are provided.
On the other hand, a high concentration region 1b2, 1c2 is provided in a region adjacent to the channel region 1g on the opposite side.

The semiconductor layer 1a is composed of a polycrystalline silicon film or the like. The gate insulating layer 2 has a two-layer structure of a first gate insulating layer 2a made of a silicon oxide film obtained by thermally oxidizing the semiconductor layer 1a and a second gate insulating layer 2b made of a silicon oxide film or the like formed by a CVD method or the like. Consists of.
The gate electrode 3c is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound, and a contact hole 12a penetrating the gate insulating layer 2 and the insulating film 12 on both sides of the semiconductor layer 1a. , 12b, is conducted to the scanning line 3a. In this embodiment, the gate electrode 3c includes a conductive polysilicon film having a thickness of about 100 nm,
It has a two-layer structure with a tungsten silicide film having a thickness of about 100 nm.

In this embodiment, when the light after passing through the liquid crystal device 100 is reflected by another member, the reflected light is incident on the semiconductor layer 1a and the pixel transistor 30 malfunctions due to the photocurrent. For the purpose of prevention, the scanning line 3a is formed of a light shielding film. However, the scanning line may be formed in the upper layer of the gate insulating layer 2 and a part thereof may be used as the gate electrode 3c. In this case, the scanning line 3a shown in FIG. 3 is formed only for light shielding.

A translucent interlayer insulating film 41 made of a silicon oxide film or the like is formed on the upper layer side of the gate electrode 3c. On the upper layer of the interlayer insulating film 41, the data line 6a and the drain electrode 6b are made of the same conductive film. Is formed. The interlayer insulating film 41 is made of, for example, a silicon oxide film formed by a plasma CVD method using silane and nitrous oxide.

The data line 6a and the drain electrode 6b are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound. In this embodiment, the data line 6a and the drain electrode 6b are formed of a titanium (Ti) film having a thickness of 20 nm, a titanium nitride (TiN) film having a thickness of 50 nm, an aluminum (Al) film having a thickness of 350 nm, and a film thickness. 150nm Ti
It has a four-layer structure in which N films are stacked in this order. The data line 6a is electrically connected to the source region 1b (data line side source / drain region) through a contact hole 41a penetrating the interlayer insulating film 41 and the gate insulating layer 2. The drain electrode 6b is a first inter-pixel region 10g
Is formed so as to partially overlap with the drain region 1c (pixel electrode side source / drain region) of the semiconductor layer 1a via a contact hole 41b penetrating the interlayer insulating film 41 and the gate insulating layer 2. It is electrically connected to the drain region 1c.

A translucent interlayer insulating film 42 made of a silicon oxide film or the like is formed on the upper side of the data line 6a and the drain electrode 6b. The interlayer insulating film 42 is made of, for example, a silicon oxide film formed by a plasma CVD method using tetraethoxysilane and oxygen gas. In this case, the film formation is performed under a temperature condition of 600 ° C. or lower, preferably 450 ° C. or lower.

On the upper layer side of the interlayer insulating film 42, the first electrode layer 5a and the relay electrode 5b are formed of the same conductive film. The first electrode layer 5a and the relay electrode 5b are made of a conductive polysilicon film,
It is made of a conductive film such as a metal silicide film, a metal film, or a metal film compound. In this form,
The first electrode layer 5a and the relay electrode 5b have an Al film with a film thickness of about 200 nm and a film thickness of 100
It has a two-layer structure with a TiN film of about nm. Similar to the data line 6a, the first electrode layer 5a extends along a region overlapping the second inter-pixel region 10h. The relay electrode 5b is formed so as to partially overlap the drain electrode 6b in a region overlapping the first inter-pixel region 10g, and is electrically connected to the drain electrode 6b through a contact hole 42a penetrating the interlayer insulating film 42. ing.

An interlayer insulating film 44 such as a silicon oxide film is formed as an etching stopper layer on the upper side of the first electrode layer 5a and the relay electrode 5b, and the interlayer insulating film 44 is formed in a region overlapping the first electrode layer 5a. An opening 44b is formed. In this embodiment, the interlayer insulating film 44 is made of a silicon oxide film or the like formed by a plasma CVD method using tetraethoxysilane and oxygen gas. In this case, the film formation is performed under a temperature condition of 600 ° C. or lower, preferably 450 ° C. or lower. Here, although not shown in FIG. 3A, the opening 44b extends along a region overlapping with the first inter-pixel region 10g starting from an intersection region between the data line 6a and the scanning line 3a. It is formed in an L shape having a portion and a portion extending from the intersection region of the data line 6a and the scanning line 3a along the region overlapping the second inter-pixel region 10h.

A translucent dielectric layer 40 is formed on the upper layer side of the interlayer insulating film 44, and a second electrode layer 7 a is formed on the upper layer side of the dielectric layer 40. The second electrode layer 7a is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound. In this embodiment, the second electrode layer 7a is made of a TiN film having a thickness of about 100 nm. Dielectric layer 40
In addition to using silicon compounds such as silicon oxide film and silicon nitride film, aluminum oxide film, titanium oxide film, tantalum oxide film, niobium oxide film, hafnium oxide film, lanthanum oxide film, zirconium oxide film, etc. A high dielectric constant dielectric layer can be used. In this case, the film formation is performed under a temperature condition of 600 ° C. or lower, preferably 450 ° C. or lower. The second electrode layer 7a includes a portion extending along a region overlapping the first inter-pixel region 10g starting from an intersection region between the data line 6a and the scanning line 3a, and an intersection region between the data line 6a and the scanning line 3a. And a portion extending along a region overlapping with the second inter-pixel region 10h. Therefore, a portion of the second electrode layer 7 a that extends along the region overlapping with the second inter-pixel region 10 h is the first electrode layer 5 a via the dielectric layer 40 in the opening 44 b of the interlayer insulating film 44. It overlaps with. Thus, in this embodiment, the first electrode layer 5a and the dielectric layer 40 are used.
The second electrode layer 7a constitutes a storage capacitor 55 in a region overlapping the first inter-pixel region 10g.

In the second electrode layer 7a, the portion extending along the region overlapping the first inter-pixel region 10g partially overlaps the relay electrode 5b and penetrates the dielectric layer 40 and the interlayer insulating film 44. It is electrically connected to the relay electrode 5b through the contact hole 44a.

A translucent interlayer insulating film 45 is formed on the upper layer side of the second electrode layer 7a, and a translucent conductive film such as an ITO (Indium Tin Oxide) film is formed on the upper layer side of the interlayer insulating film 45. A pixel electrode 9a is formed. The interlayer insulating film 45 is made of, for example, a silicon oxide film formed by a plasma CVD method using tetraethoxysilane and oxygen gas. In this case, the film formation is performed under a temperature condition of 600 ° C. or lower, preferably 450 ° C. or lower. The pixel electrode 9a partially overlaps the second electrode layer 7a in the vicinity of the intersection region between the data line 6a and the scanning line 3a, and the second electrode layer 7a is connected via a contact hole 45a penetrating the interlayer insulating film 45. Is conducting.
The surface of the interlayer insulating film 45 is a flat surface, and the pixel electrode 9a is formed on the flat surface.

An alignment film 16 is formed on the surface of the pixel electrode 9a. The alignment film 16 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In this embodiment, the alignment film 16
Are SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ ,
It is an inorganic alignment film (vertical alignment film) made of an oblique vapor deposition film such as Ta ₂ O ₅ . A light-transmitting protective film such as a silicon oxide film or a silicon nitride film is formed between the alignment film 16 and the pixel electrode 9a, and the recess formed between the pixel electrodes 9a may be filled with the protective film. is there. According to this configuration, the alignment film 16 can be formed on a flat surface.

The counter substrate 20 is made of a light-transmitting conductive film such as an ITO film on the surface of the light-transmitting substrate body 20 w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side (surface facing the element substrate 10). A common electrode 21 is formed, and an alignment film 26 is formed so as to cover the common electrode 21. Similar to the alignment film 16, the alignment film 26 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In the present embodiment, the alignment film 26 is made of SiO _x (x <2), SiO ₂ ,
It is an inorganic alignment film (vertical alignment film) made of an obliquely deposited film such as TiO ₂ , MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O ₅ . A protective film such as a silicon oxide film or a silicon nitride film may be formed between the alignment film 26 and the common electrode 21. The alignment films 16 and 26 vertically align the nematic liquid crystal compound having negative dielectric anisotropy used for the liquid crystal layer 50, so that the liquid crystal panel 1
00p operates as a normally black VA mode.

Note that the data line driving circuit 101 and the scanning line driving circuit 104 described with reference to FIGS. 1 and 2 are complementary transistor circuits each including an n-channel driving transistor and a p-channel driving transistor. Etc. are configured. Here, the driving transistor is formed by utilizing a part of the manufacturing process of the pixel transistor 30.
Therefore, the region where the data line driving circuit 101 and the scanning line driving circuit 104 are formed in the element substrate 10 also has a cross-sectional configuration substantially similar to the cross-sectional configuration shown in FIG.

(Manufacturing method of the liquid crystal device 100)
FIG. 4 is an explanatory view showing a main part of the manufacturing process of the liquid crystal device 100 according to the first embodiment of the present invention. FIGS. 4 (a), 4 (b), and 4 (c) show the first impurity introduction process. It is explanatory drawing, explanatory drawing of a 2nd impurity introduction process, and explanatory drawing of an impurity diffusion process. In addition, although the process demonstrated below is performed in the state of the large sized substrate which can take many element substrates 10, in the following description, it demonstrates as the element substrate 10 irrespective of size. In the following description, the pixel transistor 30
Is formed as an n-channel field effect transistor.

Of the manufacturing steps of the liquid crystal device 100 of the present embodiment, in the step of forming the element substrate 10, FIG.
As shown to a), the scanning line 3a, the insulating film 12, and the semiconductor layer 1 are formed on one side of the substrate body 10w.
a, After forming the gate insulating layer 2 and the gate electrode 3c, the following steps are performed.

First, an impurity introduction step for introducing impurities into the semiconductor layer 1a by a method such as ion implantation is performed.
As this impurity introduction step, in this embodiment, in the first impurity introduction step shown in FIG. 4A, in the semiconductor layer 1a, the channel planned region overlapping the gate electrode 3c (the channel region 1g shown in FIG. 3B) An n-type impurity such as phosphorus ions is introduced into the first regions 1d1, 1e1 (scheduled formation regions of the source region 1b and the drain region 1c shown in FIG. 3B) adjacent to the planned formation region with a small dose. The impurity dose at that time is, for example, 1 × 10 ¹³ / cm ^2.
It is. In the first impurity introduction step, impurities are introduced using the gate electrode 3c as a mask. Accordingly, the first regions 1d1, 1e1 are set in a self-aligned manner with respect to the gate electrode 3c. Note that the region where no impurity is introduced becomes the channel region 1g. Next, FIG.
In the second impurity introduction step shown in b), a mask 90 is formed so as to cover the gate electrode 3c wider, and in this state, the second region 1d2 separated from the planned channel region in the semiconductor layer 1a.
An n-type impurity such as phosphorus ion is introduced in a large dose with respect to 1e2. The impurity dose at that time is, for example, 1 × 10 ¹⁵ / cm ² .

Next, as shown in FIG. 4C, after the interlayer insulating film 41 is formed, an impurity diffusion step (activation step) is performed. In the impurity diffusion step, the semiconductor layer 1a is heated to a temperature of 600 ° C. or higher to diffuse the impurities in the thickness direction of the semiconductor layer 1a. As a result, of the regions into which impurities are introduced in the first impurity introduction step (first regions 1d1, 1e1), the regions where the impurities are not introduced in the second impurity introduction step are the low concentrations of the source region 1b and the drain region 1c. Region 1b1, 1
c1. Further, the regions into which impurities are introduced in the second impurity introduction step (second regions 1d2, 1e).
2) becomes the high concentration regions 1b2 and 1c2 of the source region 1b and the drain region 1c. In this way, the pixel transistor 30 composed of an n-channel field effect transistor is formed. Further, the data line driver circuit 101 and the scanning line driver circuit 104 shown in FIG.
A driver circuit transistor including a channel-type field effect transistor is formed. Note that p-channel field-effect transistors (driver circuit transistors) of the data line driver circuit 101 and the scan line driver circuit 104 can be formed by a similar method.

In this impurity diffusion step, in this embodiment, in the substrate body 10w of the element substrate 10, the semiconductor layer 1a is heated in a state where the temperature of the one surface 10s side where the semiconductor layer 1a is formed is higher than that of the other surface 10t. Impurities are diffused in the thickness direction of the semiconductor layer 1a. More specifically, the substrate body 10w is disposed on the stage 910 with the one surface 10s of the substrate body 10w facing upward, and in this state, the one surface 10s of the substrate body 10w is heated by the heating device 920.

As the heating device 920, a laser annealing device, a heat gas annealing device, a lamp annealing device, or the like can be used. The laser annealing apparatus irradiates laser light to one surface 10s of the substrate body 10w to heat the semiconductor layer 1a from the surface side. The heat gas annealing apparatus sprays a heating gas on one surface 10s of the substrate body 10w to bring the heating gas into contact with the one surface 10s, and heats the semiconductor layer 1a from the surface side. The lamp annealing apparatus irradiates one surface 10s of the substrate body 10w with infrared light to heat the semiconductor layer 1a from the surface side.

As a result, the impurities diffuse from the surface side of the semiconductor layer 1a (the side where the substrate body 10w is located in the semiconductor layer 1a) toward the bottom side (the side where the substrate body 10w is located in the semiconductor layer 1a). At this time, in this embodiment, the diffusion of impurities is controlled by a new parameter of the difference between the temperature on the surface side and the temperature on the bottom surface side of the semiconductor layer 1a in addition to the heating temperature and heating time of the semiconductor layer 1a.

After the pixel transistor 30 is formed in this way, the components described with reference to FIG. 3 and the like are formed. Since a known method can be used to form such a component, description thereof is omitted.

(Main effects of this form)
As described above, according to the method for manufacturing the liquid crystal device 100 of the present embodiment, when the semiconductor layer 1a is heated in the impurity diffusion step, the entire substrate body 10w is not heated uniformly, but the one surface 10s side is changed to the other. The semiconductor layer 1a is heated in a state where the temperature is higher than the direction 10t side. Therefore, the impurity distribution in the thickness direction of the semiconductor layer 1a can be controlled by controlling the difference between the temperature on the front surface side of the semiconductor layer 1a and the temperature on the bottom surface side of the semiconductor layer 1a. That is, conventionally, after the impurity is introduced, the impurity distribution is controlled only by the heating temperature and heating time of the semiconductor layer 1a. However, according to the present embodiment, the temperature on the surface side of the semiconductor layer 1a is further increased. The impurity distribution can also be controlled by a new parameter, the difference between the temperature on the bottom side and the temperature on the bottom side. Therefore, according to this embodiment, since the impurity distribution in the semiconductor layer 1a can be optimized, it is possible to reduce variation in transistor characteristics of the pixel transistor 30 and improve transistor characteristics.

In particular, in this embodiment, since the pixel transistor 30 (field effect transistor) is applied to the LDD structure, the effect is remarkable. That is, the field effect transistor having the LDD structure has a large variation in transistor characteristics depending on the impurity distribution in the low concentration regions 1b1, 1c1, and therefore, if the impurity concentration in the thickness direction in the low concentration regions 1b1, 1c1 is optimized. In addition, it is possible to reduce variation in transistor characteristics and improve transistor characteristics.

[Embodiment 2]
FIG. 5 is an explanatory view showing a main part of the manufacturing process of the liquid crystal device 100 according to Embodiment 2 of the present invention, and FIGS. 5A and 5B show the impurity diffusion process and the temperature control operation. It is explanatory drawing. Note that the basic configuration of the present embodiment is the same as that of the first embodiment, and a description thereof will be omitted.

Also in this embodiment, the impurity introduction step (the first impurity introduction step and the second impurity introduction step described in the first embodiment).
After performing the impurity introduction step, an impurity diffusion step (activation step) is performed. Even in the impurity diffusion step, the semiconductor layer 1a is formed in the substrate body 10w of the element substrate 10 as in the first embodiment.
The semiconductor layer 1 in a state in which the temperature of the one surface 10s side where the is formed is higher than that of the other surface 10t.
a is heated to diffuse impurities in the thickness direction of the semiconductor layer 1a.

In performing this impurity diffusion step, in this embodiment, as shown in FIG. 5A, the substrate body 10w is placed with the one surface 10s of the substrate body 10w facing upward, and the stage 940 (cooling) with a cooling device of air cooling or water cooling. The one surface 10s of the substrate body 10w is heated by the heating device 920 while cooling the other surface 10t side of the substrate body 10w. As the heating device 920, a laser annealing device, a heat gas annealing device, a lamp annealing device, or the like can be used as in the first embodiment. As the stage 940 with a cooling device, in addition to an air-cooled or water-cooled cooling device built-in, a device using heat of vaporization when a liquid is vaporized using a compressor, or a device using a Peltier element may be used. Good.

Here, the heating by the heating device 920 and the cooling by the stage 940 with a cooling device may be performed continuously. However, as shown in FIG. Cooling by the stage 940 with the apparatus may also be performed intermittently.

In this embodiment, since it is configured as described above, after introducing impurities, as in Embodiment 1,
In addition to the heating temperature and heating time of the semiconductor layer 1a, the impurity distribution can also be controlled by a new parameter of the difference between the temperature on the surface side and the temperature on the bottom surface side of the semiconductor layer 1a.
Therefore, the same effects as those of the first embodiment can be obtained, such as optimization of impurity distribution in the semiconductor layer 1a.

In this embodiment, since the stage 940 (cooling plate) with a cooling device is used, the one surface 10s of the substrate body 10w can be heated by the heating device 920 while cooling the other surface 10t side of the substrate body 10w. . Therefore, a sufficient difference can be set between the temperature on the front surface side and the temperature on the bottom surface side of the semiconductor layer 1a.

Further, as described with reference to FIG. 5B, if the heating device 920 and the stage 940 with a cooling device are turned on / off during the impurity diffusion step, the temperature on the surface side of the semiconductor layer 1a and the temperature on the bottom surface side are reduced. The difference from the temperature can be accurately controlled. Therefore, there is an effect that the impurity distribution in the semiconductor layer 1a can be further optimized.

In cooling the other surface 10t of the substrate body 10w, in addition to the configuration using the stage 940 with a cooling device, for example, when holding the substrate body 10w, the other surface 10t side is opened and the other surface 10t is cooled. A method such as blowing air may be employed.

[Other embodiments]
In the above embodiment, the example in which the present invention is applied to the transmissive liquid crystal device 100 has been described. However, the present invention may be applied to the reflective liquid crystal device 100. In the above embodiment, the example in which the present invention is applied to the liquid crystal device 100 has been described. However, the present invention may be applied to other electro-optical devices such as an organic electroluminescence device.

[Configuration example for electronic devices]
An electronic apparatus including the liquid crystal device 100 according to the above-described embodiment will be described. FIG.
It is a schematic block diagram of the projection type display apparatus using the liquid crystal device 100 to which this invention is applied, FIG.
) And (b) are respectively an explanatory diagram of a projection display device using a transmissive liquid crystal device 100 and an explanatory diagram of a projection display device using a reflective liquid crystal device 100.

(First example of projection display device)
A projection display device 110 shown in FIG. 6A is a so-called projection type projection display device that irradiates light onto a screen 111 provided on the viewer side and observes light reflected by the screen 111. . The projection display device 110 includes a light source unit 130 including a light source 112, dichroic mirrors 113 and 114, liquid crystal light valves 115 to 117 (liquid crystal device 100), a projection optical system 118, a cross dichroic prism 119, and a relay. System 120.

The light source 112 is composed of an ultrahigh pressure mercury lamp that supplies light including red light, green light, and blue light. The dichroic mirror 113 is configured to transmit red light from the light source 112 and reflect green light and blue light. The dichroic mirror 114 is configured to transmit blue light and reflect green light among the green light and the blue light reflected by the dichroic mirror 113. Thus, the dichroic mirror 113,
A color separation optical system 114 separates light emitted from the light source 112 into red light, green light, and blue light.

Here, the integrator 12 is interposed between the dichroic mirror 113 and the light source 112.
1 and the polarization conversion element 122 are arranged in order from the light source 112. Integrator 12
1 is configured to make the illuminance distribution of the light emitted from the light source 112 uniform. Further, the polarization conversion element 122 is configured to change the light from the light source 112 into polarized light having a specific vibration direction such as s-polarized light.

The liquid crystal light valve 115 is transmitted through the dichroic mirror 113 and reflected by the reflection mirror 123.
This is a transmissive liquid crystal device 100 that modulates red light reflected by the light according to an image signal. The liquid crystal light valve 115 includes a λ / 2 phase difference plate 115a, a first polarizing plate 115b, and a liquid crystal panel 115c.
And a second polarizing plate 115d. Here, the red light incident on the liquid crystal light valve 115 remains s-polarized light because the polarization of the light does not change even if it passes through the dichroic mirror 113.

The λ / 2 phase difference plate 115a is an optical element that converts s-polarized light incident on the liquid crystal light valve 115 into p-polarized light. The first polarizing plate 115b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The liquid crystal panel 115c is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to the image signal. further,
The second polarizing plate 115d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Therefore, the liquid crystal light valve 115 is configured to modulate the red light in accordance with the image signal and to emit the modulated red light toward the cross dichroic prism 119.

Note that the λ / 2 phase difference plate 115a and the first polarizing plate 115b are disposed in contact with a light-transmitting glass plate 115e that does not convert polarized light, and the λ / 2 phase difference plate 115a and the first polarizing plate 115b. It is possible to avoid distortion of 115b due to heat generation.

The liquid crystal light valve 116 is a transmissive liquid crystal device 100 that modulates green light reflected by the dichroic mirror 114 after being reflected by the dichroic mirror 113 in accordance with an image signal. Similarly to the liquid crystal light valve 115, the liquid crystal light valve 116 includes a first polarizing plate 116b, a liquid crystal panel 116c, and a second polarizing plate 116d. Green light incident on the liquid crystal light valve 116 is s-polarized light that is reflected by the dichroic mirrors 113 and 114 and then incident. The first polarizing plate 116b is a polarizing plate that blocks p-polarized light and transmits s-polarized light. The liquid crystal panel 116c is configured to convert s-polarized light into p-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to the image signal. And the 2nd polarizing plate 1
Reference numeral 16d denotes a polarizing plate that blocks s-polarized light and transmits p-polarized light. Accordingly, the liquid crystal light valve 116 is configured to modulate green light in accordance with the image signal and to emit the modulated green light toward the cross dichroic prism 119.

The liquid crystal light valve 117 is a transmissive liquid crystal device 100 that modulates blue light reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114 and then through the relay system 120 in accordance with an image signal. The liquid crystal light valve 117 is connected to the liquid crystal light valve 11.
5 and 116, the λ / 2 phase difference plate 117a, the first polarizing plate 117b, and the liquid crystal panel 117.
c and a second polarizing plate 117d. Here, since the blue light incident on the liquid crystal light valve 117 is reflected by the two reflecting mirrors 125a and 125b described later of the relay system 120 after being reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114, the s-polarized light is reflected. It has become.

The λ / 2 phase difference plate 117a is an optical element that converts s-polarized light incident on the liquid crystal light valve 117 into p-polarized light. The first polarizing plate 117b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The liquid crystal panel 117c is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to the image signal. further,
The second polarizing plate 117d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Accordingly, the liquid crystal light valve 117 is configured to modulate blue light in accordance with an image signal and to emit the modulated blue light toward the cross dichroic prism 119. The λ / 2 phase difference plate 117a and the first polarizing plate 117b are disposed in contact with the glass plate 117e.

The relay system 120 includes relay lenses 124a and 124b and reflection mirrors 125a and 125b.
And. The relay lenses 124a and 124b are provided to prevent light loss due to a long blue light path. Here, the relay lens 124a is disposed between the dichroic mirror 114 and the reflection mirror 125a. The relay lens 12
4b is disposed between the reflection mirrors 125a and 125b. The reflection mirror 125a is
The blue light transmitted through the dichroic mirror 114 and emitted from the relay lens 124a is arranged to be reflected toward the relay lens 124b. The reflection mirror 125b is arranged to reflect the blue light emitted from the relay lens 124b toward the liquid crystal light valve 117.

The cross dichroic prism 119 includes two dichroic films 119a and 119b.
Is a color synthesizing optical system in which X is orthogonally arranged in an X shape. The dichroic film 119a is a film that reflects blue light and transmits green light, and the dichroic film 119b is a film that reflects red light and transmits green light. Therefore, the cross dichroic prism 119 is configured to combine the red light, the green light, and the blue light modulated by the liquid crystal light valves 115 to 117 and emit the resultant light toward the projection optical system 118.

The light that enters the cross dichroic prism 119 from the liquid crystal light valves 115 and 117 is s-polarized light, and the cross dichroic prism 1 from the liquid crystal light valve 116.
The light incident on 19 is p-polarized light. Thus, by making the light incident on the cross dichroic prism 119 into different types of polarized light, the light incident from the liquid crystal light valves 115 to 117 in the cross dichroic prism 119 can be synthesized. Here, in general, the dichroic films 119a and 119b are excellent in s-polarized reflection transistor characteristics. Therefore, red light and blue light reflected by the dichroic films 119a and 119b are s-polarized light, and green light transmitted through the dichroic films 119a and 119b is p-polarized light. The projection optical system 118 has a projection lens (not shown) and is configured to project the light combined by the cross dichroic prism 119 onto the screen 111.

(Second example of projection display device)
A projection display device 1000 shown in FIG. 6B includes a light source unit 1021 that generates light source light, and a color separation light guide optical that separates the light source light emitted from the light source unit 1021 into three colors of red, green, and blue. Series 10
And a light modulation unit 1025 illuminated by the light source light of each color emitted from the color separation light guide optical system 1023. In addition, the projection display apparatus 1000 includes a cross dichroic prism 1027 (combining optical system) that combines image light of each color emitted from the light modulation unit 1025.
And a projection optical system 1029 that is a projection optical system for projecting the image light that has passed through the cross dichroic prism 1027 onto a screen (not shown).

In the projection display apparatus 1000, the light source unit 1021 includes a light source 1021a, a pair of fly-eye optical systems 1021d and 1021e, a polarization conversion member 1021g, and a superimposing lens 1021i. In the present embodiment, the light source unit 1021 includes a reflector 1021f having a paraboloid and emits parallel light. Fly's eye optical system 1021d, 10
21e is composed of a plurality of element lenses arranged in a matrix in a plane perpendicular to the system optical axis, and the light source light is divided by these element lenses to be individually condensed and diverged. The polarization conversion member 1021g converts the light source light emitted from the fly-eye optical system 1021e into, for example, only a p-polarized component parallel to the drawing, and supplies it to the optical path downstream optical system. Superimposing lens 1021i
The light source light that has passed through the polarization conversion member 1021g is appropriately converged as a whole, so that the plurality of liquid crystal devices 100 provided in the light modulation unit 1025 can be uniformly superimposed and illuminated.

The color separation light guide optical system 1023 includes a cross dichroic mirror 1023a, a dichroic mirror 1023b, and reflection mirrors 1023j and 1023k. In the color separation light guide optical system 1023, the substantially white light source light from the light source unit 1021 enters the cross dichroic mirror 1023a. The red (R) light reflected by one of the first dichroic mirrors 1031a constituting the cross dichroic mirror 1023a
3j is reflected through the dichroic mirror 1023b and incident side polarizing plate 1037r,
The light is incident on the red (R) liquid crystal device 100 as p-polarized light through the wire grid polarizer 1032r that transmits p-polarized light and reflects s-polarized light and the optical compensation plate 1039r.

Further, the green (G) light reflected by the first dichroic mirror 1031a is reflected by the reflecting mirror 1023j, and then also reflected by the dichroic mirror 1023b to transmit the incident-side polarizing plate 1037g and p-polarized light, and s-polarized light. Wire grid polarizer 1 that reflects light
Through 032g and the optical compensation plate 1039g, the light is incident on the liquid crystal device 100 for green (G) as p-polarized light.

On the other hand, the blue (B) light reflected by the other second dichroic mirror 1031b constituting the cross dichroic mirror 1023a is reflected by the reflection mirror 1023k and transmits the incident-side polarizing plate 1037b and the p-polarized light. Then, the light is incident on the liquid crystal device 100 for blue (B) as p-polarized light through the wire grid polarizer 1032b that reflects s-polarized light and the optical compensation plate 1039b.

Note that the optical compensation plates 1039r, 1039g, and 1039b optically compensate the characteristics of the liquid crystal layer by adjusting the polarization states of the incident light and the emitted light to the liquid crystal device 100.

In the projection display device 1000 configured as described above, in each liquid crystal device 100, the three colors of light incident through the optical compensators 1039r, 1039g, and 1039b are respectively transmitted to the respective liquid crystal devices 1.
Modulated at 00. At this time, of the modulated light emitted from the liquid crystal device 100, the s-polarized component light is reflected by the wire grid polarizers 1032r, 1032g, and 1032b, and is crossed dichroic prisms via the exit-side polarizers 1038r, 1038g, and 1038b. Incident at 1027. In the cross dichroic prism 1027, a first dielectric multilayer film 1027a and a second dielectric multilayer film 1027b intersecting in an X shape are formed, and the first dielectric multilayer film 1027a reflects R light, The other second dielectric multilayer film 1027b reflects B light. Therefore, the three colors of light are combined by the cross dichroic prism 1027 and emitted to the projection optical system 1029. The projection optical system 1029 projects the color image light synthesized by the cross dichroic prism 1027 on a screen (not shown) at a desired magnification.

(Other projection display devices)
In addition, about a projection type display apparatus, you may comprise the LED light source etc. which radiate | emit the light of each color as a light source part, and supply each color light radiate | emitted from this LED light source to another liquid crystal device. .

(Other electronic devices)
The liquid crystal device 100 to which the present invention is applied includes a mobile phone,
You may use as a direct-view type display apparatus in electronic devices, such as an information portable terminal (PDA: Personal Digital Assistants), a digital camera, a liquid crystal television, a car navigation apparatus, a videophone, a POS terminal, and a device provided with a touch panel.

1a .. semiconductor layer, 1b .. source region, 1b1, 1c1, .. low concentration region, 1b2, 1c2.
High concentration region, 1d1, 1e1, first region, 1d2, 1e2, second region, 1c ... drain region, 1g ... channel region, 9a ... pixel electrode, 10 ... element substrate, 30 ... Pixel transistor, 100 ... Liquid crystal device, 110, 1000 ... Projection type display device, 910 ...
Stage, 920 ... Heating device, 940 ... Stage with cooling device

Claims (6)

Impurity introducing step of introducing impurities into the semiconductor layer for the pixel transistor provided on the one surface and the other surface of the substrate body of the element substrate for the electro-optical device;
An impurity diffusion step of diffusing the impurities in the thickness direction of the semiconductor layer by heating the semiconductor layer in a state where the temperature of the one surface is higher than that of the other surface;
A method for manufacturing an electro-optical device. In the impurity introduction step, a first impurity introduction step for introducing the impurity into a first region adjacent to a channel planned region overlapping with the gate electrode in the semiconductor layer, and a separation from the channel planned region in the semiconductor layer. And a second impurity introduction step of introducing the impurity into the second region, wherein an impurity dose amount in the first impurity introduction step is smaller than an impurity dose amount in the second impurity introduction step. The method of manufacturing the electro-optical device according to claim 1. 3. The method of manufacturing an electro-optical device according to claim 1, wherein, in the impurity diffusion step, heating is performed from the one surface side, and the other surface side is cooled. 4. The method of manufacturing an electro-optical device according to claim 1, wherein in the impurity diffusion step, the one surface side is heated by a laser beam. 5. 4. The method of manufacturing an electro-optical device according to claim 1, wherein in the impurity diffusion step, a heating gas is brought into contact with the one surface side. 5. 4. The method of manufacturing an electro-optical device according to claim 1, wherein, in the impurity diffusion step, the one surface side is heated by an infrared lamp. 5.